wm8804.c 20 KB

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  1. /*
  2. * wm8804.c -- WM8804 S/PDIF transceiver driver
  3. *
  4. * Copyright 2010 Wolfson Microelectronics plc
  5. *
  6. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/of_device.h>
  19. #include <linux/spi/spi.h>
  20. #include <linux/regmap.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <sound/core.h>
  24. #include <sound/pcm.h>
  25. #include <sound/pcm_params.h>
  26. #include <sound/soc.h>
  27. #include <sound/initval.h>
  28. #include <sound/tlv.h>
  29. #include "wm8804.h"
  30. #define WM8804_NUM_SUPPLIES 2
  31. static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
  32. "PVDD",
  33. "DVDD"
  34. };
  35. static const struct reg_default wm8804_reg_defaults[] = {
  36. { 3, 0x21 }, /* R3 - PLL1 */
  37. { 4, 0xFD }, /* R4 - PLL2 */
  38. { 5, 0x36 }, /* R5 - PLL3 */
  39. { 6, 0x07 }, /* R6 - PLL4 */
  40. { 7, 0x16 }, /* R7 - PLL5 */
  41. { 8, 0x18 }, /* R8 - PLL6 */
  42. { 9, 0xFF }, /* R9 - SPDMODE */
  43. { 10, 0x00 }, /* R10 - INTMASK */
  44. { 18, 0x00 }, /* R18 - SPDTX1 */
  45. { 19, 0x00 }, /* R19 - SPDTX2 */
  46. { 20, 0x00 }, /* R20 - SPDTX3 */
  47. { 21, 0x71 }, /* R21 - SPDTX4 */
  48. { 22, 0x0B }, /* R22 - SPDTX5 */
  49. { 23, 0x70 }, /* R23 - GPO0 */
  50. { 24, 0x57 }, /* R24 - GPO1 */
  51. { 26, 0x42 }, /* R26 - GPO2 */
  52. { 27, 0x06 }, /* R27 - AIFTX */
  53. { 28, 0x06 }, /* R28 - AIFRX */
  54. { 29, 0x80 }, /* R29 - SPDRX1 */
  55. { 30, 0x07 }, /* R30 - PWRDN */
  56. };
  57. struct wm8804_priv {
  58. struct regmap *regmap;
  59. struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
  60. struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
  61. };
  62. static int txsrc_get(struct snd_kcontrol *kcontrol,
  63. struct snd_ctl_elem_value *ucontrol);
  64. static int txsrc_put(struct snd_kcontrol *kcontrol,
  65. struct snd_ctl_elem_value *ucontrol);
  66. /*
  67. * We can't use the same notifier block for more than one supply and
  68. * there's no way I can see to get from a callback to the caller
  69. * except container_of().
  70. */
  71. #define WM8804_REGULATOR_EVENT(n) \
  72. static int wm8804_regulator_event_##n(struct notifier_block *nb, \
  73. unsigned long event, void *data) \
  74. { \
  75. struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
  76. disable_nb[n]); \
  77. if (event & REGULATOR_EVENT_DISABLE) { \
  78. regcache_mark_dirty(wm8804->regmap); \
  79. } \
  80. return 0; \
  81. }
  82. WM8804_REGULATOR_EVENT(0)
  83. WM8804_REGULATOR_EVENT(1)
  84. static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
  85. static const SOC_ENUM_SINGLE_EXT_DECL(txsrc, txsrc_text);
  86. static const struct snd_kcontrol_new wm8804_snd_controls[] = {
  87. SOC_ENUM_EXT("Input Source", txsrc, txsrc_get, txsrc_put),
  88. SOC_SINGLE("TX Playback Switch", WM8804_PWRDN, 2, 1, 1),
  89. SOC_SINGLE("AIF Playback Switch", WM8804_PWRDN, 4, 1, 1)
  90. };
  91. static int txsrc_get(struct snd_kcontrol *kcontrol,
  92. struct snd_ctl_elem_value *ucontrol)
  93. {
  94. struct snd_soc_codec *codec;
  95. unsigned int src;
  96. codec = snd_kcontrol_chip(kcontrol);
  97. src = snd_soc_read(codec, WM8804_SPDTX4);
  98. if (src & 0x40)
  99. ucontrol->value.integer.value[0] = 1;
  100. else
  101. ucontrol->value.integer.value[0] = 0;
  102. return 0;
  103. }
  104. static int txsrc_put(struct snd_kcontrol *kcontrol,
  105. struct snd_ctl_elem_value *ucontrol)
  106. {
  107. struct snd_soc_codec *codec;
  108. unsigned int src, txpwr;
  109. codec = snd_kcontrol_chip(kcontrol);
  110. if (ucontrol->value.integer.value[0] != 0
  111. && ucontrol->value.integer.value[0] != 1)
  112. return -EINVAL;
  113. src = snd_soc_read(codec, WM8804_SPDTX4);
  114. switch ((src & 0x40) >> 6) {
  115. case 0:
  116. if (!ucontrol->value.integer.value[0])
  117. return 0;
  118. break;
  119. case 1:
  120. if (ucontrol->value.integer.value[1])
  121. return 0;
  122. break;
  123. }
  124. /* save the current power state of the transmitter */
  125. txpwr = snd_soc_read(codec, WM8804_PWRDN) & 0x4;
  126. /* power down the transmitter */
  127. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x4);
  128. /* set the tx source */
  129. snd_soc_update_bits(codec, WM8804_SPDTX4, 0x40,
  130. ucontrol->value.integer.value[0] << 6);
  131. if (ucontrol->value.integer.value[0]) {
  132. /* power down the receiver */
  133. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0x2);
  134. /* power up the AIF */
  135. snd_soc_update_bits(codec, WM8804_PWRDN, 0x10, 0);
  136. } else {
  137. /* don't power down the AIF -- may be used as an output */
  138. /* power up the receiver */
  139. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0);
  140. }
  141. /* restore the transmitter's configuration */
  142. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, txpwr);
  143. return 0;
  144. }
  145. static bool wm8804_volatile(struct device *dev, unsigned int reg)
  146. {
  147. switch (reg) {
  148. case WM8804_RST_DEVID1:
  149. case WM8804_DEVID2:
  150. case WM8804_DEVREV:
  151. case WM8804_INTSTAT:
  152. case WM8804_SPDSTAT:
  153. case WM8804_RXCHAN1:
  154. case WM8804_RXCHAN2:
  155. case WM8804_RXCHAN3:
  156. case WM8804_RXCHAN4:
  157. case WM8804_RXCHAN5:
  158. return true;
  159. default:
  160. return false;
  161. }
  162. }
  163. static int wm8804_reset(struct snd_soc_codec *codec)
  164. {
  165. return snd_soc_write(codec, WM8804_RST_DEVID1, 0x0);
  166. }
  167. static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  168. {
  169. struct snd_soc_codec *codec;
  170. u16 format, master, bcp, lrp;
  171. codec = dai->codec;
  172. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  173. case SND_SOC_DAIFMT_I2S:
  174. format = 0x2;
  175. break;
  176. case SND_SOC_DAIFMT_RIGHT_J:
  177. format = 0x0;
  178. break;
  179. case SND_SOC_DAIFMT_LEFT_J:
  180. format = 0x1;
  181. break;
  182. case SND_SOC_DAIFMT_DSP_A:
  183. case SND_SOC_DAIFMT_DSP_B:
  184. format = 0x3;
  185. break;
  186. default:
  187. dev_err(dai->dev, "Unknown dai format\n");
  188. return -EINVAL;
  189. }
  190. /* set data format */
  191. snd_soc_update_bits(codec, WM8804_AIFTX, 0x3, format);
  192. snd_soc_update_bits(codec, WM8804_AIFRX, 0x3, format);
  193. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  194. case SND_SOC_DAIFMT_CBM_CFM:
  195. master = 1;
  196. break;
  197. case SND_SOC_DAIFMT_CBS_CFS:
  198. master = 0;
  199. break;
  200. default:
  201. dev_err(dai->dev, "Unknown master/slave configuration\n");
  202. return -EINVAL;
  203. }
  204. /* set master/slave mode */
  205. snd_soc_update_bits(codec, WM8804_AIFRX, 0x40, master << 6);
  206. bcp = lrp = 0;
  207. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  208. case SND_SOC_DAIFMT_NB_NF:
  209. break;
  210. case SND_SOC_DAIFMT_IB_IF:
  211. bcp = lrp = 1;
  212. break;
  213. case SND_SOC_DAIFMT_IB_NF:
  214. bcp = 1;
  215. break;
  216. case SND_SOC_DAIFMT_NB_IF:
  217. lrp = 1;
  218. break;
  219. default:
  220. dev_err(dai->dev, "Unknown polarity configuration\n");
  221. return -EINVAL;
  222. }
  223. /* set frame inversion */
  224. snd_soc_update_bits(codec, WM8804_AIFTX, 0x10 | 0x20,
  225. (bcp << 4) | (lrp << 5));
  226. snd_soc_update_bits(codec, WM8804_AIFRX, 0x10 | 0x20,
  227. (bcp << 4) | (lrp << 5));
  228. return 0;
  229. }
  230. static int wm8804_hw_params(struct snd_pcm_substream *substream,
  231. struct snd_pcm_hw_params *params,
  232. struct snd_soc_dai *dai)
  233. {
  234. struct snd_soc_codec *codec;
  235. u16 blen;
  236. codec = dai->codec;
  237. switch (params_format(params)) {
  238. case SNDRV_PCM_FORMAT_S16_LE:
  239. blen = 0x0;
  240. break;
  241. case SNDRV_PCM_FORMAT_S20_3LE:
  242. blen = 0x1;
  243. break;
  244. case SNDRV_PCM_FORMAT_S24_LE:
  245. blen = 0x2;
  246. break;
  247. default:
  248. dev_err(dai->dev, "Unsupported word length: %u\n",
  249. params_format(params));
  250. return -EINVAL;
  251. }
  252. /* set word length */
  253. snd_soc_update_bits(codec, WM8804_AIFTX, 0xc, blen << 2);
  254. snd_soc_update_bits(codec, WM8804_AIFRX, 0xc, blen << 2);
  255. return 0;
  256. }
  257. struct pll_div {
  258. u32 prescale:1;
  259. u32 mclkdiv:1;
  260. u32 freqmode:2;
  261. u32 n:4;
  262. u32 k:22;
  263. };
  264. /* PLL rate to output rate divisions */
  265. static struct {
  266. unsigned int div;
  267. unsigned int freqmode;
  268. unsigned int mclkdiv;
  269. } post_table[] = {
  270. { 2, 0, 0 },
  271. { 4, 0, 1 },
  272. { 4, 1, 0 },
  273. { 8, 1, 1 },
  274. { 8, 2, 0 },
  275. { 16, 2, 1 },
  276. { 12, 3, 0 },
  277. { 24, 3, 1 }
  278. };
  279. #define FIXED_PLL_SIZE ((1ULL << 22) * 10)
  280. static int pll_factors(struct pll_div *pll_div, unsigned int target,
  281. unsigned int source)
  282. {
  283. u64 Kpart;
  284. unsigned long int K, Ndiv, Nmod, tmp;
  285. int i;
  286. /*
  287. * Scale the output frequency up; the PLL should run in the
  288. * region of 90-100MHz.
  289. */
  290. for (i = 0; i < ARRAY_SIZE(post_table); i++) {
  291. tmp = target * post_table[i].div;
  292. if (tmp >= 90000000 && tmp <= 100000000) {
  293. pll_div->freqmode = post_table[i].freqmode;
  294. pll_div->mclkdiv = post_table[i].mclkdiv;
  295. target *= post_table[i].div;
  296. break;
  297. }
  298. }
  299. if (i == ARRAY_SIZE(post_table)) {
  300. pr_err("%s: Unable to scale output frequency: %uHz\n",
  301. __func__, target);
  302. return -EINVAL;
  303. }
  304. pll_div->prescale = 0;
  305. Ndiv = target / source;
  306. if (Ndiv < 5) {
  307. source >>= 1;
  308. pll_div->prescale = 1;
  309. Ndiv = target / source;
  310. }
  311. if (Ndiv < 5 || Ndiv > 13) {
  312. pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
  313. __func__, Ndiv);
  314. return -EINVAL;
  315. }
  316. pll_div->n = Ndiv;
  317. Nmod = target % source;
  318. Kpart = FIXED_PLL_SIZE * (u64)Nmod;
  319. do_div(Kpart, source);
  320. K = Kpart & 0xffffffff;
  321. if ((K % 10) >= 5)
  322. K += 5;
  323. K /= 10;
  324. pll_div->k = K;
  325. return 0;
  326. }
  327. static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
  328. int source, unsigned int freq_in,
  329. unsigned int freq_out)
  330. {
  331. struct snd_soc_codec *codec;
  332. codec = dai->codec;
  333. if (!freq_in || !freq_out) {
  334. /* disable the PLL */
  335. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  336. return 0;
  337. } else {
  338. int ret;
  339. struct pll_div pll_div;
  340. ret = pll_factors(&pll_div, freq_out, freq_in);
  341. if (ret)
  342. return ret;
  343. /* power down the PLL before reprogramming it */
  344. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  345. if (!freq_in || !freq_out)
  346. return 0;
  347. /* set PLLN and PRESCALE */
  348. snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10,
  349. pll_div.n | (pll_div.prescale << 4));
  350. /* set mclkdiv and freqmode */
  351. snd_soc_update_bits(codec, WM8804_PLL5, 0x3 | 0x8,
  352. pll_div.freqmode | (pll_div.mclkdiv << 3));
  353. /* set PLLK */
  354. snd_soc_write(codec, WM8804_PLL1, pll_div.k & 0xff);
  355. snd_soc_write(codec, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
  356. snd_soc_write(codec, WM8804_PLL3, pll_div.k >> 16);
  357. /* power up the PLL */
  358. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0);
  359. }
  360. return 0;
  361. }
  362. static int wm8804_set_sysclk(struct snd_soc_dai *dai,
  363. int clk_id, unsigned int freq, int dir)
  364. {
  365. struct snd_soc_codec *codec;
  366. codec = dai->codec;
  367. switch (clk_id) {
  368. case WM8804_TX_CLKSRC_MCLK:
  369. if ((freq >= 10000000 && freq <= 14400000)
  370. || (freq >= 16280000 && freq <= 27000000))
  371. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0x80);
  372. else {
  373. dev_err(dai->dev, "OSCCLOCK is not within the "
  374. "recommended range: %uHz\n", freq);
  375. return -EINVAL;
  376. }
  377. break;
  378. case WM8804_TX_CLKSRC_PLL:
  379. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0);
  380. break;
  381. case WM8804_CLKOUT_SRC_CLK1:
  382. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0);
  383. break;
  384. case WM8804_CLKOUT_SRC_OSCCLK:
  385. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0x8);
  386. break;
  387. default:
  388. dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
  389. return -EINVAL;
  390. }
  391. return 0;
  392. }
  393. static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
  394. int div_id, int div)
  395. {
  396. struct snd_soc_codec *codec;
  397. codec = dai->codec;
  398. switch (div_id) {
  399. case WM8804_CLKOUT_DIV:
  400. snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
  401. (div & 0x3) << 4);
  402. break;
  403. default:
  404. dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
  405. return -EINVAL;
  406. }
  407. return 0;
  408. }
  409. static int wm8804_set_bias_level(struct snd_soc_codec *codec,
  410. enum snd_soc_bias_level level)
  411. {
  412. int ret;
  413. struct wm8804_priv *wm8804;
  414. wm8804 = snd_soc_codec_get_drvdata(codec);
  415. switch (level) {
  416. case SND_SOC_BIAS_ON:
  417. break;
  418. case SND_SOC_BIAS_PREPARE:
  419. /* power up the OSC and the PLL */
  420. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
  421. break;
  422. case SND_SOC_BIAS_STANDBY:
  423. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  424. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  425. wm8804->supplies);
  426. if (ret) {
  427. dev_err(codec->dev,
  428. "Failed to enable supplies: %d\n",
  429. ret);
  430. return ret;
  431. }
  432. regcache_sync(wm8804->regmap);
  433. }
  434. /* power down the OSC and the PLL */
  435. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  436. break;
  437. case SND_SOC_BIAS_OFF:
  438. /* power down the OSC and the PLL */
  439. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  440. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
  441. wm8804->supplies);
  442. break;
  443. }
  444. codec->dapm.bias_level = level;
  445. return 0;
  446. }
  447. #ifdef CONFIG_PM
  448. static int wm8804_suspend(struct snd_soc_codec *codec)
  449. {
  450. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  451. return 0;
  452. }
  453. static int wm8804_resume(struct snd_soc_codec *codec)
  454. {
  455. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  456. return 0;
  457. }
  458. #else
  459. #define wm8804_suspend NULL
  460. #define wm8804_resume NULL
  461. #endif
  462. static int wm8804_remove(struct snd_soc_codec *codec)
  463. {
  464. struct wm8804_priv *wm8804;
  465. int i;
  466. wm8804 = snd_soc_codec_get_drvdata(codec);
  467. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  468. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); ++i)
  469. regulator_unregister_notifier(wm8804->supplies[i].consumer,
  470. &wm8804->disable_nb[i]);
  471. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  472. return 0;
  473. }
  474. static int wm8804_probe(struct snd_soc_codec *codec)
  475. {
  476. struct wm8804_priv *wm8804;
  477. int i, id1, id2, ret;
  478. wm8804 = snd_soc_codec_get_drvdata(codec);
  479. codec->control_data = wm8804->regmap;
  480. ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
  481. if (ret < 0) {
  482. dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
  483. return ret;
  484. }
  485. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
  486. wm8804->supplies[i].supply = wm8804_supply_names[i];
  487. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8804->supplies),
  488. wm8804->supplies);
  489. if (ret) {
  490. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  491. return ret;
  492. }
  493. wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
  494. wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
  495. /* This should really be moved into the regulator core */
  496. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
  497. ret = regulator_register_notifier(wm8804->supplies[i].consumer,
  498. &wm8804->disable_nb[i]);
  499. if (ret != 0) {
  500. dev_err(codec->dev,
  501. "Failed to register regulator notifier: %d\n",
  502. ret);
  503. }
  504. }
  505. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  506. wm8804->supplies);
  507. if (ret) {
  508. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  509. goto err_reg_get;
  510. }
  511. id1 = snd_soc_read(codec, WM8804_RST_DEVID1);
  512. if (id1 < 0) {
  513. dev_err(codec->dev, "Failed to read device ID: %d\n", id1);
  514. ret = id1;
  515. goto err_reg_enable;
  516. }
  517. id2 = snd_soc_read(codec, WM8804_DEVID2);
  518. if (id2 < 0) {
  519. dev_err(codec->dev, "Failed to read device ID: %d\n", id2);
  520. ret = id2;
  521. goto err_reg_enable;
  522. }
  523. id2 = (id2 << 8) | id1;
  524. if (id2 != 0x8805) {
  525. dev_err(codec->dev, "Invalid device ID: %#x\n", id2);
  526. ret = -EINVAL;
  527. goto err_reg_enable;
  528. }
  529. ret = snd_soc_read(codec, WM8804_DEVREV);
  530. if (ret < 0) {
  531. dev_err(codec->dev, "Failed to read device revision: %d\n",
  532. ret);
  533. goto err_reg_enable;
  534. }
  535. dev_info(codec->dev, "revision %c\n", ret + 'A');
  536. ret = wm8804_reset(codec);
  537. if (ret < 0) {
  538. dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
  539. goto err_reg_enable;
  540. }
  541. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  542. return 0;
  543. err_reg_enable:
  544. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  545. err_reg_get:
  546. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  547. return ret;
  548. }
  549. static const struct snd_soc_dai_ops wm8804_dai_ops = {
  550. .hw_params = wm8804_hw_params,
  551. .set_fmt = wm8804_set_fmt,
  552. .set_sysclk = wm8804_set_sysclk,
  553. .set_clkdiv = wm8804_set_clkdiv,
  554. .set_pll = wm8804_set_pll
  555. };
  556. #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  557. SNDRV_PCM_FMTBIT_S24_LE)
  558. #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  559. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
  560. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
  561. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
  562. static struct snd_soc_dai_driver wm8804_dai = {
  563. .name = "wm8804-spdif",
  564. .playback = {
  565. .stream_name = "Playback",
  566. .channels_min = 2,
  567. .channels_max = 2,
  568. .rates = WM8804_RATES,
  569. .formats = WM8804_FORMATS,
  570. },
  571. .capture = {
  572. .stream_name = "Capture",
  573. .channels_min = 2,
  574. .channels_max = 2,
  575. .rates = WM8804_RATES,
  576. .formats = WM8804_FORMATS,
  577. },
  578. .ops = &wm8804_dai_ops,
  579. .symmetric_rates = 1
  580. };
  581. static struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
  582. .probe = wm8804_probe,
  583. .remove = wm8804_remove,
  584. .suspend = wm8804_suspend,
  585. .resume = wm8804_resume,
  586. .set_bias_level = wm8804_set_bias_level,
  587. .idle_bias_off = true,
  588. .controls = wm8804_snd_controls,
  589. .num_controls = ARRAY_SIZE(wm8804_snd_controls),
  590. };
  591. static const struct of_device_id wm8804_of_match[] = {
  592. { .compatible = "wlf,wm8804", },
  593. { }
  594. };
  595. MODULE_DEVICE_TABLE(of, wm8804_of_match);
  596. static struct regmap_config wm8804_regmap_config = {
  597. .reg_bits = 8,
  598. .val_bits = 8,
  599. .max_register = WM8804_MAX_REGISTER,
  600. .volatile_reg = wm8804_volatile,
  601. .cache_type = REGCACHE_RBTREE,
  602. .reg_defaults = wm8804_reg_defaults,
  603. .num_reg_defaults = ARRAY_SIZE(wm8804_reg_defaults),
  604. };
  605. #if defined(CONFIG_SPI_MASTER)
  606. static int __devinit wm8804_spi_probe(struct spi_device *spi)
  607. {
  608. struct wm8804_priv *wm8804;
  609. int ret;
  610. wm8804 = devm_kzalloc(&spi->dev, sizeof *wm8804, GFP_KERNEL);
  611. if (!wm8804)
  612. return -ENOMEM;
  613. wm8804->regmap = regmap_init_spi(spi, &wm8804_regmap_config);
  614. if (IS_ERR(wm8804->regmap)) {
  615. ret = PTR_ERR(wm8804->regmap);
  616. return ret;
  617. }
  618. spi_set_drvdata(spi, wm8804);
  619. ret = snd_soc_register_codec(&spi->dev,
  620. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  621. return ret;
  622. }
  623. static int __devexit wm8804_spi_remove(struct spi_device *spi)
  624. {
  625. struct wm8804_priv *wm8804 = spi_get_drvdata(spi);
  626. snd_soc_unregister_codec(&spi->dev);
  627. regmap_exit(wm8804->regmap);
  628. return 0;
  629. }
  630. static struct spi_driver wm8804_spi_driver = {
  631. .driver = {
  632. .name = "wm8804",
  633. .owner = THIS_MODULE,
  634. .of_match_table = wm8804_of_match,
  635. },
  636. .probe = wm8804_spi_probe,
  637. .remove = __devexit_p(wm8804_spi_remove)
  638. };
  639. #endif
  640. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  641. static __devinit int wm8804_i2c_probe(struct i2c_client *i2c,
  642. const struct i2c_device_id *id)
  643. {
  644. struct wm8804_priv *wm8804;
  645. int ret;
  646. wm8804 = devm_kzalloc(&i2c->dev, sizeof *wm8804, GFP_KERNEL);
  647. if (!wm8804)
  648. return -ENOMEM;
  649. wm8804->regmap = regmap_init_i2c(i2c, &wm8804_regmap_config);
  650. if (IS_ERR(wm8804->regmap)) {
  651. ret = PTR_ERR(wm8804->regmap);
  652. return ret;
  653. }
  654. i2c_set_clientdata(i2c, wm8804);
  655. ret = snd_soc_register_codec(&i2c->dev,
  656. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  657. if (ret != 0)
  658. goto err;
  659. return 0;
  660. err:
  661. regmap_exit(wm8804->regmap);
  662. return ret;
  663. }
  664. static __devexit int wm8804_i2c_remove(struct i2c_client *i2c)
  665. {
  666. struct wm8804_priv *wm8804 = i2c_get_clientdata(i2c);
  667. snd_soc_unregister_codec(&i2c->dev);
  668. regmap_exit(wm8804->regmap);
  669. return 0;
  670. }
  671. static const struct i2c_device_id wm8804_i2c_id[] = {
  672. { "wm8804", 0 },
  673. { }
  674. };
  675. MODULE_DEVICE_TABLE(i2c, wm8804_i2c_id);
  676. static struct i2c_driver wm8804_i2c_driver = {
  677. .driver = {
  678. .name = "wm8804",
  679. .owner = THIS_MODULE,
  680. .of_match_table = wm8804_of_match,
  681. },
  682. .probe = wm8804_i2c_probe,
  683. .remove = __devexit_p(wm8804_i2c_remove),
  684. .id_table = wm8804_i2c_id
  685. };
  686. #endif
  687. static int __init wm8804_modinit(void)
  688. {
  689. int ret = 0;
  690. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  691. ret = i2c_add_driver(&wm8804_i2c_driver);
  692. if (ret) {
  693. printk(KERN_ERR "Failed to register wm8804 I2C driver: %d\n",
  694. ret);
  695. }
  696. #endif
  697. #if defined(CONFIG_SPI_MASTER)
  698. ret = spi_register_driver(&wm8804_spi_driver);
  699. if (ret != 0) {
  700. printk(KERN_ERR "Failed to register wm8804 SPI driver: %d\n",
  701. ret);
  702. }
  703. #endif
  704. return ret;
  705. }
  706. module_init(wm8804_modinit);
  707. static void __exit wm8804_exit(void)
  708. {
  709. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  710. i2c_del_driver(&wm8804_i2c_driver);
  711. #endif
  712. #if defined(CONFIG_SPI_MASTER)
  713. spi_unregister_driver(&wm8804_spi_driver);
  714. #endif
  715. }
  716. module_exit(wm8804_exit);
  717. MODULE_DESCRIPTION("ASoC WM8804 driver");
  718. MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
  719. MODULE_LICENSE("GPL");