sp5100_tco.c 12 KB

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  1. /*
  2. * sp5100_tco : TCO timer driver for sp5100 chipsets
  3. *
  4. * (c) Copyright 2009 Google Inc., All Rights Reserved.
  5. *
  6. * Based on i8xx_tco.c:
  7. * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
  8. * Reserved.
  9. * http://www.kernelconcepts.de
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * as published by the Free Software Foundation; either version
  14. * 2 of the License, or (at your option) any later version.
  15. *
  16. * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide"
  17. */
  18. /*
  19. * Includes, defines, variables, module parameters, ...
  20. */
  21. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22. #include <linux/module.h>
  23. #include <linux/moduleparam.h>
  24. #include <linux/types.h>
  25. #include <linux/miscdevice.h>
  26. #include <linux/watchdog.h>
  27. #include <linux/init.h>
  28. #include <linux/fs.h>
  29. #include <linux/pci.h>
  30. #include <linux/ioport.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/uaccess.h>
  33. #include <linux/io.h>
  34. #include "sp5100_tco.h"
  35. /* Module and version information */
  36. #define TCO_VERSION "0.01"
  37. #define TCO_MODULE_NAME "SP5100 TCO timer"
  38. #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION
  39. /* internal variables */
  40. static u32 tcobase_phys;
  41. static void __iomem *tcobase;
  42. static unsigned int pm_iobase;
  43. static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */
  44. static unsigned long timer_alive;
  45. static char tco_expect_close;
  46. static struct pci_dev *sp5100_tco_pci;
  47. /* the watchdog platform device */
  48. static struct platform_device *sp5100_tco_platform_device;
  49. /* module parameters */
  50. #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
  51. static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
  52. module_param(heartbeat, int, 0);
  53. MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
  54. __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
  55. static bool nowayout = WATCHDOG_NOWAYOUT;
  56. module_param(nowayout, bool, 0);
  57. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"
  58. " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  59. /*
  60. * Some TCO specific functions
  61. */
  62. static void tco_timer_start(void)
  63. {
  64. u32 val;
  65. unsigned long flags;
  66. spin_lock_irqsave(&tco_lock, flags);
  67. val = readl(SP5100_WDT_CONTROL(tcobase));
  68. val |= SP5100_WDT_START_STOP_BIT;
  69. writel(val, SP5100_WDT_CONTROL(tcobase));
  70. spin_unlock_irqrestore(&tco_lock, flags);
  71. }
  72. static void tco_timer_stop(void)
  73. {
  74. u32 val;
  75. unsigned long flags;
  76. spin_lock_irqsave(&tco_lock, flags);
  77. val = readl(SP5100_WDT_CONTROL(tcobase));
  78. val &= ~SP5100_WDT_START_STOP_BIT;
  79. writel(val, SP5100_WDT_CONTROL(tcobase));
  80. spin_unlock_irqrestore(&tco_lock, flags);
  81. }
  82. static void tco_timer_keepalive(void)
  83. {
  84. u32 val;
  85. unsigned long flags;
  86. spin_lock_irqsave(&tco_lock, flags);
  87. val = readl(SP5100_WDT_CONTROL(tcobase));
  88. val |= SP5100_WDT_TRIGGER_BIT;
  89. writel(val, SP5100_WDT_CONTROL(tcobase));
  90. spin_unlock_irqrestore(&tco_lock, flags);
  91. }
  92. static int tco_timer_set_heartbeat(int t)
  93. {
  94. unsigned long flags;
  95. if (t < 0 || t > 0xffff)
  96. return -EINVAL;
  97. /* Write new heartbeat to watchdog */
  98. spin_lock_irqsave(&tco_lock, flags);
  99. writel(t, SP5100_WDT_COUNT(tcobase));
  100. spin_unlock_irqrestore(&tco_lock, flags);
  101. heartbeat = t;
  102. return 0;
  103. }
  104. /*
  105. * /dev/watchdog handling
  106. */
  107. static int sp5100_tco_open(struct inode *inode, struct file *file)
  108. {
  109. /* /dev/watchdog can only be opened once */
  110. if (test_and_set_bit(0, &timer_alive))
  111. return -EBUSY;
  112. /* Reload and activate timer */
  113. tco_timer_start();
  114. tco_timer_keepalive();
  115. return nonseekable_open(inode, file);
  116. }
  117. static int sp5100_tco_release(struct inode *inode, struct file *file)
  118. {
  119. /* Shut off the timer. */
  120. if (tco_expect_close == 42) {
  121. tco_timer_stop();
  122. } else {
  123. pr_crit("Unexpected close, not stopping watchdog!\n");
  124. tco_timer_keepalive();
  125. }
  126. clear_bit(0, &timer_alive);
  127. tco_expect_close = 0;
  128. return 0;
  129. }
  130. static ssize_t sp5100_tco_write(struct file *file, const char __user *data,
  131. size_t len, loff_t *ppos)
  132. {
  133. /* See if we got the magic character 'V' and reload the timer */
  134. if (len) {
  135. if (!nowayout) {
  136. size_t i;
  137. /* note: just in case someone wrote the magic character
  138. * five months ago... */
  139. tco_expect_close = 0;
  140. /* scan to see whether or not we got the magic character
  141. */
  142. for (i = 0; i != len; i++) {
  143. char c;
  144. if (get_user(c, data + i))
  145. return -EFAULT;
  146. if (c == 'V')
  147. tco_expect_close = 42;
  148. }
  149. }
  150. /* someone wrote to us, we should reload the timer */
  151. tco_timer_keepalive();
  152. }
  153. return len;
  154. }
  155. static long sp5100_tco_ioctl(struct file *file, unsigned int cmd,
  156. unsigned long arg)
  157. {
  158. int new_options, retval = -EINVAL;
  159. int new_heartbeat;
  160. void __user *argp = (void __user *)arg;
  161. int __user *p = argp;
  162. static const struct watchdog_info ident = {
  163. .options = WDIOF_SETTIMEOUT |
  164. WDIOF_KEEPALIVEPING |
  165. WDIOF_MAGICCLOSE,
  166. .firmware_version = 0,
  167. .identity = TCO_MODULE_NAME,
  168. };
  169. switch (cmd) {
  170. case WDIOC_GETSUPPORT:
  171. return copy_to_user(argp, &ident,
  172. sizeof(ident)) ? -EFAULT : 0;
  173. case WDIOC_GETSTATUS:
  174. case WDIOC_GETBOOTSTATUS:
  175. return put_user(0, p);
  176. case WDIOC_SETOPTIONS:
  177. if (get_user(new_options, p))
  178. return -EFAULT;
  179. if (new_options & WDIOS_DISABLECARD) {
  180. tco_timer_stop();
  181. retval = 0;
  182. }
  183. if (new_options & WDIOS_ENABLECARD) {
  184. tco_timer_start();
  185. tco_timer_keepalive();
  186. retval = 0;
  187. }
  188. return retval;
  189. case WDIOC_KEEPALIVE:
  190. tco_timer_keepalive();
  191. return 0;
  192. case WDIOC_SETTIMEOUT:
  193. if (get_user(new_heartbeat, p))
  194. return -EFAULT;
  195. if (tco_timer_set_heartbeat(new_heartbeat))
  196. return -EINVAL;
  197. tco_timer_keepalive();
  198. /* Fall through */
  199. case WDIOC_GETTIMEOUT:
  200. return put_user(heartbeat, p);
  201. default:
  202. return -ENOTTY;
  203. }
  204. }
  205. /*
  206. * Kernel Interfaces
  207. */
  208. static const struct file_operations sp5100_tco_fops = {
  209. .owner = THIS_MODULE,
  210. .llseek = no_llseek,
  211. .write = sp5100_tco_write,
  212. .unlocked_ioctl = sp5100_tco_ioctl,
  213. .open = sp5100_tco_open,
  214. .release = sp5100_tco_release,
  215. };
  216. static struct miscdevice sp5100_tco_miscdev = {
  217. .minor = WATCHDOG_MINOR,
  218. .name = "watchdog",
  219. .fops = &sp5100_tco_fops,
  220. };
  221. /*
  222. * Data for PCI driver interface
  223. *
  224. * This data only exists for exporting the supported
  225. * PCI ids via MODULE_DEVICE_TABLE. We do not actually
  226. * register a pci_driver, because someone else might
  227. * want to register another driver on the same PCI id.
  228. */
  229. static DEFINE_PCI_DEVICE_TABLE(sp5100_tco_pci_tbl) = {
  230. { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
  231. PCI_ANY_ID, },
  232. { 0, }, /* End of list */
  233. };
  234. MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
  235. /*
  236. * Init & exit routines
  237. */
  238. static unsigned char __devinit sp5100_tco_setupdevice(void)
  239. {
  240. struct pci_dev *dev = NULL;
  241. u32 val;
  242. /* Match the PCI device */
  243. for_each_pci_dev(dev) {
  244. if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
  245. sp5100_tco_pci = dev;
  246. break;
  247. }
  248. }
  249. if (!sp5100_tco_pci)
  250. return 0;
  251. /* Request the IO ports used by this driver */
  252. pm_iobase = SP5100_IO_PM_INDEX_REG;
  253. if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, "SP5100 TCO")) {
  254. pr_err("I/O address 0x%04x already in use\n", pm_iobase);
  255. goto exit;
  256. }
  257. /* Find the watchdog base address. */
  258. outb(SP5100_PM_WATCHDOG_BASE3, SP5100_IO_PM_INDEX_REG);
  259. val = inb(SP5100_IO_PM_DATA_REG);
  260. outb(SP5100_PM_WATCHDOG_BASE2, SP5100_IO_PM_INDEX_REG);
  261. val = val << 8 | inb(SP5100_IO_PM_DATA_REG);
  262. outb(SP5100_PM_WATCHDOG_BASE1, SP5100_IO_PM_INDEX_REG);
  263. val = val << 8 | inb(SP5100_IO_PM_DATA_REG);
  264. outb(SP5100_PM_WATCHDOG_BASE0, SP5100_IO_PM_INDEX_REG);
  265. /* Low three bits of BASE0 are reserved. */
  266. val = val << 8 | (inb(SP5100_IO_PM_DATA_REG) & 0xf8);
  267. if (!request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
  268. "SP5100 TCO")) {
  269. pr_err("mmio address 0x%04x already in use\n", val);
  270. goto unreg_region;
  271. }
  272. tcobase_phys = val;
  273. tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE);
  274. if (tcobase == 0) {
  275. pr_err("failed to get tcobase address\n");
  276. goto unreg_mem_region;
  277. }
  278. /* Enable watchdog decode bit */
  279. pci_read_config_dword(sp5100_tco_pci,
  280. SP5100_PCI_WATCHDOG_MISC_REG,
  281. &val);
  282. val |= SP5100_PCI_WATCHDOG_DECODE_EN;
  283. pci_write_config_dword(sp5100_tco_pci,
  284. SP5100_PCI_WATCHDOG_MISC_REG,
  285. val);
  286. /* Enable Watchdog timer and set the resolution to 1 sec. */
  287. outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
  288. val = inb(SP5100_IO_PM_DATA_REG);
  289. val |= SP5100_PM_WATCHDOG_SECOND_RES;
  290. val &= ~SP5100_PM_WATCHDOG_DISABLE;
  291. outb(val, SP5100_IO_PM_DATA_REG);
  292. /* Check that the watchdog action is set to reset the system. */
  293. val = readl(SP5100_WDT_CONTROL(tcobase));
  294. val &= ~SP5100_PM_WATCHDOG_ACTION_RESET;
  295. writel(val, SP5100_WDT_CONTROL(tcobase));
  296. /* Set a reasonable heartbeat before we stop the timer */
  297. tco_timer_set_heartbeat(heartbeat);
  298. /*
  299. * Stop the TCO before we change anything so we don't race with
  300. * a zeroed timer.
  301. */
  302. tco_timer_stop();
  303. /* Done */
  304. return 1;
  305. unreg_mem_region:
  306. release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
  307. unreg_region:
  308. release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
  309. exit:
  310. return 0;
  311. }
  312. static int __devinit sp5100_tco_init(struct platform_device *dev)
  313. {
  314. int ret;
  315. u32 val;
  316. /* Check whether or not the hardware watchdog is there. If found, then
  317. * set it up.
  318. */
  319. if (!sp5100_tco_setupdevice())
  320. return -ENODEV;
  321. /* Check to see if last reboot was due to watchdog timeout */
  322. pr_info("Watchdog reboot %sdetected\n",
  323. readl(SP5100_WDT_CONTROL(tcobase)) & SP5100_PM_WATCHDOG_FIRED ?
  324. "" : "not ");
  325. /* Clear out the old status */
  326. val = readl(SP5100_WDT_CONTROL(tcobase));
  327. val &= ~SP5100_PM_WATCHDOG_FIRED;
  328. writel(val, SP5100_WDT_CONTROL(tcobase));
  329. /*
  330. * Check that the heartbeat value is within it's range.
  331. * If not, reset to the default.
  332. */
  333. if (tco_timer_set_heartbeat(heartbeat)) {
  334. heartbeat = WATCHDOG_HEARTBEAT;
  335. tco_timer_set_heartbeat(heartbeat);
  336. }
  337. ret = misc_register(&sp5100_tco_miscdev);
  338. if (ret != 0) {
  339. pr_err("cannot register miscdev on minor=%d (err=%d)\n",
  340. WATCHDOG_MINOR, ret);
  341. goto exit;
  342. }
  343. clear_bit(0, &timer_alive);
  344. pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
  345. tcobase, heartbeat, nowayout);
  346. return 0;
  347. exit:
  348. iounmap(tcobase);
  349. release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
  350. release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
  351. return ret;
  352. }
  353. static void __devexit sp5100_tco_cleanup(void)
  354. {
  355. /* Stop the timer before we leave */
  356. if (!nowayout)
  357. tco_timer_stop();
  358. /* Deregister */
  359. misc_deregister(&sp5100_tco_miscdev);
  360. iounmap(tcobase);
  361. release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
  362. release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
  363. }
  364. static int __devexit sp5100_tco_remove(struct platform_device *dev)
  365. {
  366. if (tcobase)
  367. sp5100_tco_cleanup();
  368. return 0;
  369. }
  370. static void sp5100_tco_shutdown(struct platform_device *dev)
  371. {
  372. tco_timer_stop();
  373. }
  374. static struct platform_driver sp5100_tco_driver = {
  375. .probe = sp5100_tco_init,
  376. .remove = __devexit_p(sp5100_tco_remove),
  377. .shutdown = sp5100_tco_shutdown,
  378. .driver = {
  379. .owner = THIS_MODULE,
  380. .name = TCO_MODULE_NAME,
  381. },
  382. };
  383. static int __init sp5100_tco_init_module(void)
  384. {
  385. int err;
  386. pr_info("SP5100 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
  387. err = platform_driver_register(&sp5100_tco_driver);
  388. if (err)
  389. return err;
  390. sp5100_tco_platform_device = platform_device_register_simple(
  391. TCO_MODULE_NAME, -1, NULL, 0);
  392. if (IS_ERR(sp5100_tco_platform_device)) {
  393. err = PTR_ERR(sp5100_tco_platform_device);
  394. goto unreg_platform_driver;
  395. }
  396. return 0;
  397. unreg_platform_driver:
  398. platform_driver_unregister(&sp5100_tco_driver);
  399. return err;
  400. }
  401. static void __exit sp5100_tco_cleanup_module(void)
  402. {
  403. platform_device_unregister(sp5100_tco_platform_device);
  404. platform_driver_unregister(&sp5100_tco_driver);
  405. pr_info("SP5100 TCO Watchdog Module Unloaded\n");
  406. }
  407. module_init(sp5100_tco_init_module);
  408. module_exit(sp5100_tco_cleanup_module);
  409. MODULE_AUTHOR("Priyanka Gupta");
  410. MODULE_DESCRIPTION("TCO timer driver for SP5100 chipset");
  411. MODULE_LICENSE("GPL");
  412. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);