mipi_novatek_cmd_qhd_pt.c 2.9 KB

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  1. /* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. */
  13. #include "msm_fb.h"
  14. #include "mipi_dsi.h"
  15. #include "mipi_novatek.h"
  16. static struct msm_panel_info pinfo;
  17. static struct mipi_dsi_phy_ctrl dsi_cmd_mode_phy_db = {
  18. /* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
  19. {0x03, 0x01, 0x01, 0x00}, /* regulator */
  20. /* timing */
  21. {0xB4, 0x8D, 0x1D, 0x00, 0x20, 0x94, 0x20,
  22. 0x8F, 0x20, 0x03, 0x04},
  23. {0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
  24. {0xee, 0x02, 0x86, 0x00}, /* strength */
  25. /* pll control */
  26. {0x40, 0xf9, 0xb0, 0xda, 0x00, 0x50, 0x48, 0x63,
  27. #if defined(NOVATEK_TWO_LANE)
  28. 0x30, 0x07, 0x03,
  29. #else /* default set to 1 lane */
  30. 0x30, 0x07, 0x07,
  31. #endif
  32. 0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0},
  33. };
  34. static int __init mipi_cmd_novatek_blue_qhd_pt_init(void)
  35. {
  36. int ret;
  37. if (msm_fb_detect_client("mipi_cmd_novatek_qhd"))
  38. return 0;
  39. pinfo.xres = 540;
  40. pinfo.yres = 960;
  41. pinfo.type = MIPI_CMD_PANEL;
  42. pinfo.pdest = DISPLAY_1;
  43. pinfo.wait_cycle = 0;
  44. pinfo.bpp = 24;
  45. pinfo.lcdc.h_back_porch = 50;
  46. pinfo.lcdc.h_front_porch = 50;
  47. pinfo.lcdc.h_pulse_width = 20;
  48. pinfo.lcdc.v_back_porch = 11;
  49. pinfo.lcdc.v_front_porch = 10;
  50. pinfo.lcdc.v_pulse_width = 5;
  51. pinfo.lcdc.border_clr = 0; /* blk */
  52. pinfo.lcdc.underflow_clr = 0xff; /* blue */
  53. pinfo.lcdc.hsync_skew = 0;
  54. pinfo.bl_max = 255;
  55. pinfo.bl_min = 1;
  56. pinfo.fb_num = 2;
  57. pinfo.clk_rate = 454000000;
  58. pinfo.is_3d_panel = FB_TYPE_3D_PANEL;
  59. pinfo.lcd.vsync_enable = TRUE;
  60. pinfo.lcd.hw_vsync_mode = TRUE;
  61. pinfo.lcd.refx100 = 6200; /* adjust refx100 to prevent tearing */
  62. pinfo.lcd.v_back_porch = 11;
  63. pinfo.lcd.v_front_porch = 10;
  64. pinfo.lcd.v_pulse_width = 5;
  65. pinfo.mipi.mode = DSI_CMD_MODE;
  66. pinfo.mipi.dst_format = DSI_CMD_DST_FORMAT_RGB888;
  67. pinfo.mipi.vc = 0;
  68. pinfo.mipi.data_lane0 = TRUE;
  69. pinfo.mipi.esc_byte_ratio = 4;
  70. #if defined(NOVATEK_TWO_LANE)
  71. pinfo.mipi.data_lane1 = TRUE;
  72. #endif
  73. pinfo.mipi.t_clk_post = 0x22;
  74. pinfo.mipi.t_clk_pre = 0x3f;
  75. pinfo.mipi.stream = 0; /* dma_p */
  76. pinfo.mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
  77. pinfo.mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
  78. pinfo.mipi.te_sel = 1; /* TE from vsycn gpio */
  79. pinfo.mipi.interleave_max = 1;
  80. pinfo.mipi.insert_dcs_cmd = TRUE;
  81. pinfo.mipi.wr_mem_continue = 0x3c;
  82. pinfo.mipi.wr_mem_start = 0x2c;
  83. pinfo.mipi.dsi_phy_db = &dsi_cmd_mode_phy_db;
  84. ret = mipi_novatek_device_register(&pinfo, MIPI_DSI_PRIM,
  85. MIPI_DSI_PANEL_QHD_PT);
  86. if (ret)
  87. pr_err("%s: failed to register device!\n", __func__);
  88. return ret;
  89. }
  90. module_init(mipi_cmd_novatek_blue_qhd_pt_init);