rtc-ds1307.c 25 KB

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  1. /*
  2. * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
  3. *
  4. * Copyright (C) 2005 James Chapman (ds1337 core)
  5. * Copyright (C) 2006 David Brownell
  6. * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/slab.h>
  15. #include <linux/i2c.h>
  16. #include <linux/string.h>
  17. #include <linux/rtc.h>
  18. #include <linux/bcd.h>
  19. /*
  20. * We can't determine type by probing, but if we expect pre-Linux code
  21. * to have set the chip up as a clock (turning on the oscillator and
  22. * setting the date and time), Linux can ignore the non-clock features.
  23. * That's a natural job for a factory or repair bench.
  24. */
  25. enum ds_type {
  26. ds_1307,
  27. ds_1337,
  28. ds_1338,
  29. ds_1339,
  30. ds_1340,
  31. ds_1388,
  32. ds_3231,
  33. m41t00,
  34. mcp7941x,
  35. rx_8025,
  36. last_ds_type /* always last */
  37. /* rs5c372 too? different address... */
  38. };
  39. /* RTC registers don't differ much, except for the century flag */
  40. #define DS1307_REG_SECS 0x00 /* 00-59 */
  41. # define DS1307_BIT_CH 0x80
  42. # define DS1340_BIT_nEOSC 0x80
  43. # define MCP7941X_BIT_ST 0x80
  44. #define DS1307_REG_MIN 0x01 /* 00-59 */
  45. #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
  46. # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
  47. # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
  48. # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
  49. # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
  50. #define DS1307_REG_WDAY 0x03 /* 01-07 */
  51. # define MCP7941X_BIT_VBATEN 0x08
  52. #define DS1307_REG_MDAY 0x04 /* 01-31 */
  53. #define DS1307_REG_MONTH 0x05 /* 01-12 */
  54. # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
  55. #define DS1307_REG_YEAR 0x06 /* 00-99 */
  56. /*
  57. * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  58. * start at 7, and they differ a LOT. Only control and status matter for
  59. * basic RTC date and time functionality; be careful using them.
  60. */
  61. #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
  62. # define DS1307_BIT_OUT 0x80
  63. # define DS1338_BIT_OSF 0x20
  64. # define DS1307_BIT_SQWE 0x10
  65. # define DS1307_BIT_RS1 0x02
  66. # define DS1307_BIT_RS0 0x01
  67. #define DS1337_REG_CONTROL 0x0e
  68. # define DS1337_BIT_nEOSC 0x80
  69. # define DS1339_BIT_BBSQI 0x20
  70. # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
  71. # define DS1337_BIT_RS2 0x10
  72. # define DS1337_BIT_RS1 0x08
  73. # define DS1337_BIT_INTCN 0x04
  74. # define DS1337_BIT_A2IE 0x02
  75. # define DS1337_BIT_A1IE 0x01
  76. #define DS1340_REG_CONTROL 0x07
  77. # define DS1340_BIT_OUT 0x80
  78. # define DS1340_BIT_FT 0x40
  79. # define DS1340_BIT_CALIB_SIGN 0x20
  80. # define DS1340_M_CALIBRATION 0x1f
  81. #define DS1340_REG_FLAG 0x09
  82. # define DS1340_BIT_OSF 0x80
  83. #define DS1337_REG_STATUS 0x0f
  84. # define DS1337_BIT_OSF 0x80
  85. # define DS1337_BIT_A2I 0x02
  86. # define DS1337_BIT_A1I 0x01
  87. #define DS1339_REG_ALARM1_SECS 0x07
  88. #define DS1339_REG_TRICKLE 0x10
  89. #define RX8025_REG_CTRL1 0x0e
  90. # define RX8025_BIT_2412 0x20
  91. #define RX8025_REG_CTRL2 0x0f
  92. # define RX8025_BIT_PON 0x10
  93. # define RX8025_BIT_VDET 0x40
  94. # define RX8025_BIT_XST 0x20
  95. struct ds1307 {
  96. u8 offset; /* register's offset */
  97. u8 regs[11];
  98. u16 nvram_offset;
  99. struct bin_attribute *nvram;
  100. enum ds_type type;
  101. unsigned long flags;
  102. #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
  103. #define HAS_ALARM 1 /* bit 1 == irq claimed */
  104. struct i2c_client *client;
  105. struct rtc_device *rtc;
  106. struct work_struct work;
  107. s32 (*read_block_data)(const struct i2c_client *client, u8 command,
  108. u8 length, u8 *values);
  109. s32 (*write_block_data)(const struct i2c_client *client, u8 command,
  110. u8 length, const u8 *values);
  111. };
  112. struct chip_desc {
  113. unsigned alarm:1;
  114. u16 nvram_offset;
  115. u16 nvram_size;
  116. };
  117. static const struct chip_desc chips[last_ds_type] = {
  118. [ds_1307] = {
  119. .nvram_offset = 8,
  120. .nvram_size = 56,
  121. },
  122. [ds_1337] = {
  123. .alarm = 1,
  124. },
  125. [ds_1338] = {
  126. .nvram_offset = 8,
  127. .nvram_size = 56,
  128. },
  129. [ds_1339] = {
  130. .alarm = 1,
  131. },
  132. [ds_3231] = {
  133. .alarm = 1,
  134. },
  135. [mcp7941x] = {
  136. /* this is battery backed SRAM */
  137. .nvram_offset = 0x20,
  138. .nvram_size = 0x40,
  139. },
  140. };
  141. static const struct i2c_device_id ds1307_id[] = {
  142. { "ds1307", ds_1307 },
  143. { "ds1337", ds_1337 },
  144. { "ds1338", ds_1338 },
  145. { "ds1339", ds_1339 },
  146. { "ds1388", ds_1388 },
  147. { "ds1340", ds_1340 },
  148. { "ds3231", ds_3231 },
  149. { "m41t00", m41t00 },
  150. { "mcp7941x", mcp7941x },
  151. { "pt7c4338", ds_1307 },
  152. { "rx8025", rx_8025 },
  153. { }
  154. };
  155. MODULE_DEVICE_TABLE(i2c, ds1307_id);
  156. /*----------------------------------------------------------------------*/
  157. #define BLOCK_DATA_MAX_TRIES 10
  158. static s32 ds1307_read_block_data_once(const struct i2c_client *client,
  159. u8 command, u8 length, u8 *values)
  160. {
  161. s32 i, data;
  162. for (i = 0; i < length; i++) {
  163. data = i2c_smbus_read_byte_data(client, command + i);
  164. if (data < 0)
  165. return data;
  166. values[i] = data;
  167. }
  168. return i;
  169. }
  170. static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
  171. u8 length, u8 *values)
  172. {
  173. u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
  174. s32 ret;
  175. int tries = 0;
  176. dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
  177. ret = ds1307_read_block_data_once(client, command, length, values);
  178. if (ret < 0)
  179. return ret;
  180. do {
  181. if (++tries > BLOCK_DATA_MAX_TRIES) {
  182. dev_err(&client->dev,
  183. "ds1307_read_block_data failed\n");
  184. return -EIO;
  185. }
  186. memcpy(oldvalues, values, length);
  187. ret = ds1307_read_block_data_once(client, command, length,
  188. values);
  189. if (ret < 0)
  190. return ret;
  191. } while (memcmp(oldvalues, values, length));
  192. return length;
  193. }
  194. static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
  195. u8 length, const u8 *values)
  196. {
  197. u8 currvalues[I2C_SMBUS_BLOCK_MAX];
  198. int tries = 0;
  199. dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
  200. do {
  201. s32 i, ret;
  202. if (++tries > BLOCK_DATA_MAX_TRIES) {
  203. dev_err(&client->dev,
  204. "ds1307_write_block_data failed\n");
  205. return -EIO;
  206. }
  207. for (i = 0; i < length; i++) {
  208. ret = i2c_smbus_write_byte_data(client, command + i,
  209. values[i]);
  210. if (ret < 0)
  211. return ret;
  212. }
  213. ret = ds1307_read_block_data_once(client, command, length,
  214. currvalues);
  215. if (ret < 0)
  216. return ret;
  217. } while (memcmp(currvalues, values, length));
  218. return length;
  219. }
  220. /*----------------------------------------------------------------------*/
  221. /*
  222. * The IRQ logic includes a "real" handler running in IRQ context just
  223. * long enough to schedule this workqueue entry. We need a task context
  224. * to talk to the RTC, since I2C I/O calls require that; and disable the
  225. * IRQ until we clear its status on the chip, so that this handler can
  226. * work with any type of triggering (not just falling edge).
  227. *
  228. * The ds1337 and ds1339 both have two alarms, but we only use the first
  229. * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
  230. * signal; ds1339 chips have only one alarm signal.
  231. */
  232. static void ds1307_work(struct work_struct *work)
  233. {
  234. struct ds1307 *ds1307;
  235. struct i2c_client *client;
  236. struct mutex *lock;
  237. int stat, control;
  238. ds1307 = container_of(work, struct ds1307, work);
  239. client = ds1307->client;
  240. lock = &ds1307->rtc->ops_lock;
  241. mutex_lock(lock);
  242. stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
  243. if (stat < 0)
  244. goto out;
  245. if (stat & DS1337_BIT_A1I) {
  246. stat &= ~DS1337_BIT_A1I;
  247. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
  248. control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  249. if (control < 0)
  250. goto out;
  251. control &= ~DS1337_BIT_A1IE;
  252. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
  253. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  254. }
  255. out:
  256. if (test_bit(HAS_ALARM, &ds1307->flags))
  257. enable_irq(client->irq);
  258. mutex_unlock(lock);
  259. }
  260. static irqreturn_t ds1307_irq(int irq, void *dev_id)
  261. {
  262. struct i2c_client *client = dev_id;
  263. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  264. disable_irq_nosync(irq);
  265. schedule_work(&ds1307->work);
  266. return IRQ_HANDLED;
  267. }
  268. /*----------------------------------------------------------------------*/
  269. static int ds1307_get_time(struct device *dev, struct rtc_time *t)
  270. {
  271. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  272. int tmp;
  273. /* read the RTC date and time registers all at once */
  274. tmp = ds1307->read_block_data(ds1307->client,
  275. ds1307->offset, 7, ds1307->regs);
  276. if (tmp != 7) {
  277. dev_err(dev, "%s error %d\n", "read", tmp);
  278. return -EIO;
  279. }
  280. dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
  281. "read",
  282. ds1307->regs[0], ds1307->regs[1],
  283. ds1307->regs[2], ds1307->regs[3],
  284. ds1307->regs[4], ds1307->regs[5],
  285. ds1307->regs[6]);
  286. t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
  287. t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
  288. tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
  289. t->tm_hour = bcd2bin(tmp);
  290. t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
  291. t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
  292. tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
  293. t->tm_mon = bcd2bin(tmp) - 1;
  294. /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
  295. t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
  296. dev_dbg(dev, "%s secs=%d, mins=%d, "
  297. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  298. "read", t->tm_sec, t->tm_min,
  299. t->tm_hour, t->tm_mday,
  300. t->tm_mon, t->tm_year, t->tm_wday);
  301. /* initial clock setting can be undefined */
  302. return rtc_valid_tm(t);
  303. }
  304. static int ds1307_set_time(struct device *dev, struct rtc_time *t)
  305. {
  306. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  307. int result;
  308. int tmp;
  309. u8 *buf = ds1307->regs;
  310. dev_dbg(dev, "%s secs=%d, mins=%d, "
  311. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  312. "write", t->tm_sec, t->tm_min,
  313. t->tm_hour, t->tm_mday,
  314. t->tm_mon, t->tm_year, t->tm_wday);
  315. buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
  316. buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
  317. buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
  318. buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
  319. buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
  320. buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
  321. /* assume 20YY not 19YY */
  322. tmp = t->tm_year - 100;
  323. buf[DS1307_REG_YEAR] = bin2bcd(tmp);
  324. switch (ds1307->type) {
  325. case ds_1337:
  326. case ds_1339:
  327. case ds_3231:
  328. buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
  329. break;
  330. case ds_1340:
  331. buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
  332. | DS1340_BIT_CENTURY;
  333. break;
  334. case mcp7941x:
  335. /*
  336. * these bits were cleared when preparing the date/time
  337. * values and need to be set again before writing the
  338. * buffer out to the device.
  339. */
  340. buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
  341. buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
  342. break;
  343. default:
  344. break;
  345. }
  346. dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
  347. "write", buf[0], buf[1], buf[2], buf[3],
  348. buf[4], buf[5], buf[6]);
  349. result = ds1307->write_block_data(ds1307->client,
  350. ds1307->offset, 7, buf);
  351. if (result < 0) {
  352. dev_err(dev, "%s error %d\n", "write", result);
  353. return result;
  354. }
  355. return 0;
  356. }
  357. static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  358. {
  359. struct i2c_client *client = to_i2c_client(dev);
  360. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  361. int ret;
  362. if (!test_bit(HAS_ALARM, &ds1307->flags))
  363. return -EINVAL;
  364. /* read all ALARM1, ALARM2, and status registers at once */
  365. ret = ds1307->read_block_data(client,
  366. DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
  367. if (ret != 9) {
  368. dev_err(dev, "%s error %d\n", "alarm read", ret);
  369. return -EIO;
  370. }
  371. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  372. "alarm read",
  373. ds1307->regs[0], ds1307->regs[1],
  374. ds1307->regs[2], ds1307->regs[3],
  375. ds1307->regs[4], ds1307->regs[5],
  376. ds1307->regs[6], ds1307->regs[7],
  377. ds1307->regs[8]);
  378. /*
  379. * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
  380. * and that all four fields are checked matches
  381. */
  382. t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
  383. t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
  384. t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
  385. t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
  386. t->time.tm_mon = -1;
  387. t->time.tm_year = -1;
  388. t->time.tm_wday = -1;
  389. t->time.tm_yday = -1;
  390. t->time.tm_isdst = -1;
  391. /* ... and status */
  392. t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
  393. t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
  394. dev_dbg(dev, "%s secs=%d, mins=%d, "
  395. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  396. "alarm read", t->time.tm_sec, t->time.tm_min,
  397. t->time.tm_hour, t->time.tm_mday,
  398. t->enabled, t->pending);
  399. return 0;
  400. }
  401. static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  402. {
  403. struct i2c_client *client = to_i2c_client(dev);
  404. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  405. unsigned char *buf = ds1307->regs;
  406. u8 control, status;
  407. int ret;
  408. if (!test_bit(HAS_ALARM, &ds1307->flags))
  409. return -EINVAL;
  410. dev_dbg(dev, "%s secs=%d, mins=%d, "
  411. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  412. "alarm set", t->time.tm_sec, t->time.tm_min,
  413. t->time.tm_hour, t->time.tm_mday,
  414. t->enabled, t->pending);
  415. /* read current status of both alarms and the chip */
  416. ret = ds1307->read_block_data(client,
  417. DS1339_REG_ALARM1_SECS, 9, buf);
  418. if (ret != 9) {
  419. dev_err(dev, "%s error %d\n", "alarm write", ret);
  420. return -EIO;
  421. }
  422. control = ds1307->regs[7];
  423. status = ds1307->regs[8];
  424. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  425. "alarm set (old status)",
  426. ds1307->regs[0], ds1307->regs[1],
  427. ds1307->regs[2], ds1307->regs[3],
  428. ds1307->regs[4], ds1307->regs[5],
  429. ds1307->regs[6], control, status);
  430. /* set ALARM1, using 24 hour and day-of-month modes */
  431. buf[0] = bin2bcd(t->time.tm_sec);
  432. buf[1] = bin2bcd(t->time.tm_min);
  433. buf[2] = bin2bcd(t->time.tm_hour);
  434. buf[3] = bin2bcd(t->time.tm_mday);
  435. /* set ALARM2 to non-garbage */
  436. buf[4] = 0;
  437. buf[5] = 0;
  438. buf[6] = 0;
  439. /* optionally enable ALARM1 */
  440. buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
  441. if (t->enabled) {
  442. dev_dbg(dev, "alarm IRQ armed\n");
  443. buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
  444. }
  445. buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
  446. ret = ds1307->write_block_data(client,
  447. DS1339_REG_ALARM1_SECS, 9, buf);
  448. if (ret < 0) {
  449. dev_err(dev, "can't set alarm time\n");
  450. return ret;
  451. }
  452. return 0;
  453. }
  454. static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
  455. {
  456. struct i2c_client *client = to_i2c_client(dev);
  457. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  458. int ret;
  459. if (!test_bit(HAS_ALARM, &ds1307->flags))
  460. return -ENOTTY;
  461. ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  462. if (ret < 0)
  463. return ret;
  464. if (enabled)
  465. ret |= DS1337_BIT_A1IE;
  466. else
  467. ret &= ~DS1337_BIT_A1IE;
  468. ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
  469. if (ret < 0)
  470. return ret;
  471. return 0;
  472. }
  473. static const struct rtc_class_ops ds13xx_rtc_ops = {
  474. .read_time = ds1307_get_time,
  475. .set_time = ds1307_set_time,
  476. .read_alarm = ds1337_read_alarm,
  477. .set_alarm = ds1337_set_alarm,
  478. .alarm_irq_enable = ds1307_alarm_irq_enable,
  479. };
  480. /*----------------------------------------------------------------------*/
  481. static ssize_t
  482. ds1307_nvram_read(struct file *filp, struct kobject *kobj,
  483. struct bin_attribute *attr,
  484. char *buf, loff_t off, size_t count)
  485. {
  486. struct i2c_client *client;
  487. struct ds1307 *ds1307;
  488. int result;
  489. client = kobj_to_i2c_client(kobj);
  490. ds1307 = i2c_get_clientdata(client);
  491. if (unlikely(off >= ds1307->nvram->size))
  492. return 0;
  493. if ((off + count) > ds1307->nvram->size)
  494. count = ds1307->nvram->size - off;
  495. if (unlikely(!count))
  496. return count;
  497. result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
  498. count, buf);
  499. if (result < 0)
  500. dev_err(&client->dev, "%s error %d\n", "nvram read", result);
  501. return result;
  502. }
  503. static ssize_t
  504. ds1307_nvram_write(struct file *filp, struct kobject *kobj,
  505. struct bin_attribute *attr,
  506. char *buf, loff_t off, size_t count)
  507. {
  508. struct i2c_client *client;
  509. struct ds1307 *ds1307;
  510. int result;
  511. client = kobj_to_i2c_client(kobj);
  512. ds1307 = i2c_get_clientdata(client);
  513. if (unlikely(off >= ds1307->nvram->size))
  514. return -EFBIG;
  515. if ((off + count) > ds1307->nvram->size)
  516. count = ds1307->nvram->size - off;
  517. if (unlikely(!count))
  518. return count;
  519. result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
  520. count, buf);
  521. if (result < 0) {
  522. dev_err(&client->dev, "%s error %d\n", "nvram write", result);
  523. return result;
  524. }
  525. return count;
  526. }
  527. /*----------------------------------------------------------------------*/
  528. static int __devinit ds1307_probe(struct i2c_client *client,
  529. const struct i2c_device_id *id)
  530. {
  531. struct ds1307 *ds1307;
  532. int err = -ENODEV;
  533. int tmp;
  534. const struct chip_desc *chip = &chips[id->driver_data];
  535. struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
  536. int want_irq = false;
  537. unsigned char *buf;
  538. static const int bbsqi_bitpos[] = {
  539. [ds_1337] = 0,
  540. [ds_1339] = DS1339_BIT_BBSQI,
  541. [ds_3231] = DS3231_BIT_BBSQW,
  542. };
  543. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
  544. && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
  545. return -EIO;
  546. ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL);
  547. if (!ds1307)
  548. return -ENOMEM;
  549. i2c_set_clientdata(client, ds1307);
  550. ds1307->client = client;
  551. ds1307->type = id->driver_data;
  552. ds1307->offset = 0;
  553. buf = ds1307->regs;
  554. if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
  555. ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
  556. ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
  557. } else {
  558. ds1307->read_block_data = ds1307_read_block_data;
  559. ds1307->write_block_data = ds1307_write_block_data;
  560. }
  561. switch (ds1307->type) {
  562. case ds_1337:
  563. case ds_1339:
  564. case ds_3231:
  565. /* get registers that the "rtc" read below won't read... */
  566. tmp = ds1307->read_block_data(ds1307->client,
  567. DS1337_REG_CONTROL, 2, buf);
  568. if (tmp != 2) {
  569. pr_debug("read error %d\n", tmp);
  570. err = -EIO;
  571. goto exit_free;
  572. }
  573. /* oscillator off? turn it on, so clock can tick. */
  574. if (ds1307->regs[0] & DS1337_BIT_nEOSC)
  575. ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
  576. /*
  577. * Using IRQ? Disable the square wave and both alarms.
  578. * For some variants, be sure alarms can trigger when we're
  579. * running on Vbackup (BBSQI/BBSQW)
  580. */
  581. if (ds1307->client->irq > 0 && chip->alarm) {
  582. INIT_WORK(&ds1307->work, ds1307_work);
  583. ds1307->regs[0] |= DS1337_BIT_INTCN
  584. | bbsqi_bitpos[ds1307->type];
  585. ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
  586. want_irq = true;
  587. }
  588. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
  589. ds1307->regs[0]);
  590. /* oscillator fault? clear flag, and warn */
  591. if (ds1307->regs[1] & DS1337_BIT_OSF) {
  592. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
  593. ds1307->regs[1] & ~DS1337_BIT_OSF);
  594. dev_warn(&client->dev, "SET TIME!\n");
  595. }
  596. break;
  597. case rx_8025:
  598. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  599. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  600. if (tmp != 2) {
  601. pr_debug("read error %d\n", tmp);
  602. err = -EIO;
  603. goto exit_free;
  604. }
  605. /* oscillator off? turn it on, so clock can tick. */
  606. if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
  607. ds1307->regs[1] |= RX8025_BIT_XST;
  608. i2c_smbus_write_byte_data(client,
  609. RX8025_REG_CTRL2 << 4 | 0x08,
  610. ds1307->regs[1]);
  611. dev_warn(&client->dev,
  612. "oscillator stop detected - SET TIME!\n");
  613. }
  614. if (ds1307->regs[1] & RX8025_BIT_PON) {
  615. ds1307->regs[1] &= ~RX8025_BIT_PON;
  616. i2c_smbus_write_byte_data(client,
  617. RX8025_REG_CTRL2 << 4 | 0x08,
  618. ds1307->regs[1]);
  619. dev_warn(&client->dev, "power-on detected\n");
  620. }
  621. if (ds1307->regs[1] & RX8025_BIT_VDET) {
  622. ds1307->regs[1] &= ~RX8025_BIT_VDET;
  623. i2c_smbus_write_byte_data(client,
  624. RX8025_REG_CTRL2 << 4 | 0x08,
  625. ds1307->regs[1]);
  626. dev_warn(&client->dev, "voltage drop detected\n");
  627. }
  628. /* make sure we are running in 24hour mode */
  629. if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
  630. u8 hour;
  631. /* switch to 24 hour mode */
  632. i2c_smbus_write_byte_data(client,
  633. RX8025_REG_CTRL1 << 4 | 0x08,
  634. ds1307->regs[0] |
  635. RX8025_BIT_2412);
  636. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  637. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  638. if (tmp != 2) {
  639. pr_debug("read error %d\n", tmp);
  640. err = -EIO;
  641. goto exit_free;
  642. }
  643. /* correct hour */
  644. hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
  645. if (hour == 12)
  646. hour = 0;
  647. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  648. hour += 12;
  649. i2c_smbus_write_byte_data(client,
  650. DS1307_REG_HOUR << 4 | 0x08,
  651. hour);
  652. }
  653. break;
  654. case ds_1388:
  655. ds1307->offset = 1; /* Seconds starts at 1 */
  656. break;
  657. default:
  658. break;
  659. }
  660. read_rtc:
  661. /* read RTC registers */
  662. tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
  663. if (tmp != 8) {
  664. pr_debug("read error %d\n", tmp);
  665. err = -EIO;
  666. goto exit_free;
  667. }
  668. /*
  669. * minimal sanity checking; some chips (like DS1340) don't
  670. * specify the extra bits as must-be-zero, but there are
  671. * still a few values that are clearly out-of-range.
  672. */
  673. tmp = ds1307->regs[DS1307_REG_SECS];
  674. switch (ds1307->type) {
  675. case ds_1307:
  676. case m41t00:
  677. /* clock halted? turn it on, so clock can tick. */
  678. if (tmp & DS1307_BIT_CH) {
  679. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  680. dev_warn(&client->dev, "SET TIME!\n");
  681. goto read_rtc;
  682. }
  683. break;
  684. case ds_1338:
  685. /* clock halted? turn it on, so clock can tick. */
  686. if (tmp & DS1307_BIT_CH)
  687. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  688. /* oscillator fault? clear flag, and warn */
  689. if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
  690. i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
  691. ds1307->regs[DS1307_REG_CONTROL]
  692. & ~DS1338_BIT_OSF);
  693. dev_warn(&client->dev, "SET TIME!\n");
  694. goto read_rtc;
  695. }
  696. break;
  697. case ds_1340:
  698. /* clock halted? turn it on, so clock can tick. */
  699. if (tmp & DS1340_BIT_nEOSC)
  700. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  701. tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
  702. if (tmp < 0) {
  703. pr_debug("read error %d\n", tmp);
  704. err = -EIO;
  705. goto exit_free;
  706. }
  707. /* oscillator fault? clear flag, and warn */
  708. if (tmp & DS1340_BIT_OSF) {
  709. i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
  710. dev_warn(&client->dev, "SET TIME!\n");
  711. }
  712. break;
  713. case mcp7941x:
  714. /* make sure that the backup battery is enabled */
  715. if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
  716. i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
  717. ds1307->regs[DS1307_REG_WDAY]
  718. | MCP7941X_BIT_VBATEN);
  719. }
  720. /* clock halted? turn it on, so clock can tick. */
  721. if (!(tmp & MCP7941X_BIT_ST)) {
  722. i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
  723. MCP7941X_BIT_ST);
  724. dev_warn(&client->dev, "SET TIME!\n");
  725. goto read_rtc;
  726. }
  727. break;
  728. default:
  729. break;
  730. }
  731. tmp = ds1307->regs[DS1307_REG_HOUR];
  732. switch (ds1307->type) {
  733. case ds_1340:
  734. case m41t00:
  735. /*
  736. * NOTE: ignores century bits; fix before deploying
  737. * systems that will run through year 2100.
  738. */
  739. break;
  740. case rx_8025:
  741. break;
  742. default:
  743. if (!(tmp & DS1307_BIT_12HR))
  744. break;
  745. /*
  746. * Be sure we're in 24 hour mode. Multi-master systems
  747. * take note...
  748. */
  749. tmp = bcd2bin(tmp & 0x1f);
  750. if (tmp == 12)
  751. tmp = 0;
  752. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  753. tmp += 12;
  754. i2c_smbus_write_byte_data(client,
  755. ds1307->offset + DS1307_REG_HOUR,
  756. bin2bcd(tmp));
  757. }
  758. ds1307->rtc = rtc_device_register(client->name, &client->dev,
  759. &ds13xx_rtc_ops, THIS_MODULE);
  760. if (IS_ERR(ds1307->rtc)) {
  761. err = PTR_ERR(ds1307->rtc);
  762. dev_err(&client->dev,
  763. "unable to register the class device\n");
  764. goto exit_free;
  765. }
  766. if (want_irq) {
  767. err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
  768. ds1307->rtc->name, client);
  769. if (err) {
  770. dev_err(&client->dev,
  771. "unable to request IRQ!\n");
  772. goto exit_irq;
  773. }
  774. device_set_wakeup_capable(&client->dev, 1);
  775. set_bit(HAS_ALARM, &ds1307->flags);
  776. dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
  777. }
  778. if (chip->nvram_size) {
  779. ds1307->nvram = kzalloc(sizeof(struct bin_attribute),
  780. GFP_KERNEL);
  781. if (!ds1307->nvram) {
  782. err = -ENOMEM;
  783. goto exit_nvram;
  784. }
  785. ds1307->nvram->attr.name = "nvram";
  786. ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
  787. sysfs_bin_attr_init(ds1307->nvram);
  788. ds1307->nvram->read = ds1307_nvram_read,
  789. ds1307->nvram->write = ds1307_nvram_write,
  790. ds1307->nvram->size = chip->nvram_size;
  791. ds1307->nvram_offset = chip->nvram_offset;
  792. err = sysfs_create_bin_file(&client->dev.kobj, ds1307->nvram);
  793. if (err) {
  794. kfree(ds1307->nvram);
  795. goto exit_nvram;
  796. }
  797. set_bit(HAS_NVRAM, &ds1307->flags);
  798. dev_info(&client->dev, "%zu bytes nvram\n", ds1307->nvram->size);
  799. }
  800. return 0;
  801. exit_nvram:
  802. exit_irq:
  803. rtc_device_unregister(ds1307->rtc);
  804. exit_free:
  805. kfree(ds1307);
  806. return err;
  807. }
  808. static int __devexit ds1307_remove(struct i2c_client *client)
  809. {
  810. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  811. if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
  812. free_irq(client->irq, client);
  813. cancel_work_sync(&ds1307->work);
  814. }
  815. if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags)) {
  816. sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
  817. kfree(ds1307->nvram);
  818. }
  819. rtc_device_unregister(ds1307->rtc);
  820. kfree(ds1307);
  821. return 0;
  822. }
  823. static struct i2c_driver ds1307_driver = {
  824. .driver = {
  825. .name = "rtc-ds1307",
  826. .owner = THIS_MODULE,
  827. },
  828. .probe = ds1307_probe,
  829. .remove = __devexit_p(ds1307_remove),
  830. .id_table = ds1307_id,
  831. };
  832. module_i2c_driver(ds1307_driver);
  833. MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
  834. MODULE_LICENSE("GPL");