mipsnet.c 8.2 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. */
  6. #include <linux/init.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/io.h>
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/netdevice.h>
  12. #include <linux/etherdevice.h>
  13. #include <linux/platform_device.h>
  14. #include <asm/mips-boards/simint.h>
  15. #define MIPSNET_VERSION "2007-11-17"
  16. /*
  17. * Net status/control block as seen by sw in the core.
  18. */
  19. struct mipsnet_regs {
  20. /*
  21. * Device info for probing, reads as MIPSNET%d where %d is some
  22. * form of version.
  23. */
  24. u64 devId; /*0x00 */
  25. /*
  26. * read only busy flag.
  27. * Set and cleared by the Net Device to indicate that an rx or a tx
  28. * is in progress.
  29. */
  30. u32 busy; /*0x08 */
  31. /*
  32. * Set by the Net Device.
  33. * The device will set it once data has been received.
  34. * The value is the number of bytes that should be read from
  35. * rxDataBuffer. The value will decrease till 0 until all the data
  36. * from rxDataBuffer has been read.
  37. */
  38. u32 rxDataCount; /*0x0c */
  39. #define MIPSNET_MAX_RXTX_DATACOUNT (1 << 16)
  40. /*
  41. * Settable from the MIPS core, cleared by the Net Device.
  42. * The core should set the number of bytes it wants to send,
  43. * then it should write those bytes of data to txDataBuffer.
  44. * The device will clear txDataCount has been processed (not
  45. * necessarily sent).
  46. */
  47. u32 txDataCount; /*0x10 */
  48. /*
  49. * Interrupt control
  50. *
  51. * Used to clear the interrupted generated by this dev.
  52. * Write a 1 to clear the interrupt. (except bit31).
  53. *
  54. * Bit0 is set if it was a tx-done interrupt.
  55. * Bit1 is set when new rx-data is available.
  56. * Until this bit is cleared there will be no other RXs.
  57. *
  58. * Bit31 is used for testing, it clears after a read.
  59. * Writing 1 to this bit will cause an interrupt to be generated.
  60. * To clear the test interrupt, write 0 to this register.
  61. */
  62. u32 interruptControl; /*0x14 */
  63. #define MIPSNET_INTCTL_TXDONE (1u << 0)
  64. #define MIPSNET_INTCTL_RXDONE (1u << 1)
  65. #define MIPSNET_INTCTL_TESTBIT (1u << 31)
  66. /*
  67. * Readonly core-specific interrupt info for the device to signal
  68. * the core. The meaning of the contents of this field might change.
  69. */
  70. /* XXX: the whole memIntf interrupt scheme is messy: the device
  71. * should have no control what so ever of what VPE/register set is
  72. * being used.
  73. * The MemIntf should only expose interrupt lines, and something in
  74. * the config should be responsible for the line<->core/vpe bindings.
  75. */
  76. u32 interruptInfo; /*0x18 */
  77. /*
  78. * This is where the received data is read out.
  79. * There is more data to read until rxDataReady is 0.
  80. * Only 1 byte at this regs offset is used.
  81. */
  82. u32 rxDataBuffer; /*0x1c */
  83. /*
  84. * This is where the data to transmit is written.
  85. * Data should be written for the amount specified in the
  86. * txDataCount register.
  87. * Only 1 byte at this regs offset is used.
  88. */
  89. u32 txDataBuffer; /*0x20 */
  90. };
  91. #define regaddr(dev, field) \
  92. (dev->base_addr + offsetof(struct mipsnet_regs, field))
  93. static char mipsnet_string[] = "mipsnet";
  94. /*
  95. * Copy data from the MIPSNET rx data port
  96. */
  97. static int ioiocpy_frommipsnet(struct net_device *dev, unsigned char *kdata,
  98. int len)
  99. {
  100. for (; len > 0; len--, kdata++)
  101. *kdata = inb(regaddr(dev, rxDataBuffer));
  102. return inl(regaddr(dev, rxDataCount));
  103. }
  104. static inline void mipsnet_put_todevice(struct net_device *dev,
  105. struct sk_buff *skb)
  106. {
  107. int count_to_go = skb->len;
  108. char *buf_ptr = skb->data;
  109. outl(skb->len, regaddr(dev, txDataCount));
  110. for (; count_to_go; buf_ptr++, count_to_go--)
  111. outb(*buf_ptr, regaddr(dev, txDataBuffer));
  112. dev->stats.tx_packets++;
  113. dev->stats.tx_bytes += skb->len;
  114. dev_kfree_skb(skb);
  115. }
  116. static int mipsnet_xmit(struct sk_buff *skb, struct net_device *dev)
  117. {
  118. /*
  119. * Only one packet at a time. Once TXDONE interrupt is serviced, the
  120. * queue will be restarted.
  121. */
  122. netif_stop_queue(dev);
  123. mipsnet_put_todevice(dev, skb);
  124. return NETDEV_TX_OK;
  125. }
  126. static inline ssize_t mipsnet_get_fromdev(struct net_device *dev, size_t len)
  127. {
  128. struct sk_buff *skb;
  129. if (!len)
  130. return len;
  131. skb = netdev_alloc_skb(dev, len + NET_IP_ALIGN);
  132. if (!skb) {
  133. dev->stats.rx_dropped++;
  134. return -ENOMEM;
  135. }
  136. skb_reserve(skb, NET_IP_ALIGN);
  137. if (ioiocpy_frommipsnet(dev, skb_put(skb, len), len))
  138. return -EFAULT;
  139. skb->protocol = eth_type_trans(skb, dev);
  140. skb->ip_summed = CHECKSUM_UNNECESSARY;
  141. netif_rx(skb);
  142. dev->stats.rx_packets++;
  143. dev->stats.rx_bytes += len;
  144. return len;
  145. }
  146. static irqreturn_t mipsnet_interrupt(int irq, void *dev_id)
  147. {
  148. struct net_device *dev = dev_id;
  149. u32 int_flags;
  150. irqreturn_t ret = IRQ_NONE;
  151. if (irq != dev->irq)
  152. goto out_badirq;
  153. /* TESTBIT is cleared on read. */
  154. int_flags = inl(regaddr(dev, interruptControl));
  155. if (int_flags & MIPSNET_INTCTL_TESTBIT) {
  156. /* TESTBIT takes effect after a write with 0. */
  157. outl(0, regaddr(dev, interruptControl));
  158. ret = IRQ_HANDLED;
  159. } else if (int_flags & MIPSNET_INTCTL_TXDONE) {
  160. /* Only one packet at a time, we are done. */
  161. dev->stats.tx_packets++;
  162. netif_wake_queue(dev);
  163. outl(MIPSNET_INTCTL_TXDONE,
  164. regaddr(dev, interruptControl));
  165. ret = IRQ_HANDLED;
  166. } else if (int_flags & MIPSNET_INTCTL_RXDONE) {
  167. mipsnet_get_fromdev(dev, inl(regaddr(dev, rxDataCount)));
  168. outl(MIPSNET_INTCTL_RXDONE, regaddr(dev, interruptControl));
  169. ret = IRQ_HANDLED;
  170. }
  171. return ret;
  172. out_badirq:
  173. printk(KERN_INFO "%s: %s(): irq %d for unknown device\n",
  174. dev->name, __func__, irq);
  175. return ret;
  176. }
  177. static int mipsnet_open(struct net_device *dev)
  178. {
  179. int err;
  180. err = request_irq(dev->irq, mipsnet_interrupt,
  181. IRQF_SHARED, dev->name, (void *) dev);
  182. if (err) {
  183. release_region(dev->base_addr, sizeof(struct mipsnet_regs));
  184. return err;
  185. }
  186. netif_start_queue(dev);
  187. /* test interrupt handler */
  188. outl(MIPSNET_INTCTL_TESTBIT, regaddr(dev, interruptControl));
  189. return 0;
  190. }
  191. static int mipsnet_close(struct net_device *dev)
  192. {
  193. netif_stop_queue(dev);
  194. free_irq(dev->irq, dev);
  195. return 0;
  196. }
  197. static void mipsnet_set_mclist(struct net_device *dev)
  198. {
  199. }
  200. static const struct net_device_ops mipsnet_netdev_ops = {
  201. .ndo_open = mipsnet_open,
  202. .ndo_stop = mipsnet_close,
  203. .ndo_start_xmit = mipsnet_xmit,
  204. .ndo_set_rx_mode = mipsnet_set_mclist,
  205. .ndo_change_mtu = eth_change_mtu,
  206. .ndo_validate_addr = eth_validate_addr,
  207. .ndo_set_mac_address = eth_mac_addr,
  208. };
  209. static int __devinit mipsnet_probe(struct platform_device *dev)
  210. {
  211. struct net_device *netdev;
  212. int err;
  213. netdev = alloc_etherdev(0);
  214. if (!netdev) {
  215. err = -ENOMEM;
  216. goto out;
  217. }
  218. platform_set_drvdata(dev, netdev);
  219. netdev->netdev_ops = &mipsnet_netdev_ops;
  220. /*
  221. * TODO: probe for these or load them from PARAM
  222. */
  223. netdev->base_addr = 0x4200;
  224. netdev->irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB0 +
  225. inl(regaddr(netdev, interruptInfo));
  226. /* Get the io region now, get irq on open() */
  227. if (!request_region(netdev->base_addr, sizeof(struct mipsnet_regs),
  228. "mipsnet")) {
  229. err = -EBUSY;
  230. goto out_free_netdev;
  231. }
  232. /*
  233. * Lacking any better mechanism to allocate a MAC address we use a
  234. * random one ...
  235. */
  236. eth_hw_addr_random(netdev);
  237. err = register_netdev(netdev);
  238. if (err) {
  239. printk(KERN_ERR "MIPSNet: failed to register netdev.\n");
  240. goto out_free_region;
  241. }
  242. return 0;
  243. out_free_region:
  244. release_region(netdev->base_addr, sizeof(struct mipsnet_regs));
  245. out_free_netdev:
  246. free_netdev(netdev);
  247. out:
  248. return err;
  249. }
  250. static int __devexit mipsnet_device_remove(struct platform_device *device)
  251. {
  252. struct net_device *dev = platform_get_drvdata(device);
  253. unregister_netdev(dev);
  254. release_region(dev->base_addr, sizeof(struct mipsnet_regs));
  255. free_netdev(dev);
  256. platform_set_drvdata(device, NULL);
  257. return 0;
  258. }
  259. static struct platform_driver mipsnet_driver = {
  260. .driver = {
  261. .name = mipsnet_string,
  262. .owner = THIS_MODULE,
  263. },
  264. .probe = mipsnet_probe,
  265. .remove = __devexit_p(mipsnet_device_remove),
  266. };
  267. static int __init mipsnet_init_module(void)
  268. {
  269. int err;
  270. printk(KERN_INFO "MIPSNet Ethernet driver. Version: %s. "
  271. "(c)2005 MIPS Technologies, Inc.\n", MIPSNET_VERSION);
  272. err = platform_driver_register(&mipsnet_driver);
  273. if (err)
  274. printk(KERN_ERR "Driver registration failed\n");
  275. return err;
  276. }
  277. static void __exit mipsnet_exit_module(void)
  278. {
  279. platform_driver_unregister(&mipsnet_driver);
  280. }
  281. module_init(mipsnet_init_module);
  282. module_exit(mipsnet_exit_module);