ep93xx_eth.c 21 KB

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  1. /*
  2. * EP93xx ethernet network device driver
  3. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  4. * Dedicated to Marija Kulikova.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
  12. #include <linux/dma-mapping.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/netdevice.h>
  16. #include <linux/mii.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/ethtool.h>
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/moduleparam.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/delay.h>
  24. #include <linux/io.h>
  25. #include <linux/slab.h>
  26. #include <mach/hardware.h>
  27. #define DRV_MODULE_NAME "ep93xx-eth"
  28. #define DRV_MODULE_VERSION "0.1"
  29. #define RX_QUEUE_ENTRIES 64
  30. #define TX_QUEUE_ENTRIES 8
  31. #define MAX_PKT_SIZE 2044
  32. #define PKT_BUF_SIZE 2048
  33. #define REG_RXCTL 0x0000
  34. #define REG_RXCTL_DEFAULT 0x00073800
  35. #define REG_TXCTL 0x0004
  36. #define REG_TXCTL_ENABLE 0x00000001
  37. #define REG_MIICMD 0x0010
  38. #define REG_MIICMD_READ 0x00008000
  39. #define REG_MIICMD_WRITE 0x00004000
  40. #define REG_MIIDATA 0x0014
  41. #define REG_MIISTS 0x0018
  42. #define REG_MIISTS_BUSY 0x00000001
  43. #define REG_SELFCTL 0x0020
  44. #define REG_SELFCTL_RESET 0x00000001
  45. #define REG_INTEN 0x0024
  46. #define REG_INTEN_TX 0x00000008
  47. #define REG_INTEN_RX 0x00000007
  48. #define REG_INTSTSP 0x0028
  49. #define REG_INTSTS_TX 0x00000008
  50. #define REG_INTSTS_RX 0x00000004
  51. #define REG_INTSTSC 0x002c
  52. #define REG_AFP 0x004c
  53. #define REG_INDAD0 0x0050
  54. #define REG_INDAD1 0x0051
  55. #define REG_INDAD2 0x0052
  56. #define REG_INDAD3 0x0053
  57. #define REG_INDAD4 0x0054
  58. #define REG_INDAD5 0x0055
  59. #define REG_GIINTMSK 0x0064
  60. #define REG_GIINTMSK_ENABLE 0x00008000
  61. #define REG_BMCTL 0x0080
  62. #define REG_BMCTL_ENABLE_TX 0x00000100
  63. #define REG_BMCTL_ENABLE_RX 0x00000001
  64. #define REG_BMSTS 0x0084
  65. #define REG_BMSTS_RX_ACTIVE 0x00000008
  66. #define REG_RXDQBADD 0x0090
  67. #define REG_RXDQBLEN 0x0094
  68. #define REG_RXDCURADD 0x0098
  69. #define REG_RXDENQ 0x009c
  70. #define REG_RXSTSQBADD 0x00a0
  71. #define REG_RXSTSQBLEN 0x00a4
  72. #define REG_RXSTSQCURADD 0x00a8
  73. #define REG_RXSTSENQ 0x00ac
  74. #define REG_TXDQBADD 0x00b0
  75. #define REG_TXDQBLEN 0x00b4
  76. #define REG_TXDQCURADD 0x00b8
  77. #define REG_TXDENQ 0x00bc
  78. #define REG_TXSTSQBADD 0x00c0
  79. #define REG_TXSTSQBLEN 0x00c4
  80. #define REG_TXSTSQCURADD 0x00c8
  81. #define REG_MAXFRMLEN 0x00e8
  82. struct ep93xx_rdesc
  83. {
  84. u32 buf_addr;
  85. u32 rdesc1;
  86. };
  87. #define RDESC1_NSOF 0x80000000
  88. #define RDESC1_BUFFER_INDEX 0x7fff0000
  89. #define RDESC1_BUFFER_LENGTH 0x0000ffff
  90. struct ep93xx_rstat
  91. {
  92. u32 rstat0;
  93. u32 rstat1;
  94. };
  95. #define RSTAT0_RFP 0x80000000
  96. #define RSTAT0_RWE 0x40000000
  97. #define RSTAT0_EOF 0x20000000
  98. #define RSTAT0_EOB 0x10000000
  99. #define RSTAT0_AM 0x00c00000
  100. #define RSTAT0_RX_ERR 0x00200000
  101. #define RSTAT0_OE 0x00100000
  102. #define RSTAT0_FE 0x00080000
  103. #define RSTAT0_RUNT 0x00040000
  104. #define RSTAT0_EDATA 0x00020000
  105. #define RSTAT0_CRCE 0x00010000
  106. #define RSTAT0_CRCI 0x00008000
  107. #define RSTAT0_HTI 0x00003f00
  108. #define RSTAT1_RFP 0x80000000
  109. #define RSTAT1_BUFFER_INDEX 0x7fff0000
  110. #define RSTAT1_FRAME_LENGTH 0x0000ffff
  111. struct ep93xx_tdesc
  112. {
  113. u32 buf_addr;
  114. u32 tdesc1;
  115. };
  116. #define TDESC1_EOF 0x80000000
  117. #define TDESC1_BUFFER_INDEX 0x7fff0000
  118. #define TDESC1_BUFFER_ABORT 0x00008000
  119. #define TDESC1_BUFFER_LENGTH 0x00000fff
  120. struct ep93xx_tstat
  121. {
  122. u32 tstat0;
  123. };
  124. #define TSTAT0_TXFP 0x80000000
  125. #define TSTAT0_TXWE 0x40000000
  126. #define TSTAT0_FA 0x20000000
  127. #define TSTAT0_LCRS 0x10000000
  128. #define TSTAT0_OW 0x04000000
  129. #define TSTAT0_TXU 0x02000000
  130. #define TSTAT0_ECOLL 0x01000000
  131. #define TSTAT0_NCOLL 0x001f0000
  132. #define TSTAT0_BUFFER_INDEX 0x00007fff
  133. struct ep93xx_descs
  134. {
  135. struct ep93xx_rdesc rdesc[RX_QUEUE_ENTRIES];
  136. struct ep93xx_tdesc tdesc[TX_QUEUE_ENTRIES];
  137. struct ep93xx_rstat rstat[RX_QUEUE_ENTRIES];
  138. struct ep93xx_tstat tstat[TX_QUEUE_ENTRIES];
  139. };
  140. struct ep93xx_priv
  141. {
  142. struct resource *res;
  143. void __iomem *base_addr;
  144. int irq;
  145. struct ep93xx_descs *descs;
  146. dma_addr_t descs_dma_addr;
  147. void *rx_buf[RX_QUEUE_ENTRIES];
  148. void *tx_buf[TX_QUEUE_ENTRIES];
  149. spinlock_t rx_lock;
  150. unsigned int rx_pointer;
  151. unsigned int tx_clean_pointer;
  152. unsigned int tx_pointer;
  153. spinlock_t tx_pending_lock;
  154. unsigned int tx_pending;
  155. struct net_device *dev;
  156. struct napi_struct napi;
  157. struct mii_if_info mii;
  158. u8 mdc_divisor;
  159. };
  160. #define rdb(ep, off) __raw_readb((ep)->base_addr + (off))
  161. #define rdw(ep, off) __raw_readw((ep)->base_addr + (off))
  162. #define rdl(ep, off) __raw_readl((ep)->base_addr + (off))
  163. #define wrb(ep, off, val) __raw_writeb((val), (ep)->base_addr + (off))
  164. #define wrw(ep, off, val) __raw_writew((val), (ep)->base_addr + (off))
  165. #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off))
  166. static int ep93xx_mdio_read(struct net_device *dev, int phy_id, int reg)
  167. {
  168. struct ep93xx_priv *ep = netdev_priv(dev);
  169. int data;
  170. int i;
  171. wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg);
  172. for (i = 0; i < 10; i++) {
  173. if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
  174. break;
  175. msleep(1);
  176. }
  177. if (i == 10) {
  178. pr_info("mdio read timed out\n");
  179. data = 0xffff;
  180. } else {
  181. data = rdl(ep, REG_MIIDATA);
  182. }
  183. return data;
  184. }
  185. static void ep93xx_mdio_write(struct net_device *dev, int phy_id, int reg, int data)
  186. {
  187. struct ep93xx_priv *ep = netdev_priv(dev);
  188. int i;
  189. wrl(ep, REG_MIIDATA, data);
  190. wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg);
  191. for (i = 0; i < 10; i++) {
  192. if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
  193. break;
  194. msleep(1);
  195. }
  196. if (i == 10)
  197. pr_info("mdio write timed out\n");
  198. }
  199. static int ep93xx_rx(struct net_device *dev, int processed, int budget)
  200. {
  201. struct ep93xx_priv *ep = netdev_priv(dev);
  202. while (processed < budget) {
  203. int entry;
  204. struct ep93xx_rstat *rstat;
  205. u32 rstat0;
  206. u32 rstat1;
  207. int length;
  208. struct sk_buff *skb;
  209. entry = ep->rx_pointer;
  210. rstat = ep->descs->rstat + entry;
  211. rstat0 = rstat->rstat0;
  212. rstat1 = rstat->rstat1;
  213. if (!(rstat0 & RSTAT0_RFP) || !(rstat1 & RSTAT1_RFP))
  214. break;
  215. rstat->rstat0 = 0;
  216. rstat->rstat1 = 0;
  217. if (!(rstat0 & RSTAT0_EOF))
  218. pr_crit("not end-of-frame %.8x %.8x\n", rstat0, rstat1);
  219. if (!(rstat0 & RSTAT0_EOB))
  220. pr_crit("not end-of-buffer %.8x %.8x\n", rstat0, rstat1);
  221. if ((rstat1 & RSTAT1_BUFFER_INDEX) >> 16 != entry)
  222. pr_crit("entry mismatch %.8x %.8x\n", rstat0, rstat1);
  223. if (!(rstat0 & RSTAT0_RWE)) {
  224. dev->stats.rx_errors++;
  225. if (rstat0 & RSTAT0_OE)
  226. dev->stats.rx_fifo_errors++;
  227. if (rstat0 & RSTAT0_FE)
  228. dev->stats.rx_frame_errors++;
  229. if (rstat0 & (RSTAT0_RUNT | RSTAT0_EDATA))
  230. dev->stats.rx_length_errors++;
  231. if (rstat0 & RSTAT0_CRCE)
  232. dev->stats.rx_crc_errors++;
  233. goto err;
  234. }
  235. length = rstat1 & RSTAT1_FRAME_LENGTH;
  236. if (length > MAX_PKT_SIZE) {
  237. pr_notice("invalid length %.8x %.8x\n", rstat0, rstat1);
  238. goto err;
  239. }
  240. /* Strip FCS. */
  241. if (rstat0 & RSTAT0_CRCI)
  242. length -= 4;
  243. skb = netdev_alloc_skb(dev, length + 2);
  244. if (likely(skb != NULL)) {
  245. struct ep93xx_rdesc *rxd = &ep->descs->rdesc[entry];
  246. skb_reserve(skb, 2);
  247. dma_sync_single_for_cpu(dev->dev.parent, rxd->buf_addr,
  248. length, DMA_FROM_DEVICE);
  249. skb_copy_to_linear_data(skb, ep->rx_buf[entry], length);
  250. dma_sync_single_for_device(dev->dev.parent,
  251. rxd->buf_addr, length,
  252. DMA_FROM_DEVICE);
  253. skb_put(skb, length);
  254. skb->protocol = eth_type_trans(skb, dev);
  255. netif_receive_skb(skb);
  256. dev->stats.rx_packets++;
  257. dev->stats.rx_bytes += length;
  258. } else {
  259. dev->stats.rx_dropped++;
  260. }
  261. err:
  262. ep->rx_pointer = (entry + 1) & (RX_QUEUE_ENTRIES - 1);
  263. processed++;
  264. }
  265. return processed;
  266. }
  267. static int ep93xx_have_more_rx(struct ep93xx_priv *ep)
  268. {
  269. struct ep93xx_rstat *rstat = ep->descs->rstat + ep->rx_pointer;
  270. return !!((rstat->rstat0 & RSTAT0_RFP) && (rstat->rstat1 & RSTAT1_RFP));
  271. }
  272. static int ep93xx_poll(struct napi_struct *napi, int budget)
  273. {
  274. struct ep93xx_priv *ep = container_of(napi, struct ep93xx_priv, napi);
  275. struct net_device *dev = ep->dev;
  276. int rx = 0;
  277. poll_some_more:
  278. rx = ep93xx_rx(dev, rx, budget);
  279. if (rx < budget) {
  280. int more = 0;
  281. spin_lock_irq(&ep->rx_lock);
  282. __napi_complete(napi);
  283. wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
  284. if (ep93xx_have_more_rx(ep)) {
  285. wrl(ep, REG_INTEN, REG_INTEN_TX);
  286. wrl(ep, REG_INTSTSP, REG_INTSTS_RX);
  287. more = 1;
  288. }
  289. spin_unlock_irq(&ep->rx_lock);
  290. if (more && napi_reschedule(napi))
  291. goto poll_some_more;
  292. }
  293. if (rx) {
  294. wrw(ep, REG_RXDENQ, rx);
  295. wrw(ep, REG_RXSTSENQ, rx);
  296. }
  297. return rx;
  298. }
  299. static int ep93xx_xmit(struct sk_buff *skb, struct net_device *dev)
  300. {
  301. struct ep93xx_priv *ep = netdev_priv(dev);
  302. struct ep93xx_tdesc *txd;
  303. int entry;
  304. if (unlikely(skb->len > MAX_PKT_SIZE)) {
  305. dev->stats.tx_dropped++;
  306. dev_kfree_skb(skb);
  307. return NETDEV_TX_OK;
  308. }
  309. entry = ep->tx_pointer;
  310. ep->tx_pointer = (ep->tx_pointer + 1) & (TX_QUEUE_ENTRIES - 1);
  311. txd = &ep->descs->tdesc[entry];
  312. txd->tdesc1 = TDESC1_EOF | (entry << 16) | (skb->len & 0xfff);
  313. dma_sync_single_for_cpu(dev->dev.parent, txd->buf_addr, skb->len,
  314. DMA_TO_DEVICE);
  315. skb_copy_and_csum_dev(skb, ep->tx_buf[entry]);
  316. dma_sync_single_for_device(dev->dev.parent, txd->buf_addr, skb->len,
  317. DMA_TO_DEVICE);
  318. dev_kfree_skb(skb);
  319. spin_lock_irq(&ep->tx_pending_lock);
  320. ep->tx_pending++;
  321. if (ep->tx_pending == TX_QUEUE_ENTRIES)
  322. netif_stop_queue(dev);
  323. spin_unlock_irq(&ep->tx_pending_lock);
  324. wrl(ep, REG_TXDENQ, 1);
  325. return NETDEV_TX_OK;
  326. }
  327. static void ep93xx_tx_complete(struct net_device *dev)
  328. {
  329. struct ep93xx_priv *ep = netdev_priv(dev);
  330. int wake;
  331. wake = 0;
  332. spin_lock(&ep->tx_pending_lock);
  333. while (1) {
  334. int entry;
  335. struct ep93xx_tstat *tstat;
  336. u32 tstat0;
  337. entry = ep->tx_clean_pointer;
  338. tstat = ep->descs->tstat + entry;
  339. tstat0 = tstat->tstat0;
  340. if (!(tstat0 & TSTAT0_TXFP))
  341. break;
  342. tstat->tstat0 = 0;
  343. if (tstat0 & TSTAT0_FA)
  344. pr_crit("frame aborted %.8x\n", tstat0);
  345. if ((tstat0 & TSTAT0_BUFFER_INDEX) != entry)
  346. pr_crit("entry mismatch %.8x\n", tstat0);
  347. if (tstat0 & TSTAT0_TXWE) {
  348. int length = ep->descs->tdesc[entry].tdesc1 & 0xfff;
  349. dev->stats.tx_packets++;
  350. dev->stats.tx_bytes += length;
  351. } else {
  352. dev->stats.tx_errors++;
  353. }
  354. if (tstat0 & TSTAT0_OW)
  355. dev->stats.tx_window_errors++;
  356. if (tstat0 & TSTAT0_TXU)
  357. dev->stats.tx_fifo_errors++;
  358. dev->stats.collisions += (tstat0 >> 16) & 0x1f;
  359. ep->tx_clean_pointer = (entry + 1) & (TX_QUEUE_ENTRIES - 1);
  360. if (ep->tx_pending == TX_QUEUE_ENTRIES)
  361. wake = 1;
  362. ep->tx_pending--;
  363. }
  364. spin_unlock(&ep->tx_pending_lock);
  365. if (wake)
  366. netif_wake_queue(dev);
  367. }
  368. static irqreturn_t ep93xx_irq(int irq, void *dev_id)
  369. {
  370. struct net_device *dev = dev_id;
  371. struct ep93xx_priv *ep = netdev_priv(dev);
  372. u32 status;
  373. status = rdl(ep, REG_INTSTSC);
  374. if (status == 0)
  375. return IRQ_NONE;
  376. if (status & REG_INTSTS_RX) {
  377. spin_lock(&ep->rx_lock);
  378. if (likely(napi_schedule_prep(&ep->napi))) {
  379. wrl(ep, REG_INTEN, REG_INTEN_TX);
  380. __napi_schedule(&ep->napi);
  381. }
  382. spin_unlock(&ep->rx_lock);
  383. }
  384. if (status & REG_INTSTS_TX)
  385. ep93xx_tx_complete(dev);
  386. return IRQ_HANDLED;
  387. }
  388. static void ep93xx_free_buffers(struct ep93xx_priv *ep)
  389. {
  390. struct device *dev = ep->dev->dev.parent;
  391. int i;
  392. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  393. dma_addr_t d;
  394. d = ep->descs->rdesc[i].buf_addr;
  395. if (d)
  396. dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_FROM_DEVICE);
  397. if (ep->rx_buf[i] != NULL)
  398. kfree(ep->rx_buf[i]);
  399. }
  400. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  401. dma_addr_t d;
  402. d = ep->descs->tdesc[i].buf_addr;
  403. if (d)
  404. dma_unmap_single(dev, d, PKT_BUF_SIZE, DMA_TO_DEVICE);
  405. if (ep->tx_buf[i] != NULL)
  406. kfree(ep->tx_buf[i]);
  407. }
  408. dma_free_coherent(dev, sizeof(struct ep93xx_descs), ep->descs,
  409. ep->descs_dma_addr);
  410. }
  411. static int ep93xx_alloc_buffers(struct ep93xx_priv *ep)
  412. {
  413. struct device *dev = ep->dev->dev.parent;
  414. int i;
  415. ep->descs = dma_alloc_coherent(dev, sizeof(struct ep93xx_descs),
  416. &ep->descs_dma_addr, GFP_KERNEL);
  417. if (ep->descs == NULL)
  418. return 1;
  419. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  420. void *buf;
  421. dma_addr_t d;
  422. buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
  423. if (buf == NULL)
  424. goto err;
  425. d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_FROM_DEVICE);
  426. if (dma_mapping_error(dev, d)) {
  427. kfree(buf);
  428. goto err;
  429. }
  430. ep->rx_buf[i] = buf;
  431. ep->descs->rdesc[i].buf_addr = d;
  432. ep->descs->rdesc[i].rdesc1 = (i << 16) | PKT_BUF_SIZE;
  433. }
  434. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  435. void *buf;
  436. dma_addr_t d;
  437. buf = kmalloc(PKT_BUF_SIZE, GFP_KERNEL);
  438. if (buf == NULL)
  439. goto err;
  440. d = dma_map_single(dev, buf, PKT_BUF_SIZE, DMA_TO_DEVICE);
  441. if (dma_mapping_error(dev, d)) {
  442. kfree(buf);
  443. goto err;
  444. }
  445. ep->tx_buf[i] = buf;
  446. ep->descs->tdesc[i].buf_addr = d;
  447. }
  448. return 0;
  449. err:
  450. ep93xx_free_buffers(ep);
  451. return 1;
  452. }
  453. static int ep93xx_start_hw(struct net_device *dev)
  454. {
  455. struct ep93xx_priv *ep = netdev_priv(dev);
  456. unsigned long addr;
  457. int i;
  458. wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
  459. for (i = 0; i < 10; i++) {
  460. if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
  461. break;
  462. msleep(1);
  463. }
  464. if (i == 10) {
  465. pr_crit("hw failed to reset\n");
  466. return 1;
  467. }
  468. wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9));
  469. /* Does the PHY support preamble suppress? */
  470. if ((ep93xx_mdio_read(dev, ep->mii.phy_id, MII_BMSR) & 0x0040) != 0)
  471. wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8));
  472. /* Receive descriptor ring. */
  473. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rdesc);
  474. wrl(ep, REG_RXDQBADD, addr);
  475. wrl(ep, REG_RXDCURADD, addr);
  476. wrw(ep, REG_RXDQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rdesc));
  477. /* Receive status ring. */
  478. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, rstat);
  479. wrl(ep, REG_RXSTSQBADD, addr);
  480. wrl(ep, REG_RXSTSQCURADD, addr);
  481. wrw(ep, REG_RXSTSQBLEN, RX_QUEUE_ENTRIES * sizeof(struct ep93xx_rstat));
  482. /* Transmit descriptor ring. */
  483. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tdesc);
  484. wrl(ep, REG_TXDQBADD, addr);
  485. wrl(ep, REG_TXDQCURADD, addr);
  486. wrw(ep, REG_TXDQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tdesc));
  487. /* Transmit status ring. */
  488. addr = ep->descs_dma_addr + offsetof(struct ep93xx_descs, tstat);
  489. wrl(ep, REG_TXSTSQBADD, addr);
  490. wrl(ep, REG_TXSTSQCURADD, addr);
  491. wrw(ep, REG_TXSTSQBLEN, TX_QUEUE_ENTRIES * sizeof(struct ep93xx_tstat));
  492. wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX);
  493. wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX);
  494. wrl(ep, REG_GIINTMSK, 0);
  495. for (i = 0; i < 10; i++) {
  496. if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
  497. break;
  498. msleep(1);
  499. }
  500. if (i == 10) {
  501. pr_crit("hw failed to start\n");
  502. return 1;
  503. }
  504. wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES);
  505. wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES);
  506. wrb(ep, REG_INDAD0, dev->dev_addr[0]);
  507. wrb(ep, REG_INDAD1, dev->dev_addr[1]);
  508. wrb(ep, REG_INDAD2, dev->dev_addr[2]);
  509. wrb(ep, REG_INDAD3, dev->dev_addr[3]);
  510. wrb(ep, REG_INDAD4, dev->dev_addr[4]);
  511. wrb(ep, REG_INDAD5, dev->dev_addr[5]);
  512. wrl(ep, REG_AFP, 0);
  513. wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE);
  514. wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT);
  515. wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE);
  516. return 0;
  517. }
  518. static void ep93xx_stop_hw(struct net_device *dev)
  519. {
  520. struct ep93xx_priv *ep = netdev_priv(dev);
  521. int i;
  522. wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET);
  523. for (i = 0; i < 10; i++) {
  524. if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
  525. break;
  526. msleep(1);
  527. }
  528. if (i == 10)
  529. pr_crit("hw failed to reset\n");
  530. }
  531. static int ep93xx_open(struct net_device *dev)
  532. {
  533. struct ep93xx_priv *ep = netdev_priv(dev);
  534. int err;
  535. if (ep93xx_alloc_buffers(ep))
  536. return -ENOMEM;
  537. napi_enable(&ep->napi);
  538. if (ep93xx_start_hw(dev)) {
  539. napi_disable(&ep->napi);
  540. ep93xx_free_buffers(ep);
  541. return -EIO;
  542. }
  543. spin_lock_init(&ep->rx_lock);
  544. ep->rx_pointer = 0;
  545. ep->tx_clean_pointer = 0;
  546. ep->tx_pointer = 0;
  547. spin_lock_init(&ep->tx_pending_lock);
  548. ep->tx_pending = 0;
  549. err = request_irq(ep->irq, ep93xx_irq, IRQF_SHARED, dev->name, dev);
  550. if (err) {
  551. napi_disable(&ep->napi);
  552. ep93xx_stop_hw(dev);
  553. ep93xx_free_buffers(ep);
  554. return err;
  555. }
  556. wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE);
  557. netif_start_queue(dev);
  558. return 0;
  559. }
  560. static int ep93xx_close(struct net_device *dev)
  561. {
  562. struct ep93xx_priv *ep = netdev_priv(dev);
  563. napi_disable(&ep->napi);
  564. netif_stop_queue(dev);
  565. wrl(ep, REG_GIINTMSK, 0);
  566. free_irq(ep->irq, dev);
  567. ep93xx_stop_hw(dev);
  568. ep93xx_free_buffers(ep);
  569. return 0;
  570. }
  571. static int ep93xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  572. {
  573. struct ep93xx_priv *ep = netdev_priv(dev);
  574. struct mii_ioctl_data *data = if_mii(ifr);
  575. return generic_mii_ioctl(&ep->mii, data, cmd, NULL);
  576. }
  577. static void ep93xx_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  578. {
  579. strcpy(info->driver, DRV_MODULE_NAME);
  580. strcpy(info->version, DRV_MODULE_VERSION);
  581. }
  582. static int ep93xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  583. {
  584. struct ep93xx_priv *ep = netdev_priv(dev);
  585. return mii_ethtool_gset(&ep->mii, cmd);
  586. }
  587. static int ep93xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  588. {
  589. struct ep93xx_priv *ep = netdev_priv(dev);
  590. return mii_ethtool_sset(&ep->mii, cmd);
  591. }
  592. static int ep93xx_nway_reset(struct net_device *dev)
  593. {
  594. struct ep93xx_priv *ep = netdev_priv(dev);
  595. return mii_nway_restart(&ep->mii);
  596. }
  597. static u32 ep93xx_get_link(struct net_device *dev)
  598. {
  599. struct ep93xx_priv *ep = netdev_priv(dev);
  600. return mii_link_ok(&ep->mii);
  601. }
  602. static const struct ethtool_ops ep93xx_ethtool_ops = {
  603. .get_drvinfo = ep93xx_get_drvinfo,
  604. .get_settings = ep93xx_get_settings,
  605. .set_settings = ep93xx_set_settings,
  606. .nway_reset = ep93xx_nway_reset,
  607. .get_link = ep93xx_get_link,
  608. };
  609. static const struct net_device_ops ep93xx_netdev_ops = {
  610. .ndo_open = ep93xx_open,
  611. .ndo_stop = ep93xx_close,
  612. .ndo_start_xmit = ep93xx_xmit,
  613. .ndo_do_ioctl = ep93xx_ioctl,
  614. .ndo_validate_addr = eth_validate_addr,
  615. .ndo_change_mtu = eth_change_mtu,
  616. .ndo_set_mac_address = eth_mac_addr,
  617. };
  618. static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data)
  619. {
  620. struct net_device *dev;
  621. dev = alloc_etherdev(sizeof(struct ep93xx_priv));
  622. if (dev == NULL)
  623. return NULL;
  624. memcpy(dev->dev_addr, data->dev_addr, ETH_ALEN);
  625. dev->ethtool_ops = &ep93xx_ethtool_ops;
  626. dev->netdev_ops = &ep93xx_netdev_ops;
  627. dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
  628. return dev;
  629. }
  630. static int ep93xx_eth_remove(struct platform_device *pdev)
  631. {
  632. struct net_device *dev;
  633. struct ep93xx_priv *ep;
  634. dev = platform_get_drvdata(pdev);
  635. if (dev == NULL)
  636. return 0;
  637. platform_set_drvdata(pdev, NULL);
  638. ep = netdev_priv(dev);
  639. /* @@@ Force down. */
  640. unregister_netdev(dev);
  641. ep93xx_free_buffers(ep);
  642. if (ep->base_addr != NULL)
  643. iounmap(ep->base_addr);
  644. if (ep->res != NULL) {
  645. release_resource(ep->res);
  646. kfree(ep->res);
  647. }
  648. free_netdev(dev);
  649. return 0;
  650. }
  651. static int ep93xx_eth_probe(struct platform_device *pdev)
  652. {
  653. struct ep93xx_eth_data *data;
  654. struct net_device *dev;
  655. struct ep93xx_priv *ep;
  656. struct resource *mem;
  657. int irq;
  658. int err;
  659. if (pdev == NULL)
  660. return -ENODEV;
  661. data = pdev->dev.platform_data;
  662. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  663. irq = platform_get_irq(pdev, 0);
  664. if (!mem || irq < 0)
  665. return -ENXIO;
  666. dev = ep93xx_dev_alloc(data);
  667. if (dev == NULL) {
  668. err = -ENOMEM;
  669. goto err_out;
  670. }
  671. ep = netdev_priv(dev);
  672. ep->dev = dev;
  673. SET_NETDEV_DEV(dev, &pdev->dev);
  674. netif_napi_add(dev, &ep->napi, ep93xx_poll, 64);
  675. platform_set_drvdata(pdev, dev);
  676. ep->res = request_mem_region(mem->start, resource_size(mem),
  677. dev_name(&pdev->dev));
  678. if (ep->res == NULL) {
  679. dev_err(&pdev->dev, "Could not reserve memory region\n");
  680. err = -ENOMEM;
  681. goto err_out;
  682. }
  683. ep->base_addr = ioremap(mem->start, resource_size(mem));
  684. if (ep->base_addr == NULL) {
  685. dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
  686. err = -EIO;
  687. goto err_out;
  688. }
  689. ep->irq = irq;
  690. ep->mii.phy_id = data->phy_id;
  691. ep->mii.phy_id_mask = 0x1f;
  692. ep->mii.reg_num_mask = 0x1f;
  693. ep->mii.dev = dev;
  694. ep->mii.mdio_read = ep93xx_mdio_read;
  695. ep->mii.mdio_write = ep93xx_mdio_write;
  696. ep->mdc_divisor = 40; /* Max HCLK 100 MHz, min MDIO clk 2.5 MHz. */
  697. if (is_zero_ether_addr(dev->dev_addr))
  698. eth_hw_addr_random(dev);
  699. err = register_netdev(dev);
  700. if (err) {
  701. dev_err(&pdev->dev, "Failed to register netdev\n");
  702. goto err_out;
  703. }
  704. printk(KERN_INFO "%s: ep93xx on-chip ethernet, IRQ %d, %pM\n",
  705. dev->name, ep->irq, dev->dev_addr);
  706. return 0;
  707. err_out:
  708. ep93xx_eth_remove(pdev);
  709. return err;
  710. }
  711. static struct platform_driver ep93xx_eth_driver = {
  712. .probe = ep93xx_eth_probe,
  713. .remove = ep93xx_eth_remove,
  714. .driver = {
  715. .name = "ep93xx-eth",
  716. .owner = THIS_MODULE,
  717. },
  718. };
  719. static int __init ep93xx_eth_init_module(void)
  720. {
  721. printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n");
  722. return platform_driver_register(&ep93xx_eth_driver);
  723. }
  724. static void __exit ep93xx_eth_cleanup_module(void)
  725. {
  726. platform_driver_unregister(&ep93xx_eth_driver);
  727. }
  728. module_init(ep93xx_eth_init_module);
  729. module_exit(ep93xx_eth_cleanup_module);
  730. MODULE_LICENSE("GPL");
  731. MODULE_ALIAS("platform:ep93xx-eth");