janz-ican3.c 43 KB

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  1. /*
  2. * Janz MODULbus VMOD-ICAN3 CAN Interface Driver
  3. *
  4. * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/delay.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/netdevice.h>
  18. #include <linux/can.h>
  19. #include <linux/can/dev.h>
  20. #include <linux/can/error.h>
  21. #include <linux/mfd/janz.h>
  22. #include <asm/io.h>
  23. /* the DPM has 64k of memory, organized into 256x 256 byte pages */
  24. #define DPM_NUM_PAGES 256
  25. #define DPM_PAGE_SIZE 256
  26. #define DPM_PAGE_ADDR(p) ((p) * DPM_PAGE_SIZE)
  27. /* JANZ ICAN3 "old-style" host interface queue page numbers */
  28. #define QUEUE_OLD_CONTROL 0
  29. #define QUEUE_OLD_RB0 1
  30. #define QUEUE_OLD_RB1 2
  31. #define QUEUE_OLD_WB0 3
  32. #define QUEUE_OLD_WB1 4
  33. /* Janz ICAN3 "old-style" host interface control registers */
  34. #define MSYNC_PEER 0x00 /* ICAN only */
  35. #define MSYNC_LOCL 0x01 /* host only */
  36. #define TARGET_RUNNING 0x02
  37. #define MSYNC_RB0 0x01
  38. #define MSYNC_RB1 0x02
  39. #define MSYNC_RBLW 0x04
  40. #define MSYNC_RB_MASK (MSYNC_RB0 | MSYNC_RB1)
  41. #define MSYNC_WB0 0x10
  42. #define MSYNC_WB1 0x20
  43. #define MSYNC_WBLW 0x40
  44. #define MSYNC_WB_MASK (MSYNC_WB0 | MSYNC_WB1)
  45. /* Janz ICAN3 "new-style" host interface queue page numbers */
  46. #define QUEUE_TOHOST 5
  47. #define QUEUE_FROMHOST_MID 6
  48. #define QUEUE_FROMHOST_HIGH 7
  49. #define QUEUE_FROMHOST_LOW 8
  50. /* The first free page in the DPM is #9 */
  51. #define DPM_FREE_START 9
  52. /* Janz ICAN3 "new-style" and "fast" host interface descriptor flags */
  53. #define DESC_VALID 0x80
  54. #define DESC_WRAP 0x40
  55. #define DESC_INTERRUPT 0x20
  56. #define DESC_IVALID 0x10
  57. #define DESC_LEN(len) (len)
  58. /* Janz ICAN3 Firmware Messages */
  59. #define MSG_CONNECTI 0x02
  60. #define MSG_DISCONNECT 0x03
  61. #define MSG_IDVERS 0x04
  62. #define MSG_MSGLOST 0x05
  63. #define MSG_NEWHOSTIF 0x08
  64. #define MSG_INQUIRY 0x0a
  65. #define MSG_SETAFILMASK 0x10
  66. #define MSG_INITFDPMQUEUE 0x11
  67. #define MSG_HWCONF 0x12
  68. #define MSG_FMSGLOST 0x15
  69. #define MSG_CEVTIND 0x37
  70. #define MSG_CBTRREQ 0x41
  71. #define MSG_COFFREQ 0x42
  72. #define MSG_CONREQ 0x43
  73. #define MSG_CCONFREQ 0x47
  74. /*
  75. * Janz ICAN3 CAN Inquiry Message Types
  76. *
  77. * NOTE: there appears to be a firmware bug here. You must send
  78. * NOTE: INQUIRY_STATUS and expect to receive an INQUIRY_EXTENDED
  79. * NOTE: response. The controller never responds to a message with
  80. * NOTE: the INQUIRY_EXTENDED subspec :(
  81. */
  82. #define INQUIRY_STATUS 0x00
  83. #define INQUIRY_TERMINATION 0x01
  84. #define INQUIRY_EXTENDED 0x04
  85. /* Janz ICAN3 CAN Set Acceptance Filter Mask Message Types */
  86. #define SETAFILMASK_REJECT 0x00
  87. #define SETAFILMASK_FASTIF 0x02
  88. /* Janz ICAN3 CAN Hardware Configuration Message Types */
  89. #define HWCONF_TERMINATE_ON 0x01
  90. #define HWCONF_TERMINATE_OFF 0x00
  91. /* Janz ICAN3 CAN Event Indication Message Types */
  92. #define CEVTIND_EI 0x01
  93. #define CEVTIND_DOI 0x02
  94. #define CEVTIND_LOST 0x04
  95. #define CEVTIND_FULL 0x08
  96. #define CEVTIND_BEI 0x10
  97. #define CEVTIND_CHIP_SJA1000 0x02
  98. #define ICAN3_BUSERR_QUOTA_MAX 255
  99. /* Janz ICAN3 CAN Frame Conversion */
  100. #define ICAN3_ECHO 0x10
  101. #define ICAN3_EFF_RTR 0x40
  102. #define ICAN3_SFF_RTR 0x10
  103. #define ICAN3_EFF 0x80
  104. #define ICAN3_CAN_TYPE_MASK 0x0f
  105. #define ICAN3_CAN_TYPE_SFF 0x00
  106. #define ICAN3_CAN_TYPE_EFF 0x01
  107. #define ICAN3_CAN_DLC_MASK 0x0f
  108. /*
  109. * SJA1000 Status and Error Register Definitions
  110. *
  111. * Copied from drivers/net/can/sja1000/sja1000.h
  112. */
  113. /* status register content */
  114. #define SR_BS 0x80
  115. #define SR_ES 0x40
  116. #define SR_TS 0x20
  117. #define SR_RS 0x10
  118. #define SR_TCS 0x08
  119. #define SR_TBS 0x04
  120. #define SR_DOS 0x02
  121. #define SR_RBS 0x01
  122. #define SR_CRIT (SR_BS|SR_ES)
  123. /* ECC register */
  124. #define ECC_SEG 0x1F
  125. #define ECC_DIR 0x20
  126. #define ECC_ERR 6
  127. #define ECC_BIT 0x00
  128. #define ECC_FORM 0x40
  129. #define ECC_STUFF 0x80
  130. #define ECC_MASK 0xc0
  131. /* Number of buffers for use in the "new-style" host interface */
  132. #define ICAN3_NEW_BUFFERS 16
  133. /* Number of buffers for use in the "fast" host interface */
  134. #define ICAN3_TX_BUFFERS 512
  135. #define ICAN3_RX_BUFFERS 1024
  136. /* SJA1000 Clock Input */
  137. #define ICAN3_CAN_CLOCK 8000000
  138. /* Driver Name */
  139. #define DRV_NAME "janz-ican3"
  140. /* DPM Control Registers -- starts at offset 0x100 in the MODULbus registers */
  141. struct ican3_dpm_control {
  142. /* window address register */
  143. u8 window_address;
  144. u8 unused1;
  145. /*
  146. * Read access: clear interrupt from microcontroller
  147. * Write access: send interrupt to microcontroller
  148. */
  149. u8 interrupt;
  150. u8 unused2;
  151. /* write-only: reset all hardware on the module */
  152. u8 hwreset;
  153. u8 unused3;
  154. /* write-only: generate an interrupt to the TPU */
  155. u8 tpuinterrupt;
  156. };
  157. struct ican3_dev {
  158. /* must be the first member */
  159. struct can_priv can;
  160. /* CAN network device */
  161. struct net_device *ndev;
  162. struct napi_struct napi;
  163. /* Device for printing */
  164. struct device *dev;
  165. /* module number */
  166. unsigned int num;
  167. /* base address of registers and IRQ */
  168. struct janz_cmodio_onboard_regs __iomem *ctrl;
  169. struct ican3_dpm_control __iomem *dpmctrl;
  170. void __iomem *dpm;
  171. int irq;
  172. /* CAN bus termination status */
  173. struct completion termination_comp;
  174. bool termination_enabled;
  175. /* CAN bus error status registers */
  176. struct completion buserror_comp;
  177. struct can_berr_counter bec;
  178. /* old and new style host interface */
  179. unsigned int iftype;
  180. /*
  181. * Any function which changes the current DPM page must hold this
  182. * lock while it is performing data accesses. This ensures that the
  183. * function will not be preempted and end up reading data from a
  184. * different DPM page than it expects.
  185. */
  186. spinlock_t lock;
  187. /* new host interface */
  188. unsigned int rx_int;
  189. unsigned int rx_num;
  190. unsigned int tx_num;
  191. /* fast host interface */
  192. unsigned int fastrx_start;
  193. unsigned int fastrx_int;
  194. unsigned int fastrx_num;
  195. unsigned int fasttx_start;
  196. unsigned int fasttx_num;
  197. /* first free DPM page */
  198. unsigned int free_page;
  199. };
  200. struct ican3_msg {
  201. u8 control;
  202. u8 spec;
  203. __le16 len;
  204. u8 data[252];
  205. };
  206. struct ican3_new_desc {
  207. u8 control;
  208. u8 pointer;
  209. };
  210. struct ican3_fast_desc {
  211. u8 control;
  212. u8 command;
  213. u8 data[14];
  214. };
  215. /* write to the window basic address register */
  216. static inline void ican3_set_page(struct ican3_dev *mod, unsigned int page)
  217. {
  218. BUG_ON(page >= DPM_NUM_PAGES);
  219. iowrite8(page, &mod->dpmctrl->window_address);
  220. }
  221. /*
  222. * ICAN3 "old-style" host interface
  223. */
  224. /*
  225. * Receive a message from the ICAN3 "old-style" firmware interface
  226. *
  227. * LOCKING: must hold mod->lock
  228. *
  229. * returns 0 on success, -ENOMEM when no message exists
  230. */
  231. static int ican3_old_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  232. {
  233. unsigned int mbox, mbox_page;
  234. u8 locl, peer, xord;
  235. /* get the MSYNC registers */
  236. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  237. peer = ioread8(mod->dpm + MSYNC_PEER);
  238. locl = ioread8(mod->dpm + MSYNC_LOCL);
  239. xord = locl ^ peer;
  240. if ((xord & MSYNC_RB_MASK) == 0x00) {
  241. dev_dbg(mod->dev, "no mbox for reading\n");
  242. return -ENOMEM;
  243. }
  244. /* find the first free mbox to read */
  245. if ((xord & MSYNC_RB_MASK) == MSYNC_RB_MASK)
  246. mbox = (xord & MSYNC_RBLW) ? MSYNC_RB0 : MSYNC_RB1;
  247. else
  248. mbox = (xord & MSYNC_RB0) ? MSYNC_RB0 : MSYNC_RB1;
  249. /* copy the message */
  250. mbox_page = (mbox == MSYNC_RB0) ? QUEUE_OLD_RB0 : QUEUE_OLD_RB1;
  251. ican3_set_page(mod, mbox_page);
  252. memcpy_fromio(msg, mod->dpm, sizeof(*msg));
  253. /*
  254. * notify the firmware that the read buffer is available
  255. * for it to fill again
  256. */
  257. locl ^= mbox;
  258. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  259. iowrite8(locl, mod->dpm + MSYNC_LOCL);
  260. return 0;
  261. }
  262. /*
  263. * Send a message through the "old-style" firmware interface
  264. *
  265. * LOCKING: must hold mod->lock
  266. *
  267. * returns 0 on success, -ENOMEM when no free space exists
  268. */
  269. static int ican3_old_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  270. {
  271. unsigned int mbox, mbox_page;
  272. u8 locl, peer, xord;
  273. /* get the MSYNC registers */
  274. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  275. peer = ioread8(mod->dpm + MSYNC_PEER);
  276. locl = ioread8(mod->dpm + MSYNC_LOCL);
  277. xord = locl ^ peer;
  278. if ((xord & MSYNC_WB_MASK) == MSYNC_WB_MASK) {
  279. dev_err(mod->dev, "no mbox for writing\n");
  280. return -ENOMEM;
  281. }
  282. /* calculate a free mbox to use */
  283. mbox = (xord & MSYNC_WB0) ? MSYNC_WB1 : MSYNC_WB0;
  284. /* copy the message to the DPM */
  285. mbox_page = (mbox == MSYNC_WB0) ? QUEUE_OLD_WB0 : QUEUE_OLD_WB1;
  286. ican3_set_page(mod, mbox_page);
  287. memcpy_toio(mod->dpm, msg, sizeof(*msg));
  288. locl ^= mbox;
  289. if (mbox == MSYNC_WB1)
  290. locl |= MSYNC_WBLW;
  291. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  292. iowrite8(locl, mod->dpm + MSYNC_LOCL);
  293. return 0;
  294. }
  295. /*
  296. * ICAN3 "new-style" Host Interface Setup
  297. */
  298. static void __devinit ican3_init_new_host_interface(struct ican3_dev *mod)
  299. {
  300. struct ican3_new_desc desc;
  301. unsigned long flags;
  302. void __iomem *dst;
  303. int i;
  304. spin_lock_irqsave(&mod->lock, flags);
  305. /* setup the internal datastructures for RX */
  306. mod->rx_num = 0;
  307. mod->rx_int = 0;
  308. /* tohost queue descriptors are in page 5 */
  309. ican3_set_page(mod, QUEUE_TOHOST);
  310. dst = mod->dpm;
  311. /* initialize the tohost (rx) queue descriptors: pages 9-24 */
  312. for (i = 0; i < ICAN3_NEW_BUFFERS; i++) {
  313. desc.control = DESC_INTERRUPT | DESC_LEN(1); /* I L=1 */
  314. desc.pointer = mod->free_page;
  315. /* set wrap flag on last buffer */
  316. if (i == ICAN3_NEW_BUFFERS - 1)
  317. desc.control |= DESC_WRAP;
  318. memcpy_toio(dst, &desc, sizeof(desc));
  319. dst += sizeof(desc);
  320. mod->free_page++;
  321. }
  322. /* fromhost (tx) mid queue descriptors are in page 6 */
  323. ican3_set_page(mod, QUEUE_FROMHOST_MID);
  324. dst = mod->dpm;
  325. /* setup the internal datastructures for TX */
  326. mod->tx_num = 0;
  327. /* initialize the fromhost mid queue descriptors: pages 25-40 */
  328. for (i = 0; i < ICAN3_NEW_BUFFERS; i++) {
  329. desc.control = DESC_VALID | DESC_LEN(1); /* V L=1 */
  330. desc.pointer = mod->free_page;
  331. /* set wrap flag on last buffer */
  332. if (i == ICAN3_NEW_BUFFERS - 1)
  333. desc.control |= DESC_WRAP;
  334. memcpy_toio(dst, &desc, sizeof(desc));
  335. dst += sizeof(desc);
  336. mod->free_page++;
  337. }
  338. /* fromhost hi queue descriptors are in page 7 */
  339. ican3_set_page(mod, QUEUE_FROMHOST_HIGH);
  340. dst = mod->dpm;
  341. /* initialize only a single buffer in the fromhost hi queue (unused) */
  342. desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */
  343. desc.pointer = mod->free_page;
  344. memcpy_toio(dst, &desc, sizeof(desc));
  345. mod->free_page++;
  346. /* fromhost low queue descriptors are in page 8 */
  347. ican3_set_page(mod, QUEUE_FROMHOST_LOW);
  348. dst = mod->dpm;
  349. /* initialize only a single buffer in the fromhost low queue (unused) */
  350. desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */
  351. desc.pointer = mod->free_page;
  352. memcpy_toio(dst, &desc, sizeof(desc));
  353. mod->free_page++;
  354. spin_unlock_irqrestore(&mod->lock, flags);
  355. }
  356. /*
  357. * ICAN3 Fast Host Interface Setup
  358. */
  359. static void __devinit ican3_init_fast_host_interface(struct ican3_dev *mod)
  360. {
  361. struct ican3_fast_desc desc;
  362. unsigned long flags;
  363. unsigned int addr;
  364. void __iomem *dst;
  365. int i;
  366. spin_lock_irqsave(&mod->lock, flags);
  367. /* save the start recv page */
  368. mod->fastrx_start = mod->free_page;
  369. mod->fastrx_num = 0;
  370. mod->fastrx_int = 0;
  371. /* build a single fast tohost queue descriptor */
  372. memset(&desc, 0, sizeof(desc));
  373. desc.control = 0x00;
  374. desc.command = 1;
  375. /* build the tohost queue descriptor ring in memory */
  376. addr = 0;
  377. for (i = 0; i < ICAN3_RX_BUFFERS; i++) {
  378. /* set the wrap bit on the last buffer */
  379. if (i == ICAN3_RX_BUFFERS - 1)
  380. desc.control |= DESC_WRAP;
  381. /* switch to the correct page */
  382. ican3_set_page(mod, mod->free_page);
  383. /* copy the descriptor to the DPM */
  384. dst = mod->dpm + addr;
  385. memcpy_toio(dst, &desc, sizeof(desc));
  386. addr += sizeof(desc);
  387. /* move to the next page if necessary */
  388. if (addr >= DPM_PAGE_SIZE) {
  389. addr = 0;
  390. mod->free_page++;
  391. }
  392. }
  393. /* make sure we page-align the next queue */
  394. if (addr != 0)
  395. mod->free_page++;
  396. /* save the start xmit page */
  397. mod->fasttx_start = mod->free_page;
  398. mod->fasttx_num = 0;
  399. /* build a single fast fromhost queue descriptor */
  400. memset(&desc, 0, sizeof(desc));
  401. desc.control = DESC_VALID;
  402. desc.command = 1;
  403. /* build the fromhost queue descriptor ring in memory */
  404. addr = 0;
  405. for (i = 0; i < ICAN3_TX_BUFFERS; i++) {
  406. /* set the wrap bit on the last buffer */
  407. if (i == ICAN3_TX_BUFFERS - 1)
  408. desc.control |= DESC_WRAP;
  409. /* switch to the correct page */
  410. ican3_set_page(mod, mod->free_page);
  411. /* copy the descriptor to the DPM */
  412. dst = mod->dpm + addr;
  413. memcpy_toio(dst, &desc, sizeof(desc));
  414. addr += sizeof(desc);
  415. /* move to the next page if necessary */
  416. if (addr >= DPM_PAGE_SIZE) {
  417. addr = 0;
  418. mod->free_page++;
  419. }
  420. }
  421. spin_unlock_irqrestore(&mod->lock, flags);
  422. }
  423. /*
  424. * ICAN3 "new-style" Host Interface Message Helpers
  425. */
  426. /*
  427. * LOCKING: must hold mod->lock
  428. */
  429. static int ican3_new_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  430. {
  431. struct ican3_new_desc desc;
  432. void __iomem *desc_addr = mod->dpm + (mod->tx_num * sizeof(desc));
  433. /* switch to the fromhost mid queue, and read the buffer descriptor */
  434. ican3_set_page(mod, QUEUE_FROMHOST_MID);
  435. memcpy_fromio(&desc, desc_addr, sizeof(desc));
  436. if (!(desc.control & DESC_VALID)) {
  437. dev_dbg(mod->dev, "%s: no free buffers\n", __func__);
  438. return -ENOMEM;
  439. }
  440. /* switch to the data page, copy the data */
  441. ican3_set_page(mod, desc.pointer);
  442. memcpy_toio(mod->dpm, msg, sizeof(*msg));
  443. /* switch back to the descriptor, set the valid bit, write it back */
  444. ican3_set_page(mod, QUEUE_FROMHOST_MID);
  445. desc.control ^= DESC_VALID;
  446. memcpy_toio(desc_addr, &desc, sizeof(desc));
  447. /* update the tx number */
  448. mod->tx_num = (desc.control & DESC_WRAP) ? 0 : (mod->tx_num + 1);
  449. return 0;
  450. }
  451. /*
  452. * LOCKING: must hold mod->lock
  453. */
  454. static int ican3_new_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  455. {
  456. struct ican3_new_desc desc;
  457. void __iomem *desc_addr = mod->dpm + (mod->rx_num * sizeof(desc));
  458. /* switch to the tohost queue, and read the buffer descriptor */
  459. ican3_set_page(mod, QUEUE_TOHOST);
  460. memcpy_fromio(&desc, desc_addr, sizeof(desc));
  461. if (!(desc.control & DESC_VALID)) {
  462. dev_dbg(mod->dev, "%s: no buffers to recv\n", __func__);
  463. return -ENOMEM;
  464. }
  465. /* switch to the data page, copy the data */
  466. ican3_set_page(mod, desc.pointer);
  467. memcpy_fromio(msg, mod->dpm, sizeof(*msg));
  468. /* switch back to the descriptor, toggle the valid bit, write it back */
  469. ican3_set_page(mod, QUEUE_TOHOST);
  470. desc.control ^= DESC_VALID;
  471. memcpy_toio(desc_addr, &desc, sizeof(desc));
  472. /* update the rx number */
  473. mod->rx_num = (desc.control & DESC_WRAP) ? 0 : (mod->rx_num + 1);
  474. return 0;
  475. }
  476. /*
  477. * Message Send / Recv Helpers
  478. */
  479. static int ican3_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  480. {
  481. unsigned long flags;
  482. int ret;
  483. spin_lock_irqsave(&mod->lock, flags);
  484. if (mod->iftype == 0)
  485. ret = ican3_old_send_msg(mod, msg);
  486. else
  487. ret = ican3_new_send_msg(mod, msg);
  488. spin_unlock_irqrestore(&mod->lock, flags);
  489. return ret;
  490. }
  491. static int ican3_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  492. {
  493. unsigned long flags;
  494. int ret;
  495. spin_lock_irqsave(&mod->lock, flags);
  496. if (mod->iftype == 0)
  497. ret = ican3_old_recv_msg(mod, msg);
  498. else
  499. ret = ican3_new_recv_msg(mod, msg);
  500. spin_unlock_irqrestore(&mod->lock, flags);
  501. return ret;
  502. }
  503. /*
  504. * Quick Pre-constructed Messages
  505. */
  506. static int __devinit ican3_msg_connect(struct ican3_dev *mod)
  507. {
  508. struct ican3_msg msg;
  509. memset(&msg, 0, sizeof(msg));
  510. msg.spec = MSG_CONNECTI;
  511. msg.len = cpu_to_le16(0);
  512. return ican3_send_msg(mod, &msg);
  513. }
  514. static int __devexit ican3_msg_disconnect(struct ican3_dev *mod)
  515. {
  516. struct ican3_msg msg;
  517. memset(&msg, 0, sizeof(msg));
  518. msg.spec = MSG_DISCONNECT;
  519. msg.len = cpu_to_le16(0);
  520. return ican3_send_msg(mod, &msg);
  521. }
  522. static int __devinit ican3_msg_newhostif(struct ican3_dev *mod)
  523. {
  524. struct ican3_msg msg;
  525. int ret;
  526. memset(&msg, 0, sizeof(msg));
  527. msg.spec = MSG_NEWHOSTIF;
  528. msg.len = cpu_to_le16(0);
  529. /* If we're not using the old interface, switching seems bogus */
  530. WARN_ON(mod->iftype != 0);
  531. ret = ican3_send_msg(mod, &msg);
  532. if (ret)
  533. return ret;
  534. /* mark the module as using the new host interface */
  535. mod->iftype = 1;
  536. return 0;
  537. }
  538. static int __devinit ican3_msg_fasthostif(struct ican3_dev *mod)
  539. {
  540. struct ican3_msg msg;
  541. unsigned int addr;
  542. memset(&msg, 0, sizeof(msg));
  543. msg.spec = MSG_INITFDPMQUEUE;
  544. msg.len = cpu_to_le16(8);
  545. /* write the tohost queue start address */
  546. addr = DPM_PAGE_ADDR(mod->fastrx_start);
  547. msg.data[0] = addr & 0xff;
  548. msg.data[1] = (addr >> 8) & 0xff;
  549. msg.data[2] = (addr >> 16) & 0xff;
  550. msg.data[3] = (addr >> 24) & 0xff;
  551. /* write the fromhost queue start address */
  552. addr = DPM_PAGE_ADDR(mod->fasttx_start);
  553. msg.data[4] = addr & 0xff;
  554. msg.data[5] = (addr >> 8) & 0xff;
  555. msg.data[6] = (addr >> 16) & 0xff;
  556. msg.data[7] = (addr >> 24) & 0xff;
  557. /* If we're not using the new interface yet, we cannot do this */
  558. WARN_ON(mod->iftype != 1);
  559. return ican3_send_msg(mod, &msg);
  560. }
  561. /*
  562. * Setup the CAN filter to either accept or reject all
  563. * messages from the CAN bus.
  564. */
  565. static int __devinit ican3_set_id_filter(struct ican3_dev *mod, bool accept)
  566. {
  567. struct ican3_msg msg;
  568. int ret;
  569. /* Standard Frame Format */
  570. memset(&msg, 0, sizeof(msg));
  571. msg.spec = MSG_SETAFILMASK;
  572. msg.len = cpu_to_le16(5);
  573. msg.data[0] = 0x00; /* IDLo LSB */
  574. msg.data[1] = 0x00; /* IDLo MSB */
  575. msg.data[2] = 0xff; /* IDHi LSB */
  576. msg.data[3] = 0x07; /* IDHi MSB */
  577. /* accept all frames for fast host if, or reject all frames */
  578. msg.data[4] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT;
  579. ret = ican3_send_msg(mod, &msg);
  580. if (ret)
  581. return ret;
  582. /* Extended Frame Format */
  583. memset(&msg, 0, sizeof(msg));
  584. msg.spec = MSG_SETAFILMASK;
  585. msg.len = cpu_to_le16(13);
  586. msg.data[0] = 0; /* MUX = 0 */
  587. msg.data[1] = 0x00; /* IDLo LSB */
  588. msg.data[2] = 0x00;
  589. msg.data[3] = 0x00;
  590. msg.data[4] = 0x20; /* IDLo MSB */
  591. msg.data[5] = 0xff; /* IDHi LSB */
  592. msg.data[6] = 0xff;
  593. msg.data[7] = 0xff;
  594. msg.data[8] = 0x3f; /* IDHi MSB */
  595. /* accept all frames for fast host if, or reject all frames */
  596. msg.data[9] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT;
  597. return ican3_send_msg(mod, &msg);
  598. }
  599. /*
  600. * Bring the CAN bus online or offline
  601. */
  602. static int ican3_set_bus_state(struct ican3_dev *mod, bool on)
  603. {
  604. struct ican3_msg msg;
  605. memset(&msg, 0, sizeof(msg));
  606. msg.spec = on ? MSG_CONREQ : MSG_COFFREQ;
  607. msg.len = cpu_to_le16(0);
  608. return ican3_send_msg(mod, &msg);
  609. }
  610. static int ican3_set_termination(struct ican3_dev *mod, bool on)
  611. {
  612. struct ican3_msg msg;
  613. memset(&msg, 0, sizeof(msg));
  614. msg.spec = MSG_HWCONF;
  615. msg.len = cpu_to_le16(2);
  616. msg.data[0] = 0x00;
  617. msg.data[1] = on ? HWCONF_TERMINATE_ON : HWCONF_TERMINATE_OFF;
  618. return ican3_send_msg(mod, &msg);
  619. }
  620. static int ican3_send_inquiry(struct ican3_dev *mod, u8 subspec)
  621. {
  622. struct ican3_msg msg;
  623. memset(&msg, 0, sizeof(msg));
  624. msg.spec = MSG_INQUIRY;
  625. msg.len = cpu_to_le16(2);
  626. msg.data[0] = subspec;
  627. msg.data[1] = 0x00;
  628. return ican3_send_msg(mod, &msg);
  629. }
  630. static int ican3_set_buserror(struct ican3_dev *mod, u8 quota)
  631. {
  632. struct ican3_msg msg;
  633. memset(&msg, 0, sizeof(msg));
  634. msg.spec = MSG_CCONFREQ;
  635. msg.len = cpu_to_le16(2);
  636. msg.data[0] = 0x00;
  637. msg.data[1] = quota;
  638. return ican3_send_msg(mod, &msg);
  639. }
  640. /*
  641. * ICAN3 to Linux CAN Frame Conversion
  642. */
  643. static void ican3_to_can_frame(struct ican3_dev *mod,
  644. struct ican3_fast_desc *desc,
  645. struct can_frame *cf)
  646. {
  647. if ((desc->command & ICAN3_CAN_TYPE_MASK) == ICAN3_CAN_TYPE_SFF) {
  648. if (desc->data[1] & ICAN3_SFF_RTR)
  649. cf->can_id |= CAN_RTR_FLAG;
  650. cf->can_id |= desc->data[0] << 3;
  651. cf->can_id |= (desc->data[1] & 0xe0) >> 5;
  652. cf->can_dlc = desc->data[1] & ICAN3_CAN_DLC_MASK;
  653. memcpy(cf->data, &desc->data[2], sizeof(cf->data));
  654. } else {
  655. cf->can_dlc = desc->data[0] & ICAN3_CAN_DLC_MASK;
  656. if (desc->data[0] & ICAN3_EFF_RTR)
  657. cf->can_id |= CAN_RTR_FLAG;
  658. if (desc->data[0] & ICAN3_EFF) {
  659. cf->can_id |= CAN_EFF_FLAG;
  660. cf->can_id |= desc->data[2] << 21; /* 28-21 */
  661. cf->can_id |= desc->data[3] << 13; /* 20-13 */
  662. cf->can_id |= desc->data[4] << 5; /* 12-5 */
  663. cf->can_id |= (desc->data[5] & 0xf8) >> 3;
  664. } else {
  665. cf->can_id |= desc->data[2] << 3; /* 10-3 */
  666. cf->can_id |= desc->data[3] >> 5; /* 2-0 */
  667. }
  668. memcpy(cf->data, &desc->data[6], sizeof(cf->data));
  669. }
  670. }
  671. static void can_frame_to_ican3(struct ican3_dev *mod,
  672. struct can_frame *cf,
  673. struct ican3_fast_desc *desc)
  674. {
  675. /* clear out any stale data in the descriptor */
  676. memset(desc->data, 0, sizeof(desc->data));
  677. /* we always use the extended format, with the ECHO flag set */
  678. desc->command = ICAN3_CAN_TYPE_EFF;
  679. desc->data[0] |= cf->can_dlc;
  680. desc->data[1] |= ICAN3_ECHO;
  681. if (cf->can_id & CAN_RTR_FLAG)
  682. desc->data[0] |= ICAN3_EFF_RTR;
  683. /* pack the id into the correct places */
  684. if (cf->can_id & CAN_EFF_FLAG) {
  685. desc->data[0] |= ICAN3_EFF;
  686. desc->data[2] = (cf->can_id & 0x1fe00000) >> 21; /* 28-21 */
  687. desc->data[3] = (cf->can_id & 0x001fe000) >> 13; /* 20-13 */
  688. desc->data[4] = (cf->can_id & 0x00001fe0) >> 5; /* 12-5 */
  689. desc->data[5] = (cf->can_id & 0x0000001f) << 3; /* 4-0 */
  690. } else {
  691. desc->data[2] = (cf->can_id & 0x7F8) >> 3; /* bits 10-3 */
  692. desc->data[3] = (cf->can_id & 0x007) << 5; /* bits 2-0 */
  693. }
  694. /* copy the data bits into the descriptor */
  695. memcpy(&desc->data[6], cf->data, sizeof(cf->data));
  696. }
  697. /*
  698. * Interrupt Handling
  699. */
  700. /*
  701. * Handle an ID + Version message response from the firmware. We never generate
  702. * this message in production code, but it is very useful when debugging to be
  703. * able to display this message.
  704. */
  705. static void ican3_handle_idvers(struct ican3_dev *mod, struct ican3_msg *msg)
  706. {
  707. dev_dbg(mod->dev, "IDVERS response: %s\n", msg->data);
  708. }
  709. static void ican3_handle_msglost(struct ican3_dev *mod, struct ican3_msg *msg)
  710. {
  711. struct net_device *dev = mod->ndev;
  712. struct net_device_stats *stats = &dev->stats;
  713. struct can_frame *cf;
  714. struct sk_buff *skb;
  715. /*
  716. * Report that communication messages with the microcontroller firmware
  717. * are being lost. These are never CAN frames, so we do not generate an
  718. * error frame for userspace
  719. */
  720. if (msg->spec == MSG_MSGLOST) {
  721. dev_err(mod->dev, "lost %d control messages\n", msg->data[0]);
  722. return;
  723. }
  724. /*
  725. * Oops, this indicates that we have lost messages in the fast queue,
  726. * which are exclusively CAN messages. Our driver isn't reading CAN
  727. * frames fast enough.
  728. *
  729. * We'll pretend that the SJA1000 told us that it ran out of buffer
  730. * space, because there is not a better message for this.
  731. */
  732. skb = alloc_can_err_skb(dev, &cf);
  733. if (skb) {
  734. cf->can_id |= CAN_ERR_CRTL;
  735. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  736. stats->rx_errors++;
  737. stats->rx_bytes += cf->can_dlc;
  738. netif_rx(skb);
  739. }
  740. }
  741. /*
  742. * Handle CAN Event Indication Messages from the firmware
  743. *
  744. * The ICAN3 firmware provides the values of some SJA1000 registers when it
  745. * generates this message. The code below is largely copied from the
  746. * drivers/net/can/sja1000/sja1000.c file, and adapted as necessary
  747. */
  748. static int ican3_handle_cevtind(struct ican3_dev *mod, struct ican3_msg *msg)
  749. {
  750. struct net_device *dev = mod->ndev;
  751. struct net_device_stats *stats = &dev->stats;
  752. enum can_state state = mod->can.state;
  753. u8 status, isrc, rxerr, txerr;
  754. struct can_frame *cf;
  755. struct sk_buff *skb;
  756. /* we can only handle the SJA1000 part */
  757. if (msg->data[1] != CEVTIND_CHIP_SJA1000) {
  758. dev_err(mod->dev, "unable to handle errors on non-SJA1000\n");
  759. return -ENODEV;
  760. }
  761. /* check the message length for sanity */
  762. if (le16_to_cpu(msg->len) < 6) {
  763. dev_err(mod->dev, "error message too short\n");
  764. return -EINVAL;
  765. }
  766. skb = alloc_can_err_skb(dev, &cf);
  767. if (skb == NULL)
  768. return -ENOMEM;
  769. isrc = msg->data[0];
  770. status = msg->data[3];
  771. rxerr = msg->data[4];
  772. txerr = msg->data[5];
  773. /* data overrun interrupt */
  774. if (isrc == CEVTIND_DOI || isrc == CEVTIND_LOST) {
  775. dev_dbg(mod->dev, "data overrun interrupt\n");
  776. cf->can_id |= CAN_ERR_CRTL;
  777. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  778. stats->rx_over_errors++;
  779. stats->rx_errors++;
  780. }
  781. /* error warning + passive interrupt */
  782. if (isrc == CEVTIND_EI) {
  783. dev_dbg(mod->dev, "error warning + passive interrupt\n");
  784. if (status & SR_BS) {
  785. state = CAN_STATE_BUS_OFF;
  786. cf->can_id |= CAN_ERR_BUSOFF;
  787. can_bus_off(dev);
  788. } else if (status & SR_ES) {
  789. if (rxerr >= 128 || txerr >= 128)
  790. state = CAN_STATE_ERROR_PASSIVE;
  791. else
  792. state = CAN_STATE_ERROR_WARNING;
  793. } else {
  794. state = CAN_STATE_ERROR_ACTIVE;
  795. }
  796. }
  797. /* bus error interrupt */
  798. if (isrc == CEVTIND_BEI) {
  799. u8 ecc = msg->data[2];
  800. dev_dbg(mod->dev, "bus error interrupt\n");
  801. mod->can.can_stats.bus_error++;
  802. stats->rx_errors++;
  803. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  804. switch (ecc & ECC_MASK) {
  805. case ECC_BIT:
  806. cf->data[2] |= CAN_ERR_PROT_BIT;
  807. break;
  808. case ECC_FORM:
  809. cf->data[2] |= CAN_ERR_PROT_FORM;
  810. break;
  811. case ECC_STUFF:
  812. cf->data[2] |= CAN_ERR_PROT_STUFF;
  813. break;
  814. default:
  815. cf->data[2] |= CAN_ERR_PROT_UNSPEC;
  816. cf->data[3] = ecc & ECC_SEG;
  817. break;
  818. }
  819. if ((ecc & ECC_DIR) == 0)
  820. cf->data[2] |= CAN_ERR_PROT_TX;
  821. cf->data[6] = txerr;
  822. cf->data[7] = rxerr;
  823. }
  824. if (state != mod->can.state && (state == CAN_STATE_ERROR_WARNING ||
  825. state == CAN_STATE_ERROR_PASSIVE)) {
  826. cf->can_id |= CAN_ERR_CRTL;
  827. if (state == CAN_STATE_ERROR_WARNING) {
  828. mod->can.can_stats.error_warning++;
  829. cf->data[1] = (txerr > rxerr) ?
  830. CAN_ERR_CRTL_TX_WARNING :
  831. CAN_ERR_CRTL_RX_WARNING;
  832. } else {
  833. mod->can.can_stats.error_passive++;
  834. cf->data[1] = (txerr > rxerr) ?
  835. CAN_ERR_CRTL_TX_PASSIVE :
  836. CAN_ERR_CRTL_RX_PASSIVE;
  837. }
  838. cf->data[6] = txerr;
  839. cf->data[7] = rxerr;
  840. }
  841. mod->can.state = state;
  842. stats->rx_errors++;
  843. stats->rx_bytes += cf->can_dlc;
  844. netif_rx(skb);
  845. return 0;
  846. }
  847. static void ican3_handle_inquiry(struct ican3_dev *mod, struct ican3_msg *msg)
  848. {
  849. switch (msg->data[0]) {
  850. case INQUIRY_STATUS:
  851. case INQUIRY_EXTENDED:
  852. mod->bec.rxerr = msg->data[5];
  853. mod->bec.txerr = msg->data[6];
  854. complete(&mod->buserror_comp);
  855. break;
  856. case INQUIRY_TERMINATION:
  857. mod->termination_enabled = msg->data[6] & HWCONF_TERMINATE_ON;
  858. complete(&mod->termination_comp);
  859. break;
  860. default:
  861. dev_err(mod->dev, "received an unknown inquiry response\n");
  862. break;
  863. }
  864. }
  865. static void ican3_handle_unknown_message(struct ican3_dev *mod,
  866. struct ican3_msg *msg)
  867. {
  868. dev_warn(mod->dev, "received unknown message: spec 0x%.2x length %d\n",
  869. msg->spec, le16_to_cpu(msg->len));
  870. }
  871. /*
  872. * Handle a control message from the firmware
  873. */
  874. static void ican3_handle_message(struct ican3_dev *mod, struct ican3_msg *msg)
  875. {
  876. dev_dbg(mod->dev, "%s: modno %d spec 0x%.2x len %d bytes\n", __func__,
  877. mod->num, msg->spec, le16_to_cpu(msg->len));
  878. switch (msg->spec) {
  879. case MSG_IDVERS:
  880. ican3_handle_idvers(mod, msg);
  881. break;
  882. case MSG_MSGLOST:
  883. case MSG_FMSGLOST:
  884. ican3_handle_msglost(mod, msg);
  885. break;
  886. case MSG_CEVTIND:
  887. ican3_handle_cevtind(mod, msg);
  888. break;
  889. case MSG_INQUIRY:
  890. ican3_handle_inquiry(mod, msg);
  891. break;
  892. default:
  893. ican3_handle_unknown_message(mod, msg);
  894. break;
  895. }
  896. }
  897. /*
  898. * Check that there is room in the TX ring to transmit another skb
  899. *
  900. * LOCKING: must hold mod->lock
  901. */
  902. static bool ican3_txok(struct ican3_dev *mod)
  903. {
  904. struct ican3_fast_desc __iomem *desc;
  905. u8 control;
  906. /* copy the control bits of the descriptor */
  907. ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16));
  908. desc = mod->dpm + ((mod->fasttx_num % 16) * sizeof(*desc));
  909. control = ioread8(&desc->control);
  910. /* if the control bits are not valid, then we have no more space */
  911. if (!(control & DESC_VALID))
  912. return false;
  913. return true;
  914. }
  915. /*
  916. * Receive one CAN frame from the hardware
  917. *
  918. * CONTEXT: must be called from user context
  919. */
  920. static int ican3_recv_skb(struct ican3_dev *mod)
  921. {
  922. struct net_device *ndev = mod->ndev;
  923. struct net_device_stats *stats = &ndev->stats;
  924. struct ican3_fast_desc desc;
  925. void __iomem *desc_addr;
  926. struct can_frame *cf;
  927. struct sk_buff *skb;
  928. unsigned long flags;
  929. spin_lock_irqsave(&mod->lock, flags);
  930. /* copy the whole descriptor */
  931. ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16));
  932. desc_addr = mod->dpm + ((mod->fastrx_num % 16) * sizeof(desc));
  933. memcpy_fromio(&desc, desc_addr, sizeof(desc));
  934. spin_unlock_irqrestore(&mod->lock, flags);
  935. /* check that we actually have a CAN frame */
  936. if (!(desc.control & DESC_VALID))
  937. return -ENOBUFS;
  938. /* allocate an skb */
  939. skb = alloc_can_skb(ndev, &cf);
  940. if (unlikely(skb == NULL)) {
  941. stats->rx_dropped++;
  942. goto err_noalloc;
  943. }
  944. /* convert the ICAN3 frame into Linux CAN format */
  945. ican3_to_can_frame(mod, &desc, cf);
  946. /* receive the skb, update statistics */
  947. netif_receive_skb(skb);
  948. stats->rx_packets++;
  949. stats->rx_bytes += cf->can_dlc;
  950. err_noalloc:
  951. /* toggle the valid bit and return the descriptor to the ring */
  952. desc.control ^= DESC_VALID;
  953. spin_lock_irqsave(&mod->lock, flags);
  954. ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16));
  955. memcpy_toio(desc_addr, &desc, 1);
  956. /* update the next buffer pointer */
  957. mod->fastrx_num = (desc.control & DESC_WRAP) ? 0
  958. : (mod->fastrx_num + 1);
  959. /* there are still more buffers to process */
  960. spin_unlock_irqrestore(&mod->lock, flags);
  961. return 0;
  962. }
  963. static int ican3_napi(struct napi_struct *napi, int budget)
  964. {
  965. struct ican3_dev *mod = container_of(napi, struct ican3_dev, napi);
  966. struct ican3_msg msg;
  967. unsigned long flags;
  968. int received = 0;
  969. int ret;
  970. /* process all communication messages */
  971. while (true) {
  972. ret = ican3_recv_msg(mod, &msg);
  973. if (ret)
  974. break;
  975. ican3_handle_message(mod, &msg);
  976. }
  977. /* process all CAN frames from the fast interface */
  978. while (received < budget) {
  979. ret = ican3_recv_skb(mod);
  980. if (ret)
  981. break;
  982. received++;
  983. }
  984. /* We have processed all packets that the adapter had, but it
  985. * was less than our budget, stop polling */
  986. if (received < budget)
  987. napi_complete(napi);
  988. spin_lock_irqsave(&mod->lock, flags);
  989. /* Wake up the transmit queue if necessary */
  990. if (netif_queue_stopped(mod->ndev) && ican3_txok(mod))
  991. netif_wake_queue(mod->ndev);
  992. spin_unlock_irqrestore(&mod->lock, flags);
  993. /* re-enable interrupt generation */
  994. iowrite8(1 << mod->num, &mod->ctrl->int_enable);
  995. return received;
  996. }
  997. static irqreturn_t ican3_irq(int irq, void *dev_id)
  998. {
  999. struct ican3_dev *mod = dev_id;
  1000. u8 stat;
  1001. /*
  1002. * The interrupt status register on this device reports interrupts
  1003. * as zeroes instead of using ones like most other devices
  1004. */
  1005. stat = ioread8(&mod->ctrl->int_disable) & (1 << mod->num);
  1006. if (stat == (1 << mod->num))
  1007. return IRQ_NONE;
  1008. /* clear the MODULbus interrupt from the microcontroller */
  1009. ioread8(&mod->dpmctrl->interrupt);
  1010. /* disable interrupt generation, schedule the NAPI poller */
  1011. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1012. napi_schedule(&mod->napi);
  1013. return IRQ_HANDLED;
  1014. }
  1015. /*
  1016. * Firmware reset, startup, and shutdown
  1017. */
  1018. /*
  1019. * Reset an ICAN module to its power-on state
  1020. *
  1021. * CONTEXT: no network device registered
  1022. */
  1023. static int ican3_reset_module(struct ican3_dev *mod)
  1024. {
  1025. unsigned long start;
  1026. u8 runold, runnew;
  1027. /* disable interrupts so no more work is scheduled */
  1028. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1029. /* the first unallocated page in the DPM is #9 */
  1030. mod->free_page = DPM_FREE_START;
  1031. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  1032. runold = ioread8(mod->dpm + TARGET_RUNNING);
  1033. /* reset the module */
  1034. iowrite8(0x00, &mod->dpmctrl->hwreset);
  1035. /* wait until the module has finished resetting and is running */
  1036. start = jiffies;
  1037. do {
  1038. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  1039. runnew = ioread8(mod->dpm + TARGET_RUNNING);
  1040. if (runnew == (runold ^ 0xff))
  1041. return 0;
  1042. msleep(10);
  1043. } while (time_before(jiffies, start + HZ / 4));
  1044. dev_err(mod->dev, "failed to reset CAN module\n");
  1045. return -ETIMEDOUT;
  1046. }
  1047. static void __devexit ican3_shutdown_module(struct ican3_dev *mod)
  1048. {
  1049. ican3_msg_disconnect(mod);
  1050. ican3_reset_module(mod);
  1051. }
  1052. /*
  1053. * Startup an ICAN module, bringing it into fast mode
  1054. */
  1055. static int __devinit ican3_startup_module(struct ican3_dev *mod)
  1056. {
  1057. int ret;
  1058. ret = ican3_reset_module(mod);
  1059. if (ret) {
  1060. dev_err(mod->dev, "unable to reset module\n");
  1061. return ret;
  1062. }
  1063. /* re-enable interrupts so we can send messages */
  1064. iowrite8(1 << mod->num, &mod->ctrl->int_enable);
  1065. ret = ican3_msg_connect(mod);
  1066. if (ret) {
  1067. dev_err(mod->dev, "unable to connect to module\n");
  1068. return ret;
  1069. }
  1070. ican3_init_new_host_interface(mod);
  1071. ret = ican3_msg_newhostif(mod);
  1072. if (ret) {
  1073. dev_err(mod->dev, "unable to switch to new-style interface\n");
  1074. return ret;
  1075. }
  1076. /* default to "termination on" */
  1077. ret = ican3_set_termination(mod, true);
  1078. if (ret) {
  1079. dev_err(mod->dev, "unable to enable termination\n");
  1080. return ret;
  1081. }
  1082. /* default to "bus errors enabled" */
  1083. ret = ican3_set_buserror(mod, ICAN3_BUSERR_QUOTA_MAX);
  1084. if (ret) {
  1085. dev_err(mod->dev, "unable to set bus-error\n");
  1086. return ret;
  1087. }
  1088. ican3_init_fast_host_interface(mod);
  1089. ret = ican3_msg_fasthostif(mod);
  1090. if (ret) {
  1091. dev_err(mod->dev, "unable to switch to fast host interface\n");
  1092. return ret;
  1093. }
  1094. ret = ican3_set_id_filter(mod, true);
  1095. if (ret) {
  1096. dev_err(mod->dev, "unable to set acceptance filter\n");
  1097. return ret;
  1098. }
  1099. return 0;
  1100. }
  1101. /*
  1102. * CAN Network Device
  1103. */
  1104. static int ican3_open(struct net_device *ndev)
  1105. {
  1106. struct ican3_dev *mod = netdev_priv(ndev);
  1107. u8 quota;
  1108. int ret;
  1109. /* open the CAN layer */
  1110. ret = open_candev(ndev);
  1111. if (ret) {
  1112. dev_err(mod->dev, "unable to start CAN layer\n");
  1113. return ret;
  1114. }
  1115. /* set the bus error generation state appropriately */
  1116. if (mod->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
  1117. quota = ICAN3_BUSERR_QUOTA_MAX;
  1118. else
  1119. quota = 0;
  1120. ret = ican3_set_buserror(mod, quota);
  1121. if (ret) {
  1122. dev_err(mod->dev, "unable to set bus-error\n");
  1123. close_candev(ndev);
  1124. return ret;
  1125. }
  1126. /* bring the bus online */
  1127. ret = ican3_set_bus_state(mod, true);
  1128. if (ret) {
  1129. dev_err(mod->dev, "unable to set bus-on\n");
  1130. close_candev(ndev);
  1131. return ret;
  1132. }
  1133. /* start up the network device */
  1134. mod->can.state = CAN_STATE_ERROR_ACTIVE;
  1135. netif_start_queue(ndev);
  1136. return 0;
  1137. }
  1138. static int ican3_stop(struct net_device *ndev)
  1139. {
  1140. struct ican3_dev *mod = netdev_priv(ndev);
  1141. int ret;
  1142. /* stop the network device xmit routine */
  1143. netif_stop_queue(ndev);
  1144. mod->can.state = CAN_STATE_STOPPED;
  1145. /* bring the bus offline, stop receiving packets */
  1146. ret = ican3_set_bus_state(mod, false);
  1147. if (ret) {
  1148. dev_err(mod->dev, "unable to set bus-off\n");
  1149. return ret;
  1150. }
  1151. /* close the CAN layer */
  1152. close_candev(ndev);
  1153. return 0;
  1154. }
  1155. static int ican3_xmit(struct sk_buff *skb, struct net_device *ndev)
  1156. {
  1157. struct ican3_dev *mod = netdev_priv(ndev);
  1158. struct net_device_stats *stats = &ndev->stats;
  1159. struct can_frame *cf = (struct can_frame *)skb->data;
  1160. struct ican3_fast_desc desc;
  1161. void __iomem *desc_addr;
  1162. unsigned long flags;
  1163. spin_lock_irqsave(&mod->lock, flags);
  1164. /* check that we can actually transmit */
  1165. if (!ican3_txok(mod)) {
  1166. dev_err(mod->dev, "no free descriptors, stopping queue\n");
  1167. netif_stop_queue(ndev);
  1168. spin_unlock_irqrestore(&mod->lock, flags);
  1169. return NETDEV_TX_BUSY;
  1170. }
  1171. /* copy the control bits of the descriptor */
  1172. ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16));
  1173. desc_addr = mod->dpm + ((mod->fasttx_num % 16) * sizeof(desc));
  1174. memset(&desc, 0, sizeof(desc));
  1175. memcpy_fromio(&desc, desc_addr, 1);
  1176. /* convert the Linux CAN frame into ICAN3 format */
  1177. can_frame_to_ican3(mod, cf, &desc);
  1178. /*
  1179. * the programming manual says that you must set the IVALID bit, then
  1180. * interrupt, then set the valid bit. Quite weird, but it seems to be
  1181. * required for this to work
  1182. */
  1183. desc.control |= DESC_IVALID;
  1184. memcpy_toio(desc_addr, &desc, sizeof(desc));
  1185. /* generate a MODULbus interrupt to the microcontroller */
  1186. iowrite8(0x01, &mod->dpmctrl->interrupt);
  1187. desc.control ^= DESC_VALID;
  1188. memcpy_toio(desc_addr, &desc, sizeof(desc));
  1189. /* update the next buffer pointer */
  1190. mod->fasttx_num = (desc.control & DESC_WRAP) ? 0
  1191. : (mod->fasttx_num + 1);
  1192. /* update statistics */
  1193. stats->tx_packets++;
  1194. stats->tx_bytes += cf->can_dlc;
  1195. kfree_skb(skb);
  1196. /*
  1197. * This hardware doesn't have TX-done notifications, so we'll try and
  1198. * emulate it the best we can using ECHO skbs. Get the next TX
  1199. * descriptor, and see if we have room to send. If not, stop the queue.
  1200. * It will be woken when the ECHO skb for the current packet is recv'd.
  1201. */
  1202. /* copy the control bits of the descriptor */
  1203. if (!ican3_txok(mod))
  1204. netif_stop_queue(ndev);
  1205. spin_unlock_irqrestore(&mod->lock, flags);
  1206. return NETDEV_TX_OK;
  1207. }
  1208. static const struct net_device_ops ican3_netdev_ops = {
  1209. .ndo_open = ican3_open,
  1210. .ndo_stop = ican3_stop,
  1211. .ndo_start_xmit = ican3_xmit,
  1212. };
  1213. /*
  1214. * Low-level CAN Device
  1215. */
  1216. /* This structure was stolen from drivers/net/can/sja1000/sja1000.c */
  1217. static struct can_bittiming_const ican3_bittiming_const = {
  1218. .name = DRV_NAME,
  1219. .tseg1_min = 1,
  1220. .tseg1_max = 16,
  1221. .tseg2_min = 1,
  1222. .tseg2_max = 8,
  1223. .sjw_max = 4,
  1224. .brp_min = 1,
  1225. .brp_max = 64,
  1226. .brp_inc = 1,
  1227. };
  1228. /*
  1229. * This routine was stolen from drivers/net/can/sja1000/sja1000.c
  1230. *
  1231. * The bittiming register command for the ICAN3 just sets the bit timing
  1232. * registers on the SJA1000 chip directly
  1233. */
  1234. static int ican3_set_bittiming(struct net_device *ndev)
  1235. {
  1236. struct ican3_dev *mod = netdev_priv(ndev);
  1237. struct can_bittiming *bt = &mod->can.bittiming;
  1238. struct ican3_msg msg;
  1239. u8 btr0, btr1;
  1240. btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6);
  1241. btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) |
  1242. (((bt->phase_seg2 - 1) & 0x7) << 4);
  1243. if (mod->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
  1244. btr1 |= 0x80;
  1245. memset(&msg, 0, sizeof(msg));
  1246. msg.spec = MSG_CBTRREQ;
  1247. msg.len = cpu_to_le16(4);
  1248. msg.data[0] = 0x00;
  1249. msg.data[1] = 0x00;
  1250. msg.data[2] = btr0;
  1251. msg.data[3] = btr1;
  1252. return ican3_send_msg(mod, &msg);
  1253. }
  1254. static int ican3_set_mode(struct net_device *ndev, enum can_mode mode)
  1255. {
  1256. struct ican3_dev *mod = netdev_priv(ndev);
  1257. int ret;
  1258. if (mode != CAN_MODE_START)
  1259. return -ENOTSUPP;
  1260. /* bring the bus online */
  1261. ret = ican3_set_bus_state(mod, true);
  1262. if (ret) {
  1263. dev_err(mod->dev, "unable to set bus-on\n");
  1264. return ret;
  1265. }
  1266. /* start up the network device */
  1267. mod->can.state = CAN_STATE_ERROR_ACTIVE;
  1268. if (netif_queue_stopped(ndev))
  1269. netif_wake_queue(ndev);
  1270. return 0;
  1271. }
  1272. static int ican3_get_berr_counter(const struct net_device *ndev,
  1273. struct can_berr_counter *bec)
  1274. {
  1275. struct ican3_dev *mod = netdev_priv(ndev);
  1276. int ret;
  1277. ret = ican3_send_inquiry(mod, INQUIRY_STATUS);
  1278. if (ret)
  1279. return ret;
  1280. ret = wait_for_completion_timeout(&mod->buserror_comp, HZ);
  1281. if (ret <= 0) {
  1282. dev_info(mod->dev, "%s timed out\n", __func__);
  1283. return -ETIMEDOUT;
  1284. }
  1285. bec->rxerr = mod->bec.rxerr;
  1286. bec->txerr = mod->bec.txerr;
  1287. return 0;
  1288. }
  1289. /*
  1290. * Sysfs Attributes
  1291. */
  1292. static ssize_t ican3_sysfs_show_term(struct device *dev,
  1293. struct device_attribute *attr,
  1294. char *buf)
  1295. {
  1296. struct ican3_dev *mod = netdev_priv(to_net_dev(dev));
  1297. int ret;
  1298. ret = ican3_send_inquiry(mod, INQUIRY_TERMINATION);
  1299. if (ret)
  1300. return ret;
  1301. ret = wait_for_completion_timeout(&mod->termination_comp, HZ);
  1302. if (ret <= 0) {
  1303. dev_info(mod->dev, "%s timed out\n", __func__);
  1304. return -ETIMEDOUT;
  1305. }
  1306. return snprintf(buf, PAGE_SIZE, "%u\n", mod->termination_enabled);
  1307. }
  1308. static ssize_t ican3_sysfs_set_term(struct device *dev,
  1309. struct device_attribute *attr,
  1310. const char *buf, size_t count)
  1311. {
  1312. struct ican3_dev *mod = netdev_priv(to_net_dev(dev));
  1313. unsigned long enable;
  1314. int ret;
  1315. if (strict_strtoul(buf, 0, &enable))
  1316. return -EINVAL;
  1317. ret = ican3_set_termination(mod, enable);
  1318. if (ret)
  1319. return ret;
  1320. return count;
  1321. }
  1322. static DEVICE_ATTR(termination, S_IWUSR | S_IRUGO, ican3_sysfs_show_term,
  1323. ican3_sysfs_set_term);
  1324. static struct attribute *ican3_sysfs_attrs[] = {
  1325. &dev_attr_termination.attr,
  1326. NULL,
  1327. };
  1328. static struct attribute_group ican3_sysfs_attr_group = {
  1329. .attrs = ican3_sysfs_attrs,
  1330. };
  1331. /*
  1332. * PCI Subsystem
  1333. */
  1334. static int __devinit ican3_probe(struct platform_device *pdev)
  1335. {
  1336. struct janz_platform_data *pdata;
  1337. struct net_device *ndev;
  1338. struct ican3_dev *mod;
  1339. struct resource *res;
  1340. struct device *dev;
  1341. int ret;
  1342. pdata = pdev->dev.platform_data;
  1343. if (!pdata)
  1344. return -ENXIO;
  1345. dev_dbg(&pdev->dev, "probe: module number %d\n", pdata->modno);
  1346. /* save the struct device for printing */
  1347. dev = &pdev->dev;
  1348. /* allocate the CAN device and private data */
  1349. ndev = alloc_candev(sizeof(*mod), 0);
  1350. if (!ndev) {
  1351. dev_err(dev, "unable to allocate CANdev\n");
  1352. ret = -ENOMEM;
  1353. goto out_return;
  1354. }
  1355. platform_set_drvdata(pdev, ndev);
  1356. mod = netdev_priv(ndev);
  1357. mod->ndev = ndev;
  1358. mod->dev = &pdev->dev;
  1359. mod->num = pdata->modno;
  1360. netif_napi_add(ndev, &mod->napi, ican3_napi, ICAN3_RX_BUFFERS);
  1361. spin_lock_init(&mod->lock);
  1362. init_completion(&mod->termination_comp);
  1363. init_completion(&mod->buserror_comp);
  1364. /* setup device-specific sysfs attributes */
  1365. ndev->sysfs_groups[0] = &ican3_sysfs_attr_group;
  1366. /* the first unallocated page in the DPM is 9 */
  1367. mod->free_page = DPM_FREE_START;
  1368. ndev->netdev_ops = &ican3_netdev_ops;
  1369. ndev->flags |= IFF_ECHO;
  1370. SET_NETDEV_DEV(ndev, &pdev->dev);
  1371. mod->can.clock.freq = ICAN3_CAN_CLOCK;
  1372. mod->can.bittiming_const = &ican3_bittiming_const;
  1373. mod->can.do_set_bittiming = ican3_set_bittiming;
  1374. mod->can.do_set_mode = ican3_set_mode;
  1375. mod->can.do_get_berr_counter = ican3_get_berr_counter;
  1376. mod->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES
  1377. | CAN_CTRLMODE_BERR_REPORTING;
  1378. /* find our IRQ number */
  1379. mod->irq = platform_get_irq(pdev, 0);
  1380. if (mod->irq < 0) {
  1381. dev_err(dev, "IRQ line not found\n");
  1382. ret = -ENODEV;
  1383. goto out_free_ndev;
  1384. }
  1385. ndev->irq = mod->irq;
  1386. /* get access to the MODULbus registers for this module */
  1387. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1388. if (!res) {
  1389. dev_err(dev, "MODULbus registers not found\n");
  1390. ret = -ENODEV;
  1391. goto out_free_ndev;
  1392. }
  1393. mod->dpm = ioremap(res->start, resource_size(res));
  1394. if (!mod->dpm) {
  1395. dev_err(dev, "MODULbus registers not ioremap\n");
  1396. ret = -ENOMEM;
  1397. goto out_free_ndev;
  1398. }
  1399. mod->dpmctrl = mod->dpm + DPM_PAGE_SIZE;
  1400. /* get access to the control registers for this module */
  1401. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1402. if (!res) {
  1403. dev_err(dev, "CONTROL registers not found\n");
  1404. ret = -ENODEV;
  1405. goto out_iounmap_dpm;
  1406. }
  1407. mod->ctrl = ioremap(res->start, resource_size(res));
  1408. if (!mod->ctrl) {
  1409. dev_err(dev, "CONTROL registers not ioremap\n");
  1410. ret = -ENOMEM;
  1411. goto out_iounmap_dpm;
  1412. }
  1413. /* disable our IRQ, then hookup the IRQ handler */
  1414. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1415. ret = request_irq(mod->irq, ican3_irq, IRQF_SHARED, DRV_NAME, mod);
  1416. if (ret) {
  1417. dev_err(dev, "unable to request IRQ\n");
  1418. goto out_iounmap_ctrl;
  1419. }
  1420. /* reset and initialize the CAN controller into fast mode */
  1421. napi_enable(&mod->napi);
  1422. ret = ican3_startup_module(mod);
  1423. if (ret) {
  1424. dev_err(dev, "%s: unable to start CANdev\n", __func__);
  1425. goto out_free_irq;
  1426. }
  1427. /* register with the Linux CAN layer */
  1428. ret = register_candev(ndev);
  1429. if (ret) {
  1430. dev_err(dev, "%s: unable to register CANdev\n", __func__);
  1431. goto out_free_irq;
  1432. }
  1433. dev_info(dev, "module %d: registered CAN device\n", pdata->modno);
  1434. return 0;
  1435. out_free_irq:
  1436. napi_disable(&mod->napi);
  1437. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1438. free_irq(mod->irq, mod);
  1439. out_iounmap_ctrl:
  1440. iounmap(mod->ctrl);
  1441. out_iounmap_dpm:
  1442. iounmap(mod->dpm);
  1443. out_free_ndev:
  1444. free_candev(ndev);
  1445. out_return:
  1446. return ret;
  1447. }
  1448. static int __devexit ican3_remove(struct platform_device *pdev)
  1449. {
  1450. struct net_device *ndev = platform_get_drvdata(pdev);
  1451. struct ican3_dev *mod = netdev_priv(ndev);
  1452. /* unregister the netdevice, stop interrupts */
  1453. unregister_netdev(ndev);
  1454. napi_disable(&mod->napi);
  1455. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1456. free_irq(mod->irq, mod);
  1457. /* put the module into reset */
  1458. ican3_shutdown_module(mod);
  1459. /* unmap all registers */
  1460. iounmap(mod->ctrl);
  1461. iounmap(mod->dpm);
  1462. free_candev(ndev);
  1463. return 0;
  1464. }
  1465. static struct platform_driver ican3_driver = {
  1466. .driver = {
  1467. .name = DRV_NAME,
  1468. .owner = THIS_MODULE,
  1469. },
  1470. .probe = ican3_probe,
  1471. .remove = __devexit_p(ican3_remove),
  1472. };
  1473. module_platform_driver(ican3_driver);
  1474. MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
  1475. MODULE_DESCRIPTION("Janz MODULbus VMOD-ICAN3 Driver");
  1476. MODULE_LICENSE("GPL");
  1477. MODULE_ALIAS("platform:janz-ican3");