s5p_mfc_shm.h 2.9 KB

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  1. /*
  2. * linux/drivers/media/video/s5p-mfc/s5p_mfc_shm.h
  3. *
  4. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com/
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. */
  12. #ifndef S5P_MFC_SHM_H_
  13. #define S5P_MFC_SHM_H_
  14. enum MFC_SHM_OFS
  15. {
  16. EXTENEDED_DECODE_STATUS = 0x00, /* D */
  17. SET_FRAME_TAG = 0x04, /* D */
  18. GET_FRAME_TAG_TOP = 0x08, /* D */
  19. GET_FRAME_TAG_BOT = 0x0C, /* D */
  20. PIC_TIME_TOP = 0x10, /* D */
  21. PIC_TIME_BOT = 0x14, /* D */
  22. START_BYTE_NUM = 0x18, /* D */
  23. CROP_INFO_H = 0x20, /* D */
  24. CROP_INFO_V = 0x24, /* D */
  25. EXT_ENC_CONTROL = 0x28, /* E */
  26. ENC_PARAM_CHANGE = 0x2C, /* E */
  27. RC_VOP_TIMING = 0x30, /* E, MPEG4 */
  28. HEC_PERIOD = 0x34, /* E, MPEG4 */
  29. METADATA_ENABLE = 0x38, /* C */
  30. METADATA_STATUS = 0x3C, /* C */
  31. METADATA_DISPLAY_INDEX = 0x40, /* C */
  32. EXT_METADATA_START_ADDR = 0x44, /* C */
  33. PUT_EXTRADATA = 0x48, /* C */
  34. EXTRADATA_ADDR = 0x4C, /* C */
  35. ALLOC_LUMA_DPB_SIZE = 0x64, /* D */
  36. ALLOC_CHROMA_DPB_SIZE = 0x68, /* D */
  37. ALLOC_MV_SIZE = 0x6C, /* D */
  38. P_B_FRAME_QP = 0x70, /* E */
  39. SAMPLE_ASPECT_RATIO_IDC = 0x74, /* E, H.264, depend on
  40. ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
  41. EXTENDED_SAR = 0x78, /* E, H.264, depned on
  42. ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */
  43. DISP_PIC_PROFILE = 0x7C, /* D */
  44. FLUSH_CMD_TYPE = 0x80, /* C */
  45. FLUSH_CMD_INBUF1 = 0x84, /* C */
  46. FLUSH_CMD_INBUF2 = 0x88, /* C */
  47. FLUSH_CMD_OUTBUF = 0x8C, /* E */
  48. NEW_RC_BIT_RATE = 0x90, /* E, format as RC_BIT_RATE(0xC5A8)
  49. depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */
  50. NEW_RC_FRAME_RATE = 0x94, /* E, format as RC_FRAME_RATE(0xD0D0)
  51. depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */
  52. NEW_I_PERIOD = 0x98, /* E, format as I_FRM_CTRL(0xC504)
  53. depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */
  54. H264_I_PERIOD = 0x9C, /* E, H.264, open GOP */
  55. RC_CONTROL_CONFIG = 0xA0, /* E */
  56. BATCH_INPUT_ADDR = 0xA4, /* E */
  57. BATCH_OUTPUT_ADDR = 0xA8, /* E */
  58. BATCH_OUTPUT_SIZE = 0xAC, /* E */
  59. MIN_LUMA_DPB_SIZE = 0xB0, /* D */
  60. DEVICE_FORMAT_ID = 0xB4, /* C */
  61. H264_POC_TYPE = 0xB8, /* D */
  62. MIN_CHROMA_DPB_SIZE = 0xBC, /* D */
  63. DISP_PIC_FRAME_TYPE = 0xC0, /* D */
  64. FREE_LUMA_DPB = 0xC4, /* D, VC1 MPEG4 */
  65. ASPECT_RATIO_INFO = 0xC8, /* D, MPEG4 */
  66. EXTENDED_PAR = 0xCC, /* D, MPEG4 */
  67. DBG_HISTORY_INPUT0 = 0xD0, /* C */
  68. DBG_HISTORY_INPUT1 = 0xD4, /* C */
  69. DBG_HISTORY_OUTPUT = 0xD8, /* C */
  70. HIERARCHICAL_P_QP = 0xE0, /* E, H.264 */
  71. };
  72. int s5p_mfc_init_shm(struct s5p_mfc_ctx *ctx);
  73. #define s5p_mfc_write_shm(ctx, x, ofs) \
  74. do { \
  75. writel(x, (ctx->shm + ofs)); \
  76. wmb(); \
  77. } while (0)
  78. static inline u32 s5p_mfc_read_shm(struct s5p_mfc_ctx *ctx, unsigned int ofs)
  79. {
  80. rmb();
  81. return readl(ctx->shm + ofs);
  82. }
  83. #endif /* S5P_MFC_SHM_H_ */