k10temp.c 6.9 KB

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  1. /*
  2. * k10temp.c - AMD Family 10h/11h/12h/14h/15h processor hardware monitoring
  3. *
  4. * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License; either
  9. * version 2 of the License, or (at your option) any later version.
  10. *
  11. * This driver is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14. * See the GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this driver; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/err.h>
  20. #include <linux/hwmon.h>
  21. #include <linux/hwmon-sysfs.h>
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/pci.h>
  25. #include <asm/processor.h>
  26. MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
  27. MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  28. MODULE_LICENSE("GPL");
  29. static bool force;
  30. module_param(force, bool, 0444);
  31. MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
  32. /* PCI-IDs for Northbridge devices not used anywhere else */
  33. #define PCI_DEVICE_ID_AMD_15H_M10H_NB_F3 0x1403
  34. /* CPUID function 0x80000001, ebx */
  35. #define CPUID_PKGTYPE_MASK 0xf0000000
  36. #define CPUID_PKGTYPE_F 0x00000000
  37. #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
  38. /* DRAM controller (PCI function 2) */
  39. #define REG_DCT0_CONFIG_HIGH 0x094
  40. #define DDR3_MODE 0x00000100
  41. /* miscellaneous (PCI function 3) */
  42. #define REG_HARDWARE_THERMAL_CONTROL 0x64
  43. #define HTC_ENABLE 0x00000001
  44. #define REG_REPORTED_TEMPERATURE 0xa4
  45. #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
  46. #define NB_CAP_HTC 0x00000400
  47. static ssize_t show_temp(struct device *dev,
  48. struct device_attribute *attr, char *buf)
  49. {
  50. u32 regval;
  51. pci_read_config_dword(to_pci_dev(dev),
  52. REG_REPORTED_TEMPERATURE, &regval);
  53. return sprintf(buf, "%u\n", (regval >> 21) * 125);
  54. }
  55. static ssize_t show_temp_max(struct device *dev,
  56. struct device_attribute *attr, char *buf)
  57. {
  58. return sprintf(buf, "%d\n", 70 * 1000);
  59. }
  60. static ssize_t show_temp_crit(struct device *dev,
  61. struct device_attribute *devattr, char *buf)
  62. {
  63. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  64. int show_hyst = attr->index;
  65. u32 regval;
  66. int value;
  67. pci_read_config_dword(to_pci_dev(dev),
  68. REG_HARDWARE_THERMAL_CONTROL, &regval);
  69. value = ((regval >> 16) & 0x7f) * 500 + 52000;
  70. if (show_hyst)
  71. value -= ((regval >> 24) & 0xf) * 500;
  72. return sprintf(buf, "%d\n", value);
  73. }
  74. static ssize_t show_name(struct device *dev,
  75. struct device_attribute *attr, char *buf)
  76. {
  77. return sprintf(buf, "k10temp\n");
  78. }
  79. static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL);
  80. static DEVICE_ATTR(temp1_max, S_IRUGO, show_temp_max, NULL);
  81. static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
  82. static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
  83. static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
  84. static bool __devinit has_erratum_319(struct pci_dev *pdev)
  85. {
  86. u32 pkg_type, reg_dram_cfg;
  87. if (boot_cpu_data.x86 != 0x10)
  88. return false;
  89. /*
  90. * Erratum 319: The thermal sensor of Socket F/AM2+ processors
  91. * may be unreliable.
  92. */
  93. pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
  94. if (pkg_type == CPUID_PKGTYPE_F)
  95. return true;
  96. if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
  97. return false;
  98. /* DDR3 memory implies socket AM3, which is good */
  99. pci_bus_read_config_dword(pdev->bus,
  100. PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
  101. REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
  102. if (reg_dram_cfg & DDR3_MODE)
  103. return false;
  104. /*
  105. * Unfortunately it is possible to run a socket AM3 CPU with DDR2
  106. * memory. We blacklist all the cores which do exist in socket AM2+
  107. * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
  108. * and AM3 formats, but that's the best we can do.
  109. */
  110. return boot_cpu_data.x86_model < 4 ||
  111. (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
  112. }
  113. static int __devinit k10temp_probe(struct pci_dev *pdev,
  114. const struct pci_device_id *id)
  115. {
  116. struct device *hwmon_dev;
  117. u32 reg_caps, reg_htc;
  118. int unreliable = has_erratum_319(pdev);
  119. int err;
  120. if (unreliable && !force) {
  121. dev_err(&pdev->dev,
  122. "unreliable CPU thermal sensor; monitoring disabled\n");
  123. err = -ENODEV;
  124. goto exit;
  125. }
  126. err = device_create_file(&pdev->dev, &dev_attr_temp1_input);
  127. if (err)
  128. goto exit;
  129. err = device_create_file(&pdev->dev, &dev_attr_temp1_max);
  130. if (err)
  131. goto exit_remove;
  132. pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES, &reg_caps);
  133. pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, &reg_htc);
  134. if ((reg_caps & NB_CAP_HTC) && (reg_htc & HTC_ENABLE)) {
  135. err = device_create_file(&pdev->dev,
  136. &sensor_dev_attr_temp1_crit.dev_attr);
  137. if (err)
  138. goto exit_remove;
  139. err = device_create_file(&pdev->dev,
  140. &sensor_dev_attr_temp1_crit_hyst.dev_attr);
  141. if (err)
  142. goto exit_remove;
  143. }
  144. err = device_create_file(&pdev->dev, &dev_attr_name);
  145. if (err)
  146. goto exit_remove;
  147. hwmon_dev = hwmon_device_register(&pdev->dev);
  148. if (IS_ERR(hwmon_dev)) {
  149. err = PTR_ERR(hwmon_dev);
  150. goto exit_remove;
  151. }
  152. pci_set_drvdata(pdev, hwmon_dev);
  153. if (unreliable && force)
  154. dev_warn(&pdev->dev,
  155. "unreliable CPU thermal sensor; check erratum 319\n");
  156. return 0;
  157. exit_remove:
  158. device_remove_file(&pdev->dev, &dev_attr_name);
  159. device_remove_file(&pdev->dev, &dev_attr_temp1_input);
  160. device_remove_file(&pdev->dev, &dev_attr_temp1_max);
  161. device_remove_file(&pdev->dev,
  162. &sensor_dev_attr_temp1_crit.dev_attr);
  163. device_remove_file(&pdev->dev,
  164. &sensor_dev_attr_temp1_crit_hyst.dev_attr);
  165. exit:
  166. return err;
  167. }
  168. static void __devexit k10temp_remove(struct pci_dev *pdev)
  169. {
  170. hwmon_device_unregister(pci_get_drvdata(pdev));
  171. device_remove_file(&pdev->dev, &dev_attr_name);
  172. device_remove_file(&pdev->dev, &dev_attr_temp1_input);
  173. device_remove_file(&pdev->dev, &dev_attr_temp1_max);
  174. device_remove_file(&pdev->dev,
  175. &sensor_dev_attr_temp1_crit.dev_attr);
  176. device_remove_file(&pdev->dev,
  177. &sensor_dev_attr_temp1_crit_hyst.dev_attr);
  178. pci_set_drvdata(pdev, NULL);
  179. }
  180. static DEFINE_PCI_DEVICE_TABLE(k10temp_id_table) = {
  181. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
  182. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
  183. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
  184. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
  185. { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_NB_F3) },
  186. {}
  187. };
  188. MODULE_DEVICE_TABLE(pci, k10temp_id_table);
  189. static struct pci_driver k10temp_driver = {
  190. .name = "k10temp",
  191. .id_table = k10temp_id_table,
  192. .probe = k10temp_probe,
  193. .remove = __devexit_p(k10temp_remove),
  194. };
  195. static int __init k10temp_init(void)
  196. {
  197. return pci_register_driver(&k10temp_driver);
  198. }
  199. static void __exit k10temp_exit(void)
  200. {
  201. pci_unregister_driver(&k10temp_driver);
  202. }
  203. module_init(k10temp_init)
  204. module_exit(k10temp_exit)