clksrc-dbx500-prcmu.c 2.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293
  1. /*
  2. * Copyright (C) ST-Ericsson SA 2011
  3. *
  4. * License Terms: GNU General Public License v2
  5. * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
  6. * Author: Sundar Iyer for ST-Ericsson
  7. * sched_clock implementation is based on:
  8. * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
  9. *
  10. * DBx500-PRCMU Timer
  11. * The PRCMU has 5 timers which are available in a always-on
  12. * power domain. We use the Timer 4 for our always-on clock
  13. * source on DB8500 and Timer 3 on DB5500.
  14. */
  15. #include <linux/clockchips.h>
  16. #include <linux/clksrc-dbx500-prcmu.h>
  17. #include <linux/sched_clock.h>
  18. #include <mach/setup.h>
  19. #include <mach/hardware.h>
  20. #define RATE_32K 32768
  21. #define TIMER_MODE_CONTINOUS 0x1
  22. #define TIMER_DOWNCOUNT_VAL 0xffffffff
  23. #define PRCMU_TIMER_REF 0
  24. #define PRCMU_TIMER_DOWNCOUNT 0x4
  25. #define PRCMU_TIMER_MODE 0x8
  26. #define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
  27. static void __iomem *clksrc_dbx500_timer_base;
  28. static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs)
  29. {
  30. u32 count, count2;
  31. do {
  32. count = readl(clksrc_dbx500_timer_base +
  33. PRCMU_TIMER_DOWNCOUNT);
  34. count2 = readl(clksrc_dbx500_timer_base +
  35. PRCMU_TIMER_DOWNCOUNT);
  36. } while (count2 != count);
  37. /* Negate because the timer is a decrementing counter */
  38. return ~count;
  39. }
  40. static struct clocksource clocksource_dbx500_prcmu = {
  41. .name = "dbx500-prcmu-timer",
  42. .rating = 300,
  43. .read = clksrc_dbx500_prcmu_read,
  44. .mask = CLOCKSOURCE_MASK(32),
  45. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  46. };
  47. #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
  48. static u32 notrace dbx500_prcmu_sched_clock_read(void)
  49. {
  50. if (unlikely(!clksrc_dbx500_timer_base))
  51. return 0;
  52. return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
  53. }
  54. #endif
  55. void __init clksrc_dbx500_prcmu_init(void __iomem *base)
  56. {
  57. clksrc_dbx500_timer_base = base;
  58. /*
  59. * The A9 sub system expects the timer to be configured as
  60. * a continous looping timer.
  61. * The PRCMU should configure it but if it for some reason
  62. * don't we do it here.
  63. */
  64. if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
  65. TIMER_MODE_CONTINOUS) {
  66. writel(TIMER_MODE_CONTINOUS,
  67. clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
  68. writel(TIMER_DOWNCOUNT_VAL,
  69. clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
  70. }
  71. #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
  72. setup_sched_clock(dbx500_prcmu_sched_clock_read,
  73. 32, RATE_32K);
  74. #endif
  75. clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
  76. }