setup.c 4.3 KB

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  1. /*
  2. * linux/arch/m32r/platforms/mappi2/setup.c
  3. *
  4. * Setup routines for Renesas MAPPI-II(M3A-ZA36) Board
  5. *
  6. * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
  7. * Hitoshi Yamamoto, Mamoru Sakugawa
  8. */
  9. #include <linux/irq.h>
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/platform_device.h>
  13. #include <asm/m32r.h>
  14. #include <asm/io.h>
  15. #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  16. icu_data_t icu_data[NR_IRQS];
  17. static void disable_mappi2_irq(unsigned int irq)
  18. {
  19. unsigned long port, data;
  20. if ((irq == 0) ||(irq >= NR_IRQS)) {
  21. printk("bad irq 0x%08x\n", irq);
  22. return;
  23. }
  24. port = irq2port(irq);
  25. data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  26. outl(data, port);
  27. }
  28. static void enable_mappi2_irq(unsigned int irq)
  29. {
  30. unsigned long port, data;
  31. if ((irq == 0) ||(irq >= NR_IRQS)) {
  32. printk("bad irq 0x%08x\n", irq);
  33. return;
  34. }
  35. port = irq2port(irq);
  36. data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  37. outl(data, port);
  38. }
  39. static void mask_mappi2(struct irq_data *data)
  40. {
  41. disable_mappi2_irq(data->irq);
  42. }
  43. static void unmask_mappi2(struct irq_data *data)
  44. {
  45. enable_mappi2_irq(data->irq);
  46. }
  47. static void shutdown_mappi2(struct irq_data *data)
  48. {
  49. unsigned long port;
  50. port = irq2port(data->irq);
  51. outl(M32R_ICUCR_ILEVEL7, port);
  52. }
  53. static struct irq_chip mappi2_irq_type =
  54. {
  55. .name = "MAPPI2-IRQ",
  56. .irq_shutdown = shutdown_mappi2,
  57. .irq_mask = mask_mappi2,
  58. .irq_unmask = unmask_mappi2,
  59. };
  60. void __init init_IRQ(void)
  61. {
  62. #if defined(CONFIG_SMC91X)
  63. /* INT0 : LAN controller (SMC91111) */
  64. irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
  65. handle_level_irq);
  66. icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
  67. disable_mappi2_irq(M32R_IRQ_INT0);
  68. #endif /* CONFIG_SMC91X */
  69. /* MFT2 : system timer */
  70. irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
  71. handle_level_irq);
  72. icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
  73. disable_mappi2_irq(M32R_IRQ_MFT2);
  74. #ifdef CONFIG_SERIAL_M32R_SIO
  75. /* SIO0_R : uart receive data */
  76. irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
  77. handle_level_irq);
  78. icu_data[M32R_IRQ_SIO0_R].icucr = 0;
  79. disable_mappi2_irq(M32R_IRQ_SIO0_R);
  80. /* SIO0_S : uart send data */
  81. irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
  82. handle_level_irq);
  83. icu_data[M32R_IRQ_SIO0_S].icucr = 0;
  84. disable_mappi2_irq(M32R_IRQ_SIO0_S);
  85. /* SIO1_R : uart receive data */
  86. irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
  87. handle_level_irq);
  88. icu_data[M32R_IRQ_SIO1_R].icucr = 0;
  89. disable_mappi2_irq(M32R_IRQ_SIO1_R);
  90. /* SIO1_S : uart send data */
  91. irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
  92. handle_level_irq);
  93. icu_data[M32R_IRQ_SIO1_S].icucr = 0;
  94. disable_mappi2_irq(M32R_IRQ_SIO1_S);
  95. #endif /* CONFIG_M32R_USE_DBG_CONSOLE */
  96. #if defined(CONFIG_USB)
  97. /* INT1 : USB Host controller interrupt */
  98. irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
  99. handle_level_irq);
  100. icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
  101. disable_mappi2_irq(M32R_IRQ_INT1);
  102. #endif /* CONFIG_USB */
  103. /* ICUCR40: CFC IREQ */
  104. irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
  105. handle_level_irq);
  106. icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
  107. disable_mappi2_irq(PLD_IRQ_CFIREQ);
  108. #if defined(CONFIG_M32R_CFC)
  109. /* ICUCR41: CFC Insert */
  110. irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
  111. handle_level_irq);
  112. icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
  113. disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
  114. /* ICUCR42: CFC Eject */
  115. irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
  116. handle_level_irq);
  117. icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
  118. disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
  119. #endif /* CONFIG_MAPPI2_CFC */
  120. }
  121. #define LAN_IOSTART 0x300
  122. #define LAN_IOEND 0x320
  123. static struct resource smc91x_resources[] = {
  124. [0] = {
  125. .start = (LAN_IOSTART),
  126. .end = (LAN_IOEND),
  127. .flags = IORESOURCE_MEM,
  128. },
  129. [1] = {
  130. .start = M32R_IRQ_INT0,
  131. .end = M32R_IRQ_INT0,
  132. .flags = IORESOURCE_IRQ,
  133. }
  134. };
  135. static struct platform_device smc91x_device = {
  136. .name = "smc91x",
  137. .id = 0,
  138. .num_resources = ARRAY_SIZE(smc91x_resources),
  139. .resource = smc91x_resources,
  140. };
  141. static int __init platform_init(void)
  142. {
  143. platform_device_register(&smc91x_device);
  144. return 0;
  145. }
  146. arch_initcall(platform_init);