copypage-v4wb.c 2.8 KB

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  1. /*
  2. * linux/arch/arm/mm/copypage-v4wb.c
  3. *
  4. * Copyright (C) 1995-1999 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/init.h>
  11. #include <linux/highmem.h>
  12. /*
  13. * ARMv4 optimised copy_user_highpage
  14. *
  15. * We flush the destination cache lines just before we write the data into the
  16. * corresponding address. Since the Dcache is read-allocate, this removes the
  17. * Dcache aliasing issue. The writes will be forwarded to the write buffer,
  18. * and merged as appropriate.
  19. *
  20. * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
  21. * instruction. If your processor does not supply this, you have to write your
  22. * own copy_user_highpage that does the right thing.
  23. */
  24. static void __naked
  25. v4wb_copy_user_page(void *kto, const void *kfrom)
  26. {
  27. asm("\
  28. stmfd sp!, {r4, lr} @ 2\n\
  29. mov r2, %2 @ 1\n\
  30. ldmia r1!, {r3, r4, ip, lr} @ 4\n\
  31. 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
  32. stmia r0!, {r3, r4, ip, lr} @ 4\n\
  33. ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\
  34. stmia r0!, {r3, r4, ip, lr} @ 4\n\
  35. ldmia r1!, {r3, r4, ip, lr} @ 4\n\
  36. mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
  37. stmia r0!, {r3, r4, ip, lr} @ 4\n\
  38. ldmia r1!, {r3, r4, ip, lr} @ 4\n\
  39. subs r2, r2, #1 @ 1\n\
  40. stmia r0!, {r3, r4, ip, lr} @ 4\n\
  41. ldmneia r1!, {r3, r4, ip, lr} @ 4\n\
  42. bne 1b @ 1\n\
  43. mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\
  44. ldmfd sp!, {r4, pc} @ 3"
  45. :
  46. : "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64));
  47. }
  48. void v4wb_copy_user_highpage(struct page *to, struct page *from,
  49. unsigned long vaddr, struct vm_area_struct *vma)
  50. {
  51. void *kto, *kfrom;
  52. kto = kmap_atomic(to);
  53. kfrom = kmap_atomic(from);
  54. flush_cache_page(vma, vaddr, page_to_pfn(from));
  55. v4wb_copy_user_page(kto, kfrom);
  56. kunmap_atomic(kfrom);
  57. kunmap_atomic(kto);
  58. }
  59. /*
  60. * ARMv4 optimised clear_user_page
  61. *
  62. * Same story as above.
  63. */
  64. void v4wb_clear_user_highpage(struct page *page, unsigned long vaddr)
  65. {
  66. void *ptr, *kaddr = kmap_atomic(page);
  67. asm volatile("\
  68. mov r1, %2 @ 1\n\
  69. mov r2, #0 @ 1\n\
  70. mov r3, #0 @ 1\n\
  71. mov ip, #0 @ 1\n\
  72. mov lr, #0 @ 1\n\
  73. 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
  74. stmia %0!, {r2, r3, ip, lr} @ 4\n\
  75. stmia %0!, {r2, r3, ip, lr} @ 4\n\
  76. mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
  77. stmia %0!, {r2, r3, ip, lr} @ 4\n\
  78. stmia %0!, {r2, r3, ip, lr} @ 4\n\
  79. subs r1, r1, #1 @ 1\n\
  80. bne 1b @ 1\n\
  81. mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB"
  82. : "=r" (ptr)
  83. : "0" (kaddr), "I" (PAGE_SIZE / 64)
  84. : "r1", "r2", "r3", "ip", "lr");
  85. kunmap_atomic(kaddr);
  86. }
  87. struct cpu_user_fns v4wb_user_fns __initdata = {
  88. .cpu_clear_user_highpage = v4wb_clear_user_highpage,
  89. .cpu_copy_user_highpage = v4wb_copy_user_highpage,
  90. };