dl2k.c 46 KB

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  1. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  2. /*
  3. Copyright (c) 2001, 2002 by D-Link Corporation
  4. Written by Edward Peng.<edward_peng@dlink.com.tw>
  5. Created 03-May-2001, base on Linux' sundance.c.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. */
  11. #define DRV_NAME "DL2000/TC902x-based linux driver"
  12. #define DRV_VERSION "v1.19"
  13. #define DRV_RELDATE "2007/08/12"
  14. #include "dl2k.h"
  15. #include <linux/dma-mapping.h>
  16. static char version[] __devinitdata =
  17. KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
  18. #define MAX_UNITS 8
  19. static int mtu[MAX_UNITS];
  20. static int vlan[MAX_UNITS];
  21. static int jumbo[MAX_UNITS];
  22. static char *media[MAX_UNITS];
  23. static int tx_flow=-1;
  24. static int rx_flow=-1;
  25. static int copy_thresh;
  26. static int rx_coalesce=10; /* Rx frame count each interrupt */
  27. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  28. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  29. MODULE_AUTHOR ("Edward Peng");
  30. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  31. MODULE_LICENSE("GPL");
  32. module_param_array(mtu, int, NULL, 0);
  33. module_param_array(media, charp, NULL, 0);
  34. module_param_array(vlan, int, NULL, 0);
  35. module_param_array(jumbo, int, NULL, 0);
  36. module_param(tx_flow, int, 0);
  37. module_param(rx_flow, int, 0);
  38. module_param(copy_thresh, int, 0);
  39. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  40. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  41. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  42. /* Enable the default interrupts */
  43. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  44. UpdateStats | LinkEvent)
  45. #define EnableInt() \
  46. writew(DEFAULT_INTR, ioaddr + IntEnable)
  47. static const int max_intrloop = 50;
  48. static const int multicast_filter_limit = 0x40;
  49. static int rio_open (struct net_device *dev);
  50. static void rio_timer (unsigned long data);
  51. static void rio_tx_timeout (struct net_device *dev);
  52. static void alloc_list (struct net_device *dev);
  53. static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
  54. static irqreturn_t rio_interrupt (int irq, void *dev_instance);
  55. static void rio_free_tx (struct net_device *dev, int irq);
  56. static void tx_error (struct net_device *dev, int tx_status);
  57. static int receive_packet (struct net_device *dev);
  58. static void rio_error (struct net_device *dev, int int_status);
  59. static int change_mtu (struct net_device *dev, int new_mtu);
  60. static void set_multicast (struct net_device *dev);
  61. static struct net_device_stats *get_stats (struct net_device *dev);
  62. static int clear_stats (struct net_device *dev);
  63. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  64. static int rio_close (struct net_device *dev);
  65. static int find_miiphy (struct net_device *dev);
  66. static int parse_eeprom (struct net_device *dev);
  67. static int read_eeprom (long ioaddr, int eep_addr);
  68. static int mii_wait_link (struct net_device *dev, int wait);
  69. static int mii_set_media (struct net_device *dev);
  70. static int mii_get_media (struct net_device *dev);
  71. static int mii_set_media_pcs (struct net_device *dev);
  72. static int mii_get_media_pcs (struct net_device *dev);
  73. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  74. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  75. u16 data);
  76. static const struct ethtool_ops ethtool_ops;
  77. static const struct net_device_ops netdev_ops = {
  78. .ndo_open = rio_open,
  79. .ndo_start_xmit = start_xmit,
  80. .ndo_stop = rio_close,
  81. .ndo_get_stats = get_stats,
  82. .ndo_validate_addr = eth_validate_addr,
  83. .ndo_set_mac_address = eth_mac_addr,
  84. .ndo_set_rx_mode = set_multicast,
  85. .ndo_do_ioctl = rio_ioctl,
  86. .ndo_tx_timeout = rio_tx_timeout,
  87. .ndo_change_mtu = change_mtu,
  88. };
  89. static int __devinit
  90. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  91. {
  92. struct net_device *dev;
  93. struct netdev_private *np;
  94. static int card_idx;
  95. int chip_idx = ent->driver_data;
  96. int err, irq;
  97. long ioaddr;
  98. static int version_printed;
  99. void *ring_space;
  100. dma_addr_t ring_dma;
  101. if (!version_printed++)
  102. printk ("%s", version);
  103. err = pci_enable_device (pdev);
  104. if (err)
  105. return err;
  106. irq = pdev->irq;
  107. err = pci_request_regions (pdev, "dl2k");
  108. if (err)
  109. goto err_out_disable;
  110. pci_set_master (pdev);
  111. dev = alloc_etherdev (sizeof (*np));
  112. if (!dev) {
  113. err = -ENOMEM;
  114. goto err_out_res;
  115. }
  116. SET_NETDEV_DEV(dev, &pdev->dev);
  117. #ifdef MEM_MAPPING
  118. ioaddr = pci_resource_start (pdev, 1);
  119. ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
  120. if (!ioaddr) {
  121. err = -ENOMEM;
  122. goto err_out_dev;
  123. }
  124. #else
  125. ioaddr = pci_resource_start (pdev, 0);
  126. #endif
  127. dev->base_addr = ioaddr;
  128. dev->irq = irq;
  129. np = netdev_priv(dev);
  130. np->chip_id = chip_idx;
  131. np->pdev = pdev;
  132. spin_lock_init (&np->tx_lock);
  133. spin_lock_init (&np->rx_lock);
  134. /* Parse manual configuration */
  135. np->an_enable = 1;
  136. np->tx_coalesce = 1;
  137. if (card_idx < MAX_UNITS) {
  138. if (media[card_idx] != NULL) {
  139. np->an_enable = 0;
  140. if (strcmp (media[card_idx], "auto") == 0 ||
  141. strcmp (media[card_idx], "autosense") == 0 ||
  142. strcmp (media[card_idx], "0") == 0 ) {
  143. np->an_enable = 2;
  144. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  145. strcmp (media[card_idx], "4") == 0) {
  146. np->speed = 100;
  147. np->full_duplex = 1;
  148. } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
  149. strcmp (media[card_idx], "3") == 0) {
  150. np->speed = 100;
  151. np->full_duplex = 0;
  152. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  153. strcmp (media[card_idx], "2") == 0) {
  154. np->speed = 10;
  155. np->full_duplex = 1;
  156. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  157. strcmp (media[card_idx], "1") == 0) {
  158. np->speed = 10;
  159. np->full_duplex = 0;
  160. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  161. strcmp (media[card_idx], "6") == 0) {
  162. np->speed=1000;
  163. np->full_duplex=1;
  164. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  165. strcmp (media[card_idx], "5") == 0) {
  166. np->speed = 1000;
  167. np->full_duplex = 0;
  168. } else {
  169. np->an_enable = 1;
  170. }
  171. }
  172. if (jumbo[card_idx] != 0) {
  173. np->jumbo = 1;
  174. dev->mtu = MAX_JUMBO;
  175. } else {
  176. np->jumbo = 0;
  177. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  178. dev->mtu = mtu[card_idx];
  179. }
  180. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  181. vlan[card_idx] : 0;
  182. if (rx_coalesce > 0 && rx_timeout > 0) {
  183. np->rx_coalesce = rx_coalesce;
  184. np->rx_timeout = rx_timeout;
  185. np->coalesce = 1;
  186. }
  187. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  188. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  189. if (tx_coalesce < 1)
  190. tx_coalesce = 1;
  191. else if (tx_coalesce > TX_RING_SIZE-1)
  192. tx_coalesce = TX_RING_SIZE - 1;
  193. }
  194. dev->netdev_ops = &netdev_ops;
  195. dev->watchdog_timeo = TX_TIMEOUT;
  196. SET_ETHTOOL_OPS(dev, &ethtool_ops);
  197. #if 0
  198. dev->features = NETIF_F_IP_CSUM;
  199. #endif
  200. pci_set_drvdata (pdev, dev);
  201. ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
  202. if (!ring_space)
  203. goto err_out_iounmap;
  204. np->tx_ring = ring_space;
  205. np->tx_ring_dma = ring_dma;
  206. ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
  207. if (!ring_space)
  208. goto err_out_unmap_tx;
  209. np->rx_ring = ring_space;
  210. np->rx_ring_dma = ring_dma;
  211. /* Parse eeprom data */
  212. parse_eeprom (dev);
  213. /* Find PHY address */
  214. err = find_miiphy (dev);
  215. if (err)
  216. goto err_out_unmap_rx;
  217. /* Fiber device? */
  218. np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
  219. np->link_status = 0;
  220. /* Set media and reset PHY */
  221. if (np->phy_media) {
  222. /* default Auto-Negotiation for fiber deivices */
  223. if (np->an_enable == 2) {
  224. np->an_enable = 1;
  225. }
  226. mii_set_media_pcs (dev);
  227. } else {
  228. /* Auto-Negotiation is mandatory for 1000BASE-T,
  229. IEEE 802.3ab Annex 28D page 14 */
  230. if (np->speed == 1000)
  231. np->an_enable = 1;
  232. mii_set_media (dev);
  233. }
  234. err = register_netdev (dev);
  235. if (err)
  236. goto err_out_unmap_rx;
  237. card_idx++;
  238. printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
  239. dev->name, np->name, dev->dev_addr, irq);
  240. if (tx_coalesce > 1)
  241. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  242. tx_coalesce);
  243. if (np->coalesce)
  244. printk(KERN_INFO
  245. "rx_coalesce:\t%d packets\n"
  246. "rx_timeout: \t%d ns\n",
  247. np->rx_coalesce, np->rx_timeout*640);
  248. if (np->vlan)
  249. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  250. return 0;
  251. err_out_unmap_rx:
  252. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
  253. err_out_unmap_tx:
  254. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
  255. err_out_iounmap:
  256. #ifdef MEM_MAPPING
  257. iounmap ((void *) ioaddr);
  258. err_out_dev:
  259. #endif
  260. free_netdev (dev);
  261. err_out_res:
  262. pci_release_regions (pdev);
  263. err_out_disable:
  264. pci_disable_device (pdev);
  265. return err;
  266. }
  267. static int
  268. find_miiphy (struct net_device *dev)
  269. {
  270. int i, phy_found = 0;
  271. struct netdev_private *np;
  272. long ioaddr;
  273. np = netdev_priv(dev);
  274. ioaddr = dev->base_addr;
  275. np->phy_addr = 1;
  276. for (i = 31; i >= 0; i--) {
  277. int mii_status = mii_read (dev, i, 1);
  278. if (mii_status != 0xffff && mii_status != 0x0000) {
  279. np->phy_addr = i;
  280. phy_found++;
  281. }
  282. }
  283. if (!phy_found) {
  284. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  285. return -ENODEV;
  286. }
  287. return 0;
  288. }
  289. static int
  290. parse_eeprom (struct net_device *dev)
  291. {
  292. int i, j;
  293. long ioaddr = dev->base_addr;
  294. u8 sromdata[256];
  295. u8 *psib;
  296. u32 crc;
  297. PSROM_t psrom = (PSROM_t) sromdata;
  298. struct netdev_private *np = netdev_priv(dev);
  299. int cid, next;
  300. #ifdef MEM_MAPPING
  301. ioaddr = pci_resource_start (np->pdev, 0);
  302. #endif
  303. /* Read eeprom */
  304. for (i = 0; i < 128; i++) {
  305. ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom (ioaddr, i));
  306. }
  307. #ifdef MEM_MAPPING
  308. ioaddr = dev->base_addr;
  309. #endif
  310. if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
  311. /* Check CRC */
  312. crc = ~ether_crc_le (256 - 4, sromdata);
  313. if (psrom->crc != cpu_to_le32(crc)) {
  314. printk (KERN_ERR "%s: EEPROM data CRC error.\n",
  315. dev->name);
  316. return -1;
  317. }
  318. }
  319. /* Set MAC address */
  320. for (i = 0; i < 6; i++)
  321. dev->dev_addr[i] = psrom->mac_addr[i];
  322. if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
  323. return 0;
  324. }
  325. /* Parse Software Information Block */
  326. i = 0x30;
  327. psib = (u8 *) sromdata;
  328. do {
  329. cid = psib[i++];
  330. next = psib[i++];
  331. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  332. printk (KERN_ERR "Cell data error\n");
  333. return -1;
  334. }
  335. switch (cid) {
  336. case 0: /* Format version */
  337. break;
  338. case 1: /* End of cell */
  339. return 0;
  340. case 2: /* Duplex Polarity */
  341. np->duplex_polarity = psib[i];
  342. writeb (readb (ioaddr + PhyCtrl) | psib[i],
  343. ioaddr + PhyCtrl);
  344. break;
  345. case 3: /* Wake Polarity */
  346. np->wake_polarity = psib[i];
  347. break;
  348. case 9: /* Adapter description */
  349. j = (next - i > 255) ? 255 : next - i;
  350. memcpy (np->name, &(psib[i]), j);
  351. break;
  352. case 4:
  353. case 5:
  354. case 6:
  355. case 7:
  356. case 8: /* Reversed */
  357. break;
  358. default: /* Unknown cell */
  359. return -1;
  360. }
  361. i = next;
  362. } while (1);
  363. return 0;
  364. }
  365. static int
  366. rio_open (struct net_device *dev)
  367. {
  368. struct netdev_private *np = netdev_priv(dev);
  369. long ioaddr = dev->base_addr;
  370. int i;
  371. u16 macctrl;
  372. i = request_irq (dev->irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
  373. if (i)
  374. return i;
  375. /* Reset all logic functions */
  376. writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
  377. ioaddr + ASICCtrl + 2);
  378. mdelay(10);
  379. /* DebugCtrl bit 4, 5, 9 must set */
  380. writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
  381. /* Jumbo frame */
  382. if (np->jumbo != 0)
  383. writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
  384. alloc_list (dev);
  385. /* Get station address */
  386. for (i = 0; i < 6; i++)
  387. writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
  388. set_multicast (dev);
  389. if (np->coalesce) {
  390. writel (np->rx_coalesce | np->rx_timeout << 16,
  391. ioaddr + RxDMAIntCtrl);
  392. }
  393. /* Set RIO to poll every N*320nsec. */
  394. writeb (0x20, ioaddr + RxDMAPollPeriod);
  395. writeb (0xff, ioaddr + TxDMAPollPeriod);
  396. writeb (0x30, ioaddr + RxDMABurstThresh);
  397. writeb (0x30, ioaddr + RxDMAUrgentThresh);
  398. writel (0x0007ffff, ioaddr + RmonStatMask);
  399. /* clear statistics */
  400. clear_stats (dev);
  401. /* VLAN supported */
  402. if (np->vlan) {
  403. /* priority field in RxDMAIntCtrl */
  404. writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
  405. ioaddr + RxDMAIntCtrl);
  406. /* VLANId */
  407. writew (np->vlan, ioaddr + VLANId);
  408. /* Length/Type should be 0x8100 */
  409. writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
  410. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  411. VLAN information tagged by TFC' VID, CFI fields. */
  412. writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
  413. ioaddr + MACCtrl);
  414. }
  415. init_timer (&np->timer);
  416. np->timer.expires = jiffies + 1*HZ;
  417. np->timer.data = (unsigned long) dev;
  418. np->timer.function = rio_timer;
  419. add_timer (&np->timer);
  420. /* Start Tx/Rx */
  421. writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
  422. ioaddr + MACCtrl);
  423. macctrl = 0;
  424. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  425. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  426. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  427. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  428. writew(macctrl, ioaddr + MACCtrl);
  429. netif_start_queue (dev);
  430. /* Enable default interrupts */
  431. EnableInt ();
  432. return 0;
  433. }
  434. static void
  435. rio_timer (unsigned long data)
  436. {
  437. struct net_device *dev = (struct net_device *)data;
  438. struct netdev_private *np = netdev_priv(dev);
  439. unsigned int entry;
  440. int next_tick = 1*HZ;
  441. unsigned long flags;
  442. spin_lock_irqsave(&np->rx_lock, flags);
  443. /* Recover rx ring exhausted error */
  444. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  445. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  446. /* Re-allocate skbuffs to fill the descriptor ring */
  447. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  448. struct sk_buff *skb;
  449. entry = np->old_rx % RX_RING_SIZE;
  450. /* Dropped packets don't need to re-allocate */
  451. if (np->rx_skbuff[entry] == NULL) {
  452. skb = netdev_alloc_skb_ip_align(dev,
  453. np->rx_buf_sz);
  454. if (skb == NULL) {
  455. np->rx_ring[entry].fraginfo = 0;
  456. printk (KERN_INFO
  457. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  458. dev->name, entry);
  459. break;
  460. }
  461. np->rx_skbuff[entry] = skb;
  462. np->rx_ring[entry].fraginfo =
  463. cpu_to_le64 (pci_map_single
  464. (np->pdev, skb->data, np->rx_buf_sz,
  465. PCI_DMA_FROMDEVICE));
  466. }
  467. np->rx_ring[entry].fraginfo |=
  468. cpu_to_le64((u64)np->rx_buf_sz << 48);
  469. np->rx_ring[entry].status = 0;
  470. } /* end for */
  471. } /* end if */
  472. spin_unlock_irqrestore (&np->rx_lock, flags);
  473. np->timer.expires = jiffies + next_tick;
  474. add_timer(&np->timer);
  475. }
  476. static void
  477. rio_tx_timeout (struct net_device *dev)
  478. {
  479. long ioaddr = dev->base_addr;
  480. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  481. dev->name, readl (ioaddr + TxStatus));
  482. rio_free_tx(dev, 0);
  483. dev->if_port = 0;
  484. dev->trans_start = jiffies; /* prevent tx timeout */
  485. }
  486. /* allocate and initialize Tx and Rx descriptors */
  487. static void
  488. alloc_list (struct net_device *dev)
  489. {
  490. struct netdev_private *np = netdev_priv(dev);
  491. int i;
  492. np->cur_rx = np->cur_tx = 0;
  493. np->old_rx = np->old_tx = 0;
  494. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  495. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  496. for (i = 0; i < TX_RING_SIZE; i++) {
  497. np->tx_skbuff[i] = NULL;
  498. np->tx_ring[i].status = cpu_to_le64 (TFDDone);
  499. np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
  500. ((i+1)%TX_RING_SIZE) *
  501. sizeof (struct netdev_desc));
  502. }
  503. /* Initialize Rx descriptors */
  504. for (i = 0; i < RX_RING_SIZE; i++) {
  505. np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
  506. ((i + 1) % RX_RING_SIZE) *
  507. sizeof (struct netdev_desc));
  508. np->rx_ring[i].status = 0;
  509. np->rx_ring[i].fraginfo = 0;
  510. np->rx_skbuff[i] = NULL;
  511. }
  512. /* Allocate the rx buffers */
  513. for (i = 0; i < RX_RING_SIZE; i++) {
  514. /* Allocated fixed size of skbuff */
  515. struct sk_buff *skb;
  516. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  517. np->rx_skbuff[i] = skb;
  518. if (skb == NULL) {
  519. printk (KERN_ERR
  520. "%s: alloc_list: allocate Rx buffer error! ",
  521. dev->name);
  522. break;
  523. }
  524. /* Rubicon now supports 40 bits of addressing space. */
  525. np->rx_ring[i].fraginfo =
  526. cpu_to_le64 ( pci_map_single (
  527. np->pdev, skb->data, np->rx_buf_sz,
  528. PCI_DMA_FROMDEVICE));
  529. np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
  530. }
  531. /* Set RFDListPtr */
  532. writel (np->rx_ring_dma, dev->base_addr + RFDListPtr0);
  533. writel (0, dev->base_addr + RFDListPtr1);
  534. }
  535. static netdev_tx_t
  536. start_xmit (struct sk_buff *skb, struct net_device *dev)
  537. {
  538. struct netdev_private *np = netdev_priv(dev);
  539. struct netdev_desc *txdesc;
  540. unsigned entry;
  541. u32 ioaddr;
  542. u64 tfc_vlan_tag = 0;
  543. if (np->link_status == 0) { /* Link Down */
  544. dev_kfree_skb(skb);
  545. return NETDEV_TX_OK;
  546. }
  547. ioaddr = dev->base_addr;
  548. entry = np->cur_tx % TX_RING_SIZE;
  549. np->tx_skbuff[entry] = skb;
  550. txdesc = &np->tx_ring[entry];
  551. #if 0
  552. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  553. txdesc->status |=
  554. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  555. IPChecksumEnable);
  556. }
  557. #endif
  558. if (np->vlan) {
  559. tfc_vlan_tag = VLANTagInsert |
  560. ((u64)np->vlan << 32) |
  561. ((u64)skb->priority << 45);
  562. }
  563. txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
  564. skb->len,
  565. PCI_DMA_TODEVICE));
  566. txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
  567. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  568. * Work around: Always use 1 descriptor in 10Mbps mode */
  569. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  570. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  571. WordAlignDisable |
  572. TxDMAIndicate |
  573. (1 << FragCountShift));
  574. else
  575. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  576. WordAlignDisable |
  577. (1 << FragCountShift));
  578. /* TxDMAPollNow */
  579. writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
  580. /* Schedule ISR */
  581. writel(10000, ioaddr + CountDown);
  582. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  583. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  584. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  585. /* do nothing */
  586. } else if (!netif_queue_stopped(dev)) {
  587. netif_stop_queue (dev);
  588. }
  589. /* The first TFDListPtr */
  590. if (readl (dev->base_addr + TFDListPtr0) == 0) {
  591. writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
  592. dev->base_addr + TFDListPtr0);
  593. writel (0, dev->base_addr + TFDListPtr1);
  594. }
  595. return NETDEV_TX_OK;
  596. }
  597. static irqreturn_t
  598. rio_interrupt (int irq, void *dev_instance)
  599. {
  600. struct net_device *dev = dev_instance;
  601. struct netdev_private *np;
  602. unsigned int_status;
  603. long ioaddr;
  604. int cnt = max_intrloop;
  605. int handled = 0;
  606. ioaddr = dev->base_addr;
  607. np = netdev_priv(dev);
  608. while (1) {
  609. int_status = readw (ioaddr + IntStatus);
  610. writew (int_status, ioaddr + IntStatus);
  611. int_status &= DEFAULT_INTR;
  612. if (int_status == 0 || --cnt < 0)
  613. break;
  614. handled = 1;
  615. /* Processing received packets */
  616. if (int_status & RxDMAComplete)
  617. receive_packet (dev);
  618. /* TxDMAComplete interrupt */
  619. if ((int_status & (TxDMAComplete|IntRequested))) {
  620. int tx_status;
  621. tx_status = readl (ioaddr + TxStatus);
  622. if (tx_status & 0x01)
  623. tx_error (dev, tx_status);
  624. /* Free used tx skbuffs */
  625. rio_free_tx (dev, 1);
  626. }
  627. /* Handle uncommon events */
  628. if (int_status &
  629. (HostError | LinkEvent | UpdateStats))
  630. rio_error (dev, int_status);
  631. }
  632. if (np->cur_tx != np->old_tx)
  633. writel (100, ioaddr + CountDown);
  634. return IRQ_RETVAL(handled);
  635. }
  636. static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
  637. {
  638. return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
  639. }
  640. static void
  641. rio_free_tx (struct net_device *dev, int irq)
  642. {
  643. struct netdev_private *np = netdev_priv(dev);
  644. int entry = np->old_tx % TX_RING_SIZE;
  645. int tx_use = 0;
  646. unsigned long flag = 0;
  647. if (irq)
  648. spin_lock(&np->tx_lock);
  649. else
  650. spin_lock_irqsave(&np->tx_lock, flag);
  651. /* Free used tx skbuffs */
  652. while (entry != np->cur_tx) {
  653. struct sk_buff *skb;
  654. if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
  655. break;
  656. skb = np->tx_skbuff[entry];
  657. pci_unmap_single (np->pdev,
  658. desc_to_dma(&np->tx_ring[entry]),
  659. skb->len, PCI_DMA_TODEVICE);
  660. if (irq)
  661. dev_kfree_skb_irq (skb);
  662. else
  663. dev_kfree_skb (skb);
  664. np->tx_skbuff[entry] = NULL;
  665. entry = (entry + 1) % TX_RING_SIZE;
  666. tx_use++;
  667. }
  668. if (irq)
  669. spin_unlock(&np->tx_lock);
  670. else
  671. spin_unlock_irqrestore(&np->tx_lock, flag);
  672. np->old_tx = entry;
  673. /* If the ring is no longer full, clear tx_full and
  674. call netif_wake_queue() */
  675. if (netif_queue_stopped(dev) &&
  676. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  677. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  678. netif_wake_queue (dev);
  679. }
  680. }
  681. static void
  682. tx_error (struct net_device *dev, int tx_status)
  683. {
  684. struct netdev_private *np;
  685. long ioaddr = dev->base_addr;
  686. int frame_id;
  687. int i;
  688. np = netdev_priv(dev);
  689. frame_id = (tx_status & 0xffff0000);
  690. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  691. dev->name, tx_status, frame_id);
  692. np->stats.tx_errors++;
  693. /* Ttransmit Underrun */
  694. if (tx_status & 0x10) {
  695. np->stats.tx_fifo_errors++;
  696. writew (readw (ioaddr + TxStartThresh) + 0x10,
  697. ioaddr + TxStartThresh);
  698. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  699. writew (TxReset | DMAReset | FIFOReset | NetworkReset,
  700. ioaddr + ASICCtrl + 2);
  701. /* Wait for ResetBusy bit clear */
  702. for (i = 50; i > 0; i--) {
  703. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  704. break;
  705. mdelay (1);
  706. }
  707. rio_free_tx (dev, 1);
  708. /* Reset TFDListPtr */
  709. writel (np->tx_ring_dma +
  710. np->old_tx * sizeof (struct netdev_desc),
  711. dev->base_addr + TFDListPtr0);
  712. writel (0, dev->base_addr + TFDListPtr1);
  713. /* Let TxStartThresh stay default value */
  714. }
  715. /* Late Collision */
  716. if (tx_status & 0x04) {
  717. np->stats.tx_fifo_errors++;
  718. /* TxReset and clear FIFO */
  719. writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
  720. /* Wait reset done */
  721. for (i = 50; i > 0; i--) {
  722. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  723. break;
  724. mdelay (1);
  725. }
  726. /* Let TxStartThresh stay default value */
  727. }
  728. /* Maximum Collisions */
  729. #ifdef ETHER_STATS
  730. if (tx_status & 0x08)
  731. np->stats.collisions16++;
  732. #else
  733. if (tx_status & 0x08)
  734. np->stats.collisions++;
  735. #endif
  736. /* Restart the Tx */
  737. writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
  738. }
  739. static int
  740. receive_packet (struct net_device *dev)
  741. {
  742. struct netdev_private *np = netdev_priv(dev);
  743. int entry = np->cur_rx % RX_RING_SIZE;
  744. int cnt = 30;
  745. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  746. while (1) {
  747. struct netdev_desc *desc = &np->rx_ring[entry];
  748. int pkt_len;
  749. u64 frame_status;
  750. if (!(desc->status & cpu_to_le64(RFDDone)) ||
  751. !(desc->status & cpu_to_le64(FrameStart)) ||
  752. !(desc->status & cpu_to_le64(FrameEnd)))
  753. break;
  754. /* Chip omits the CRC. */
  755. frame_status = le64_to_cpu(desc->status);
  756. pkt_len = frame_status & 0xffff;
  757. if (--cnt < 0)
  758. break;
  759. /* Update rx error statistics, drop packet. */
  760. if (frame_status & RFS_Errors) {
  761. np->stats.rx_errors++;
  762. if (frame_status & (RxRuntFrame | RxLengthError))
  763. np->stats.rx_length_errors++;
  764. if (frame_status & RxFCSError)
  765. np->stats.rx_crc_errors++;
  766. if (frame_status & RxAlignmentError && np->speed != 1000)
  767. np->stats.rx_frame_errors++;
  768. if (frame_status & RxFIFOOverrun)
  769. np->stats.rx_fifo_errors++;
  770. } else {
  771. struct sk_buff *skb;
  772. /* Small skbuffs for short packets */
  773. if (pkt_len > copy_thresh) {
  774. pci_unmap_single (np->pdev,
  775. desc_to_dma(desc),
  776. np->rx_buf_sz,
  777. PCI_DMA_FROMDEVICE);
  778. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  779. np->rx_skbuff[entry] = NULL;
  780. } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
  781. pci_dma_sync_single_for_cpu(np->pdev,
  782. desc_to_dma(desc),
  783. np->rx_buf_sz,
  784. PCI_DMA_FROMDEVICE);
  785. skb_copy_to_linear_data (skb,
  786. np->rx_skbuff[entry]->data,
  787. pkt_len);
  788. skb_put (skb, pkt_len);
  789. pci_dma_sync_single_for_device(np->pdev,
  790. desc_to_dma(desc),
  791. np->rx_buf_sz,
  792. PCI_DMA_FROMDEVICE);
  793. }
  794. skb->protocol = eth_type_trans (skb, dev);
  795. #if 0
  796. /* Checksum done by hw, but csum value unavailable. */
  797. if (np->pdev->pci_rev_id >= 0x0c &&
  798. !(frame_status & (TCPError | UDPError | IPError))) {
  799. skb->ip_summed = CHECKSUM_UNNECESSARY;
  800. }
  801. #endif
  802. netif_rx (skb);
  803. }
  804. entry = (entry + 1) % RX_RING_SIZE;
  805. }
  806. spin_lock(&np->rx_lock);
  807. np->cur_rx = entry;
  808. /* Re-allocate skbuffs to fill the descriptor ring */
  809. entry = np->old_rx;
  810. while (entry != np->cur_rx) {
  811. struct sk_buff *skb;
  812. /* Dropped packets don't need to re-allocate */
  813. if (np->rx_skbuff[entry] == NULL) {
  814. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  815. if (skb == NULL) {
  816. np->rx_ring[entry].fraginfo = 0;
  817. printk (KERN_INFO
  818. "%s: receive_packet: "
  819. "Unable to re-allocate Rx skbuff.#%d\n",
  820. dev->name, entry);
  821. break;
  822. }
  823. np->rx_skbuff[entry] = skb;
  824. np->rx_ring[entry].fraginfo =
  825. cpu_to_le64 (pci_map_single
  826. (np->pdev, skb->data, np->rx_buf_sz,
  827. PCI_DMA_FROMDEVICE));
  828. }
  829. np->rx_ring[entry].fraginfo |=
  830. cpu_to_le64((u64)np->rx_buf_sz << 48);
  831. np->rx_ring[entry].status = 0;
  832. entry = (entry + 1) % RX_RING_SIZE;
  833. }
  834. np->old_rx = entry;
  835. spin_unlock(&np->rx_lock);
  836. return 0;
  837. }
  838. static void
  839. rio_error (struct net_device *dev, int int_status)
  840. {
  841. long ioaddr = dev->base_addr;
  842. struct netdev_private *np = netdev_priv(dev);
  843. u16 macctrl;
  844. /* Link change event */
  845. if (int_status & LinkEvent) {
  846. if (mii_wait_link (dev, 10) == 0) {
  847. printk (KERN_INFO "%s: Link up\n", dev->name);
  848. if (np->phy_media)
  849. mii_get_media_pcs (dev);
  850. else
  851. mii_get_media (dev);
  852. if (np->speed == 1000)
  853. np->tx_coalesce = tx_coalesce;
  854. else
  855. np->tx_coalesce = 1;
  856. macctrl = 0;
  857. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  858. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  859. macctrl |= (np->tx_flow) ?
  860. TxFlowControlEnable : 0;
  861. macctrl |= (np->rx_flow) ?
  862. RxFlowControlEnable : 0;
  863. writew(macctrl, ioaddr + MACCtrl);
  864. np->link_status = 1;
  865. netif_carrier_on(dev);
  866. } else {
  867. printk (KERN_INFO "%s: Link off\n", dev->name);
  868. np->link_status = 0;
  869. netif_carrier_off(dev);
  870. }
  871. }
  872. /* UpdateStats statistics registers */
  873. if (int_status & UpdateStats) {
  874. get_stats (dev);
  875. }
  876. /* PCI Error, a catastronphic error related to the bus interface
  877. occurs, set GlobalReset and HostReset to reset. */
  878. if (int_status & HostError) {
  879. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  880. dev->name, int_status);
  881. writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
  882. mdelay (500);
  883. }
  884. }
  885. static struct net_device_stats *
  886. get_stats (struct net_device *dev)
  887. {
  888. long ioaddr = dev->base_addr;
  889. struct netdev_private *np = netdev_priv(dev);
  890. #ifdef MEM_MAPPING
  891. int i;
  892. #endif
  893. unsigned int stat_reg;
  894. /* All statistics registers need to be acknowledged,
  895. else statistic overflow could cause problems */
  896. np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
  897. np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
  898. np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
  899. np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
  900. np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
  901. np->stats.collisions += readl (ioaddr + SingleColFrames)
  902. + readl (ioaddr + MultiColFrames);
  903. /* detailed tx errors */
  904. stat_reg = readw (ioaddr + FramesAbortXSColls);
  905. np->stats.tx_aborted_errors += stat_reg;
  906. np->stats.tx_errors += stat_reg;
  907. stat_reg = readw (ioaddr + CarrierSenseErrors);
  908. np->stats.tx_carrier_errors += stat_reg;
  909. np->stats.tx_errors += stat_reg;
  910. /* Clear all other statistic register. */
  911. readl (ioaddr + McstOctetXmtOk);
  912. readw (ioaddr + BcstFramesXmtdOk);
  913. readl (ioaddr + McstFramesXmtdOk);
  914. readw (ioaddr + BcstFramesRcvdOk);
  915. readw (ioaddr + MacControlFramesRcvd);
  916. readw (ioaddr + FrameTooLongErrors);
  917. readw (ioaddr + InRangeLengthErrors);
  918. readw (ioaddr + FramesCheckSeqErrors);
  919. readw (ioaddr + FramesLostRxErrors);
  920. readl (ioaddr + McstOctetXmtOk);
  921. readl (ioaddr + BcstOctetXmtOk);
  922. readl (ioaddr + McstFramesXmtdOk);
  923. readl (ioaddr + FramesWDeferredXmt);
  924. readl (ioaddr + LateCollisions);
  925. readw (ioaddr + BcstFramesXmtdOk);
  926. readw (ioaddr + MacControlFramesXmtd);
  927. readw (ioaddr + FramesWEXDeferal);
  928. #ifdef MEM_MAPPING
  929. for (i = 0x100; i <= 0x150; i += 4)
  930. readl (ioaddr + i);
  931. #endif
  932. readw (ioaddr + TxJumboFrames);
  933. readw (ioaddr + RxJumboFrames);
  934. readw (ioaddr + TCPCheckSumErrors);
  935. readw (ioaddr + UDPCheckSumErrors);
  936. readw (ioaddr + IPCheckSumErrors);
  937. return &np->stats;
  938. }
  939. static int
  940. clear_stats (struct net_device *dev)
  941. {
  942. long ioaddr = dev->base_addr;
  943. #ifdef MEM_MAPPING
  944. int i;
  945. #endif
  946. /* All statistics registers need to be acknowledged,
  947. else statistic overflow could cause problems */
  948. readl (ioaddr + FramesRcvOk);
  949. readl (ioaddr + FramesXmtOk);
  950. readl (ioaddr + OctetRcvOk);
  951. readl (ioaddr + OctetXmtOk);
  952. readl (ioaddr + McstFramesRcvdOk);
  953. readl (ioaddr + SingleColFrames);
  954. readl (ioaddr + MultiColFrames);
  955. readl (ioaddr + LateCollisions);
  956. /* detailed rx errors */
  957. readw (ioaddr + FrameTooLongErrors);
  958. readw (ioaddr + InRangeLengthErrors);
  959. readw (ioaddr + FramesCheckSeqErrors);
  960. readw (ioaddr + FramesLostRxErrors);
  961. /* detailed tx errors */
  962. readw (ioaddr + FramesAbortXSColls);
  963. readw (ioaddr + CarrierSenseErrors);
  964. /* Clear all other statistic register. */
  965. readl (ioaddr + McstOctetXmtOk);
  966. readw (ioaddr + BcstFramesXmtdOk);
  967. readl (ioaddr + McstFramesXmtdOk);
  968. readw (ioaddr + BcstFramesRcvdOk);
  969. readw (ioaddr + MacControlFramesRcvd);
  970. readl (ioaddr + McstOctetXmtOk);
  971. readl (ioaddr + BcstOctetXmtOk);
  972. readl (ioaddr + McstFramesXmtdOk);
  973. readl (ioaddr + FramesWDeferredXmt);
  974. readw (ioaddr + BcstFramesXmtdOk);
  975. readw (ioaddr + MacControlFramesXmtd);
  976. readw (ioaddr + FramesWEXDeferal);
  977. #ifdef MEM_MAPPING
  978. for (i = 0x100; i <= 0x150; i += 4)
  979. readl (ioaddr + i);
  980. #endif
  981. readw (ioaddr + TxJumboFrames);
  982. readw (ioaddr + RxJumboFrames);
  983. readw (ioaddr + TCPCheckSumErrors);
  984. readw (ioaddr + UDPCheckSumErrors);
  985. readw (ioaddr + IPCheckSumErrors);
  986. return 0;
  987. }
  988. static int
  989. change_mtu (struct net_device *dev, int new_mtu)
  990. {
  991. struct netdev_private *np = netdev_priv(dev);
  992. int max = (np->jumbo) ? MAX_JUMBO : 1536;
  993. if ((new_mtu < 68) || (new_mtu > max)) {
  994. return -EINVAL;
  995. }
  996. dev->mtu = new_mtu;
  997. return 0;
  998. }
  999. static void
  1000. set_multicast (struct net_device *dev)
  1001. {
  1002. long ioaddr = dev->base_addr;
  1003. u32 hash_table[2];
  1004. u16 rx_mode = 0;
  1005. struct netdev_private *np = netdev_priv(dev);
  1006. hash_table[0] = hash_table[1] = 0;
  1007. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  1008. hash_table[1] |= 0x02000000;
  1009. if (dev->flags & IFF_PROMISC) {
  1010. /* Receive all frames promiscuously. */
  1011. rx_mode = ReceiveAllFrames;
  1012. } else if ((dev->flags & IFF_ALLMULTI) ||
  1013. (netdev_mc_count(dev) > multicast_filter_limit)) {
  1014. /* Receive broadcast and multicast frames */
  1015. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1016. } else if (!netdev_mc_empty(dev)) {
  1017. struct netdev_hw_addr *ha;
  1018. /* Receive broadcast frames and multicast frames filtering
  1019. by Hashtable */
  1020. rx_mode =
  1021. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1022. netdev_for_each_mc_addr(ha, dev) {
  1023. int bit, index = 0;
  1024. int crc = ether_crc_le(ETH_ALEN, ha->addr);
  1025. /* The inverted high significant 6 bits of CRC are
  1026. used as an index to hashtable */
  1027. for (bit = 0; bit < 6; bit++)
  1028. if (crc & (1 << (31 - bit)))
  1029. index |= (1 << bit);
  1030. hash_table[index / 32] |= (1 << (index % 32));
  1031. }
  1032. } else {
  1033. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1034. }
  1035. if (np->vlan) {
  1036. /* ReceiveVLANMatch field in ReceiveMode */
  1037. rx_mode |= ReceiveVLANMatch;
  1038. }
  1039. writel (hash_table[0], ioaddr + HashTable0);
  1040. writel (hash_table[1], ioaddr + HashTable1);
  1041. writew (rx_mode, ioaddr + ReceiveMode);
  1042. }
  1043. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1044. {
  1045. struct netdev_private *np = netdev_priv(dev);
  1046. strcpy(info->driver, "dl2k");
  1047. strcpy(info->version, DRV_VERSION);
  1048. strcpy(info->bus_info, pci_name(np->pdev));
  1049. }
  1050. static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1051. {
  1052. struct netdev_private *np = netdev_priv(dev);
  1053. if (np->phy_media) {
  1054. /* fiber device */
  1055. cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1056. cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1057. cmd->port = PORT_FIBRE;
  1058. cmd->transceiver = XCVR_INTERNAL;
  1059. } else {
  1060. /* copper device */
  1061. cmd->supported = SUPPORTED_10baseT_Half |
  1062. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1063. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1064. SUPPORTED_Autoneg | SUPPORTED_MII;
  1065. cmd->advertising = ADVERTISED_10baseT_Half |
  1066. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1067. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
  1068. ADVERTISED_Autoneg | ADVERTISED_MII;
  1069. cmd->port = PORT_MII;
  1070. cmd->transceiver = XCVR_INTERNAL;
  1071. }
  1072. if ( np->link_status ) {
  1073. ethtool_cmd_speed_set(cmd, np->speed);
  1074. cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1075. } else {
  1076. ethtool_cmd_speed_set(cmd, -1);
  1077. cmd->duplex = -1;
  1078. }
  1079. if ( np->an_enable)
  1080. cmd->autoneg = AUTONEG_ENABLE;
  1081. else
  1082. cmd->autoneg = AUTONEG_DISABLE;
  1083. cmd->phy_address = np->phy_addr;
  1084. return 0;
  1085. }
  1086. static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1087. {
  1088. struct netdev_private *np = netdev_priv(dev);
  1089. netif_carrier_off(dev);
  1090. if (cmd->autoneg == AUTONEG_ENABLE) {
  1091. if (np->an_enable)
  1092. return 0;
  1093. else {
  1094. np->an_enable = 1;
  1095. mii_set_media(dev);
  1096. return 0;
  1097. }
  1098. } else {
  1099. np->an_enable = 0;
  1100. if (np->speed == 1000) {
  1101. ethtool_cmd_speed_set(cmd, SPEED_100);
  1102. cmd->duplex = DUPLEX_FULL;
  1103. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1104. }
  1105. switch (ethtool_cmd_speed(cmd)) {
  1106. case SPEED_10:
  1107. np->speed = 10;
  1108. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1109. break;
  1110. case SPEED_100:
  1111. np->speed = 100;
  1112. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1113. break;
  1114. case SPEED_1000: /* not supported */
  1115. default:
  1116. return -EINVAL;
  1117. }
  1118. mii_set_media(dev);
  1119. }
  1120. return 0;
  1121. }
  1122. static u32 rio_get_link(struct net_device *dev)
  1123. {
  1124. struct netdev_private *np = netdev_priv(dev);
  1125. return np->link_status;
  1126. }
  1127. static const struct ethtool_ops ethtool_ops = {
  1128. .get_drvinfo = rio_get_drvinfo,
  1129. .get_settings = rio_get_settings,
  1130. .set_settings = rio_set_settings,
  1131. .get_link = rio_get_link,
  1132. };
  1133. static int
  1134. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1135. {
  1136. int phy_addr;
  1137. struct netdev_private *np = netdev_priv(dev);
  1138. struct mii_ioctl_data *miidata = if_mii(rq);
  1139. phy_addr = np->phy_addr;
  1140. switch (cmd) {
  1141. case SIOCGMIIPHY:
  1142. miidata->phy_id = phy_addr;
  1143. break;
  1144. case SIOCGMIIREG:
  1145. miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
  1146. break;
  1147. case SIOCSMIIREG:
  1148. if (!capable(CAP_NET_ADMIN))
  1149. return -EPERM;
  1150. mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
  1151. break;
  1152. default:
  1153. return -EOPNOTSUPP;
  1154. }
  1155. return 0;
  1156. }
  1157. #define EEP_READ 0x0200
  1158. #define EEP_BUSY 0x8000
  1159. /* Read the EEPROM word */
  1160. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1161. static int
  1162. read_eeprom (long ioaddr, int eep_addr)
  1163. {
  1164. int i = 1000;
  1165. outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
  1166. while (i-- > 0) {
  1167. if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
  1168. return inw (ioaddr + EepromData);
  1169. }
  1170. }
  1171. return 0;
  1172. }
  1173. enum phy_ctrl_bits {
  1174. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1175. MII_DUPLEX = 0x08,
  1176. };
  1177. #define mii_delay() readb(ioaddr)
  1178. static void
  1179. mii_sendbit (struct net_device *dev, u32 data)
  1180. {
  1181. long ioaddr = dev->base_addr + PhyCtrl;
  1182. data = (data) ? MII_DATA1 : 0;
  1183. data |= MII_WRITE;
  1184. data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
  1185. writeb (data, ioaddr);
  1186. mii_delay ();
  1187. writeb (data | MII_CLK, ioaddr);
  1188. mii_delay ();
  1189. }
  1190. static int
  1191. mii_getbit (struct net_device *dev)
  1192. {
  1193. long ioaddr = dev->base_addr + PhyCtrl;
  1194. u8 data;
  1195. data = (readb (ioaddr) & 0xf8) | MII_READ;
  1196. writeb (data, ioaddr);
  1197. mii_delay ();
  1198. writeb (data | MII_CLK, ioaddr);
  1199. mii_delay ();
  1200. return ((readb (ioaddr) >> 1) & 1);
  1201. }
  1202. static void
  1203. mii_send_bits (struct net_device *dev, u32 data, int len)
  1204. {
  1205. int i;
  1206. for (i = len - 1; i >= 0; i--) {
  1207. mii_sendbit (dev, data & (1 << i));
  1208. }
  1209. }
  1210. static int
  1211. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1212. {
  1213. u32 cmd;
  1214. int i;
  1215. u32 retval = 0;
  1216. /* Preamble */
  1217. mii_send_bits (dev, 0xffffffff, 32);
  1218. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1219. /* ST,OP = 0110'b for read operation */
  1220. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1221. mii_send_bits (dev, cmd, 14);
  1222. /* Turnaround */
  1223. if (mii_getbit (dev))
  1224. goto err_out;
  1225. /* Read data */
  1226. for (i = 0; i < 16; i++) {
  1227. retval |= mii_getbit (dev);
  1228. retval <<= 1;
  1229. }
  1230. /* End cycle */
  1231. mii_getbit (dev);
  1232. return (retval >> 1) & 0xffff;
  1233. err_out:
  1234. return 0;
  1235. }
  1236. static int
  1237. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1238. {
  1239. u32 cmd;
  1240. /* Preamble */
  1241. mii_send_bits (dev, 0xffffffff, 32);
  1242. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1243. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1244. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1245. mii_send_bits (dev, cmd, 32);
  1246. /* End cycle */
  1247. mii_getbit (dev);
  1248. return 0;
  1249. }
  1250. static int
  1251. mii_wait_link (struct net_device *dev, int wait)
  1252. {
  1253. __u16 bmsr;
  1254. int phy_addr;
  1255. struct netdev_private *np;
  1256. np = netdev_priv(dev);
  1257. phy_addr = np->phy_addr;
  1258. do {
  1259. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1260. if (bmsr & BMSR_LSTATUS)
  1261. return 0;
  1262. mdelay (1);
  1263. } while (--wait > 0);
  1264. return -1;
  1265. }
  1266. static int
  1267. mii_get_media (struct net_device *dev)
  1268. {
  1269. __u16 negotiate;
  1270. __u16 bmsr;
  1271. __u16 mscr;
  1272. __u16 mssr;
  1273. int phy_addr;
  1274. struct netdev_private *np;
  1275. np = netdev_priv(dev);
  1276. phy_addr = np->phy_addr;
  1277. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1278. if (np->an_enable) {
  1279. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1280. /* Auto-Negotiation not completed */
  1281. return -1;
  1282. }
  1283. negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1284. mii_read (dev, phy_addr, MII_LPA);
  1285. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1286. mssr = mii_read (dev, phy_addr, MII_STAT1000);
  1287. if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
  1288. np->speed = 1000;
  1289. np->full_duplex = 1;
  1290. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1291. } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
  1292. np->speed = 1000;
  1293. np->full_duplex = 0;
  1294. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1295. } else if (negotiate & ADVERTISE_100FULL) {
  1296. np->speed = 100;
  1297. np->full_duplex = 1;
  1298. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1299. } else if (negotiate & ADVERTISE_100HALF) {
  1300. np->speed = 100;
  1301. np->full_duplex = 0;
  1302. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1303. } else if (negotiate & ADVERTISE_10FULL) {
  1304. np->speed = 10;
  1305. np->full_duplex = 1;
  1306. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1307. } else if (negotiate & ADVERTISE_10HALF) {
  1308. np->speed = 10;
  1309. np->full_duplex = 0;
  1310. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1311. }
  1312. if (negotiate & ADVERTISE_PAUSE_CAP) {
  1313. np->tx_flow &= 1;
  1314. np->rx_flow &= 1;
  1315. } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
  1316. np->tx_flow = 0;
  1317. np->rx_flow &= 1;
  1318. }
  1319. /* else tx_flow, rx_flow = user select */
  1320. } else {
  1321. __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1322. switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
  1323. case BMCR_SPEED1000:
  1324. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1325. break;
  1326. case BMCR_SPEED100:
  1327. printk (KERN_INFO "Operating at 100 Mbps, ");
  1328. break;
  1329. case 0:
  1330. printk (KERN_INFO "Operating at 10 Mbps, ");
  1331. }
  1332. if (bmcr & BMCR_FULLDPLX) {
  1333. printk (KERN_CONT "Full duplex\n");
  1334. } else {
  1335. printk (KERN_CONT "Half duplex\n");
  1336. }
  1337. }
  1338. if (np->tx_flow)
  1339. printk(KERN_INFO "Enable Tx Flow Control\n");
  1340. else
  1341. printk(KERN_INFO "Disable Tx Flow Control\n");
  1342. if (np->rx_flow)
  1343. printk(KERN_INFO "Enable Rx Flow Control\n");
  1344. else
  1345. printk(KERN_INFO "Disable Rx Flow Control\n");
  1346. return 0;
  1347. }
  1348. static int
  1349. mii_set_media (struct net_device *dev)
  1350. {
  1351. __u16 pscr;
  1352. __u16 bmcr;
  1353. __u16 bmsr;
  1354. __u16 anar;
  1355. int phy_addr;
  1356. struct netdev_private *np;
  1357. np = netdev_priv(dev);
  1358. phy_addr = np->phy_addr;
  1359. /* Does user set speed? */
  1360. if (np->an_enable) {
  1361. /* Advertise capabilities */
  1362. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1363. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1364. ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
  1365. ADVERTISE_100HALF | ADVERTISE_10HALF |
  1366. ADVERTISE_100BASE4);
  1367. if (bmsr & BMSR_100FULL)
  1368. anar |= ADVERTISE_100FULL;
  1369. if (bmsr & BMSR_100HALF)
  1370. anar |= ADVERTISE_100HALF;
  1371. if (bmsr & BMSR_100BASE4)
  1372. anar |= ADVERTISE_100BASE4;
  1373. if (bmsr & BMSR_10FULL)
  1374. anar |= ADVERTISE_10FULL;
  1375. if (bmsr & BMSR_10HALF)
  1376. anar |= ADVERTISE_10HALF;
  1377. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1378. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1379. /* Enable Auto crossover */
  1380. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1381. pscr |= 3 << 5; /* 11'b */
  1382. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1383. /* Soft reset PHY */
  1384. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1385. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1386. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1387. mdelay(1);
  1388. } else {
  1389. /* Force speed setting */
  1390. /* 1) Disable Auto crossover */
  1391. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1392. pscr &= ~(3 << 5);
  1393. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1394. /* 2) PHY Reset */
  1395. bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1396. bmcr |= BMCR_RESET;
  1397. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1398. /* 3) Power Down */
  1399. bmcr = 0x1940; /* must be 0x1940 */
  1400. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1401. mdelay (100); /* wait a certain time */
  1402. /* 4) Advertise nothing */
  1403. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1404. /* 5) Set media and Power Up */
  1405. bmcr = BMCR_PDOWN;
  1406. if (np->speed == 100) {
  1407. bmcr |= BMCR_SPEED100;
  1408. printk (KERN_INFO "Manual 100 Mbps, ");
  1409. } else if (np->speed == 10) {
  1410. printk (KERN_INFO "Manual 10 Mbps, ");
  1411. }
  1412. if (np->full_duplex) {
  1413. bmcr |= BMCR_FULLDPLX;
  1414. printk (KERN_CONT "Full duplex\n");
  1415. } else {
  1416. printk (KERN_CONT "Half duplex\n");
  1417. }
  1418. #if 0
  1419. /* Set 1000BaseT Master/Slave setting */
  1420. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1421. mscr |= MII_MSCR_CFG_ENABLE;
  1422. mscr &= ~MII_MSCR_CFG_VALUE = 0;
  1423. #endif
  1424. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1425. mdelay(10);
  1426. }
  1427. return 0;
  1428. }
  1429. static int
  1430. mii_get_media_pcs (struct net_device *dev)
  1431. {
  1432. __u16 negotiate;
  1433. __u16 bmsr;
  1434. int phy_addr;
  1435. struct netdev_private *np;
  1436. np = netdev_priv(dev);
  1437. phy_addr = np->phy_addr;
  1438. bmsr = mii_read (dev, phy_addr, PCS_BMSR);
  1439. if (np->an_enable) {
  1440. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1441. /* Auto-Negotiation not completed */
  1442. return -1;
  1443. }
  1444. negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
  1445. mii_read (dev, phy_addr, PCS_ANLPAR);
  1446. np->speed = 1000;
  1447. if (negotiate & PCS_ANAR_FULL_DUPLEX) {
  1448. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1449. np->full_duplex = 1;
  1450. } else {
  1451. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1452. np->full_duplex = 0;
  1453. }
  1454. if (negotiate & PCS_ANAR_PAUSE) {
  1455. np->tx_flow &= 1;
  1456. np->rx_flow &= 1;
  1457. } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
  1458. np->tx_flow = 0;
  1459. np->rx_flow &= 1;
  1460. }
  1461. /* else tx_flow, rx_flow = user select */
  1462. } else {
  1463. __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
  1464. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1465. if (bmcr & BMCR_FULLDPLX) {
  1466. printk (KERN_CONT "Full duplex\n");
  1467. } else {
  1468. printk (KERN_CONT "Half duplex\n");
  1469. }
  1470. }
  1471. if (np->tx_flow)
  1472. printk(KERN_INFO "Enable Tx Flow Control\n");
  1473. else
  1474. printk(KERN_INFO "Disable Tx Flow Control\n");
  1475. if (np->rx_flow)
  1476. printk(KERN_INFO "Enable Rx Flow Control\n");
  1477. else
  1478. printk(KERN_INFO "Disable Rx Flow Control\n");
  1479. return 0;
  1480. }
  1481. static int
  1482. mii_set_media_pcs (struct net_device *dev)
  1483. {
  1484. __u16 bmcr;
  1485. __u16 esr;
  1486. __u16 anar;
  1487. int phy_addr;
  1488. struct netdev_private *np;
  1489. np = netdev_priv(dev);
  1490. phy_addr = np->phy_addr;
  1491. /* Auto-Negotiation? */
  1492. if (np->an_enable) {
  1493. /* Advertise capabilities */
  1494. esr = mii_read (dev, phy_addr, PCS_ESR);
  1495. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1496. ~PCS_ANAR_HALF_DUPLEX &
  1497. ~PCS_ANAR_FULL_DUPLEX;
  1498. if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
  1499. anar |= PCS_ANAR_HALF_DUPLEX;
  1500. if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
  1501. anar |= PCS_ANAR_FULL_DUPLEX;
  1502. anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
  1503. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1504. /* Soft reset PHY */
  1505. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1506. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1507. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1508. mdelay(1);
  1509. } else {
  1510. /* Force speed setting */
  1511. /* PHY Reset */
  1512. bmcr = BMCR_RESET;
  1513. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1514. mdelay(10);
  1515. if (np->full_duplex) {
  1516. bmcr = BMCR_FULLDPLX;
  1517. printk (KERN_INFO "Manual full duplex\n");
  1518. } else {
  1519. bmcr = 0;
  1520. printk (KERN_INFO "Manual half duplex\n");
  1521. }
  1522. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1523. mdelay(10);
  1524. /* Advertise nothing */
  1525. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1526. }
  1527. return 0;
  1528. }
  1529. static int
  1530. rio_close (struct net_device *dev)
  1531. {
  1532. long ioaddr = dev->base_addr;
  1533. struct netdev_private *np = netdev_priv(dev);
  1534. struct sk_buff *skb;
  1535. int i;
  1536. netif_stop_queue (dev);
  1537. /* Disable interrupts */
  1538. writew (0, ioaddr + IntEnable);
  1539. /* Stop Tx and Rx logics */
  1540. writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
  1541. free_irq (dev->irq, dev);
  1542. del_timer_sync (&np->timer);
  1543. /* Free all the skbuffs in the queue. */
  1544. for (i = 0; i < RX_RING_SIZE; i++) {
  1545. skb = np->rx_skbuff[i];
  1546. if (skb) {
  1547. pci_unmap_single(np->pdev,
  1548. desc_to_dma(&np->rx_ring[i]),
  1549. skb->len, PCI_DMA_FROMDEVICE);
  1550. dev_kfree_skb (skb);
  1551. np->rx_skbuff[i] = NULL;
  1552. }
  1553. np->rx_ring[i].status = 0;
  1554. np->rx_ring[i].fraginfo = 0;
  1555. }
  1556. for (i = 0; i < TX_RING_SIZE; i++) {
  1557. skb = np->tx_skbuff[i];
  1558. if (skb) {
  1559. pci_unmap_single(np->pdev,
  1560. desc_to_dma(&np->tx_ring[i]),
  1561. skb->len, PCI_DMA_TODEVICE);
  1562. dev_kfree_skb (skb);
  1563. np->tx_skbuff[i] = NULL;
  1564. }
  1565. }
  1566. return 0;
  1567. }
  1568. static void __devexit
  1569. rio_remove1 (struct pci_dev *pdev)
  1570. {
  1571. struct net_device *dev = pci_get_drvdata (pdev);
  1572. if (dev) {
  1573. struct netdev_private *np = netdev_priv(dev);
  1574. unregister_netdev (dev);
  1575. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
  1576. np->rx_ring_dma);
  1577. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
  1578. np->tx_ring_dma);
  1579. #ifdef MEM_MAPPING
  1580. iounmap ((char *) (dev->base_addr));
  1581. #endif
  1582. free_netdev (dev);
  1583. pci_release_regions (pdev);
  1584. pci_disable_device (pdev);
  1585. }
  1586. pci_set_drvdata (pdev, NULL);
  1587. }
  1588. static struct pci_driver rio_driver = {
  1589. .name = "dl2k",
  1590. .id_table = rio_pci_tbl,
  1591. .probe = rio_probe1,
  1592. .remove = __devexit_p(rio_remove1),
  1593. };
  1594. static int __init
  1595. rio_init (void)
  1596. {
  1597. return pci_register_driver(&rio_driver);
  1598. }
  1599. static void __exit
  1600. rio_exit (void)
  1601. {
  1602. pci_unregister_driver (&rio_driver);
  1603. }
  1604. module_init (rio_init);
  1605. module_exit (rio_exit);
  1606. /*
  1607. Compile command:
  1608. gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
  1609. Read Documentation/networking/dl2k.txt for details.
  1610. */