emufx.c 99 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Creative Labs, Inc.
  4. * Routines for effect processor FX8010
  5. *
  6. * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
  7. * Added EMU 1010 support.
  8. *
  9. * BUGS:
  10. * --
  11. *
  12. * TODO:
  13. * --
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  28. *
  29. */
  30. #include <linux/pci.h>
  31. #include <linux/capability.h>
  32. #include <linux/delay.h>
  33. #include <linux/slab.h>
  34. #include <linux/vmalloc.h>
  35. #include <linux/init.h>
  36. #include <linux/mutex.h>
  37. #include <linux/moduleparam.h>
  38. #include <sound/core.h>
  39. #include <sound/tlv.h>
  40. #include <sound/emu10k1.h>
  41. #if 0 /* for testing purposes - digital out -> capture */
  42. #define EMU10K1_CAPTURE_DIGITAL_OUT
  43. #endif
  44. #if 0 /* for testing purposes - set S/PDIF to AC3 output */
  45. #define EMU10K1_SET_AC3_IEC958
  46. #endif
  47. #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
  48. #define EMU10K1_CENTER_LFE_FROM_FRONT
  49. #endif
  50. static bool high_res_gpr_volume;
  51. module_param(high_res_gpr_volume, bool, 0444);
  52. MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
  53. /*
  54. * Tables
  55. */
  56. static char *fxbuses[16] = {
  57. /* 0x00 */ "PCM Left",
  58. /* 0x01 */ "PCM Right",
  59. /* 0x02 */ "PCM Surround Left",
  60. /* 0x03 */ "PCM Surround Right",
  61. /* 0x04 */ "MIDI Left",
  62. /* 0x05 */ "MIDI Right",
  63. /* 0x06 */ "Center",
  64. /* 0x07 */ "LFE",
  65. /* 0x08 */ NULL,
  66. /* 0x09 */ NULL,
  67. /* 0x0a */ NULL,
  68. /* 0x0b */ NULL,
  69. /* 0x0c */ "MIDI Reverb",
  70. /* 0x0d */ "MIDI Chorus",
  71. /* 0x0e */ NULL,
  72. /* 0x0f */ NULL
  73. };
  74. static char *creative_ins[16] = {
  75. /* 0x00 */ "AC97 Left",
  76. /* 0x01 */ "AC97 Right",
  77. /* 0x02 */ "TTL IEC958 Left",
  78. /* 0x03 */ "TTL IEC958 Right",
  79. /* 0x04 */ "Zoom Video Left",
  80. /* 0x05 */ "Zoom Video Right",
  81. /* 0x06 */ "Optical IEC958 Left",
  82. /* 0x07 */ "Optical IEC958 Right",
  83. /* 0x08 */ "Line/Mic 1 Left",
  84. /* 0x09 */ "Line/Mic 1 Right",
  85. /* 0x0a */ "Coaxial IEC958 Left",
  86. /* 0x0b */ "Coaxial IEC958 Right",
  87. /* 0x0c */ "Line/Mic 2 Left",
  88. /* 0x0d */ "Line/Mic 2 Right",
  89. /* 0x0e */ NULL,
  90. /* 0x0f */ NULL
  91. };
  92. static char *audigy_ins[16] = {
  93. /* 0x00 */ "AC97 Left",
  94. /* 0x01 */ "AC97 Right",
  95. /* 0x02 */ "Audigy CD Left",
  96. /* 0x03 */ "Audigy CD Right",
  97. /* 0x04 */ "Optical IEC958 Left",
  98. /* 0x05 */ "Optical IEC958 Right",
  99. /* 0x06 */ NULL,
  100. /* 0x07 */ NULL,
  101. /* 0x08 */ "Line/Mic 2 Left",
  102. /* 0x09 */ "Line/Mic 2 Right",
  103. /* 0x0a */ "SPDIF Left",
  104. /* 0x0b */ "SPDIF Right",
  105. /* 0x0c */ "Aux2 Left",
  106. /* 0x0d */ "Aux2 Right",
  107. /* 0x0e */ NULL,
  108. /* 0x0f */ NULL
  109. };
  110. static char *creative_outs[32] = {
  111. /* 0x00 */ "AC97 Left",
  112. /* 0x01 */ "AC97 Right",
  113. /* 0x02 */ "Optical IEC958 Left",
  114. /* 0x03 */ "Optical IEC958 Right",
  115. /* 0x04 */ "Center",
  116. /* 0x05 */ "LFE",
  117. /* 0x06 */ "Headphone Left",
  118. /* 0x07 */ "Headphone Right",
  119. /* 0x08 */ "Surround Left",
  120. /* 0x09 */ "Surround Right",
  121. /* 0x0a */ "PCM Capture Left",
  122. /* 0x0b */ "PCM Capture Right",
  123. /* 0x0c */ "MIC Capture",
  124. /* 0x0d */ "AC97 Surround Left",
  125. /* 0x0e */ "AC97 Surround Right",
  126. /* 0x0f */ NULL,
  127. /* 0x10 */ NULL,
  128. /* 0x11 */ "Analog Center",
  129. /* 0x12 */ "Analog LFE",
  130. /* 0x13 */ NULL,
  131. /* 0x14 */ NULL,
  132. /* 0x15 */ NULL,
  133. /* 0x16 */ NULL,
  134. /* 0x17 */ NULL,
  135. /* 0x18 */ NULL,
  136. /* 0x19 */ NULL,
  137. /* 0x1a */ NULL,
  138. /* 0x1b */ NULL,
  139. /* 0x1c */ NULL,
  140. /* 0x1d */ NULL,
  141. /* 0x1e */ NULL,
  142. /* 0x1f */ NULL,
  143. };
  144. static char *audigy_outs[32] = {
  145. /* 0x00 */ "Digital Front Left",
  146. /* 0x01 */ "Digital Front Right",
  147. /* 0x02 */ "Digital Center",
  148. /* 0x03 */ "Digital LEF",
  149. /* 0x04 */ "Headphone Left",
  150. /* 0x05 */ "Headphone Right",
  151. /* 0x06 */ "Digital Rear Left",
  152. /* 0x07 */ "Digital Rear Right",
  153. /* 0x08 */ "Front Left",
  154. /* 0x09 */ "Front Right",
  155. /* 0x0a */ "Center",
  156. /* 0x0b */ "LFE",
  157. /* 0x0c */ NULL,
  158. /* 0x0d */ NULL,
  159. /* 0x0e */ "Rear Left",
  160. /* 0x0f */ "Rear Right",
  161. /* 0x10 */ "AC97 Front Left",
  162. /* 0x11 */ "AC97 Front Right",
  163. /* 0x12 */ "ADC Caputre Left",
  164. /* 0x13 */ "ADC Capture Right",
  165. /* 0x14 */ NULL,
  166. /* 0x15 */ NULL,
  167. /* 0x16 */ NULL,
  168. /* 0x17 */ NULL,
  169. /* 0x18 */ NULL,
  170. /* 0x19 */ NULL,
  171. /* 0x1a */ NULL,
  172. /* 0x1b */ NULL,
  173. /* 0x1c */ NULL,
  174. /* 0x1d */ NULL,
  175. /* 0x1e */ NULL,
  176. /* 0x1f */ NULL,
  177. };
  178. static const u32 bass_table[41][5] = {
  179. { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
  180. { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
  181. { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
  182. { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
  183. { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
  184. { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
  185. { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
  186. { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
  187. { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
  188. { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
  189. { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
  190. { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
  191. { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
  192. { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
  193. { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
  194. { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
  195. { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
  196. { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
  197. { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
  198. { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
  199. { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
  200. { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
  201. { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
  202. { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
  203. { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
  204. { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
  205. { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
  206. { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
  207. { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
  208. { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
  209. { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
  210. { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
  211. { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
  212. { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
  213. { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
  214. { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
  215. { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
  216. { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
  217. { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
  218. { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
  219. { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
  220. };
  221. static const u32 treble_table[41][5] = {
  222. { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
  223. { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
  224. { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
  225. { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
  226. { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
  227. { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
  228. { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
  229. { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
  230. { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
  231. { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
  232. { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
  233. { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
  234. { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
  235. { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
  236. { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
  237. { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
  238. { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
  239. { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
  240. { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
  241. { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
  242. { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
  243. { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
  244. { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
  245. { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
  246. { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
  247. { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
  248. { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
  249. { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
  250. { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
  251. { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
  252. { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
  253. { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
  254. { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
  255. { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
  256. { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
  257. { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
  258. { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
  259. { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
  260. { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
  261. { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
  262. { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
  263. };
  264. /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
  265. static const u32 db_table[101] = {
  266. 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
  267. 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
  268. 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
  269. 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
  270. 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
  271. 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
  272. 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
  273. 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
  274. 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
  275. 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
  276. 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
  277. 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
  278. 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
  279. 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
  280. 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
  281. 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
  282. 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
  283. 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
  284. 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
  285. 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
  286. 0x7fffffff,
  287. };
  288. /* EMU10k1/EMU10k2 DSP control db gain */
  289. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
  290. static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
  291. /* EMU10K1 bass/treble db gain */
  292. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
  293. static const u32 onoff_table[2] = {
  294. 0x00000000, 0x00000001
  295. };
  296. /*
  297. */
  298. static inline mm_segment_t snd_enter_user(void)
  299. {
  300. mm_segment_t fs = get_fs();
  301. set_fs(get_ds());
  302. return fs;
  303. }
  304. static inline void snd_leave_user(mm_segment_t fs)
  305. {
  306. set_fs(fs);
  307. }
  308. /*
  309. * controls
  310. */
  311. static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  312. {
  313. struct snd_emu10k1_fx8010_ctl *ctl =
  314. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  315. if (ctl->min == 0 && ctl->max == 1)
  316. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  317. else
  318. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  319. uinfo->count = ctl->vcount;
  320. uinfo->value.integer.min = ctl->min;
  321. uinfo->value.integer.max = ctl->max;
  322. return 0;
  323. }
  324. static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  325. {
  326. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  327. struct snd_emu10k1_fx8010_ctl *ctl =
  328. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  329. unsigned long flags;
  330. unsigned int i;
  331. spin_lock_irqsave(&emu->reg_lock, flags);
  332. for (i = 0; i < ctl->vcount; i++)
  333. ucontrol->value.integer.value[i] = ctl->value[i];
  334. spin_unlock_irqrestore(&emu->reg_lock, flags);
  335. return 0;
  336. }
  337. static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  338. {
  339. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  340. struct snd_emu10k1_fx8010_ctl *ctl =
  341. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  342. unsigned long flags;
  343. unsigned int nval, val;
  344. unsigned int i, j;
  345. int change = 0;
  346. spin_lock_irqsave(&emu->reg_lock, flags);
  347. for (i = 0; i < ctl->vcount; i++) {
  348. nval = ucontrol->value.integer.value[i];
  349. if (nval < ctl->min)
  350. nval = ctl->min;
  351. if (nval > ctl->max)
  352. nval = ctl->max;
  353. if (nval != ctl->value[i])
  354. change = 1;
  355. val = ctl->value[i] = nval;
  356. switch (ctl->translation) {
  357. case EMU10K1_GPR_TRANSLATION_NONE:
  358. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
  359. break;
  360. case EMU10K1_GPR_TRANSLATION_TABLE100:
  361. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
  362. break;
  363. case EMU10K1_GPR_TRANSLATION_BASS:
  364. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  365. change = -EIO;
  366. goto __error;
  367. }
  368. for (j = 0; j < 5; j++)
  369. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
  370. break;
  371. case EMU10K1_GPR_TRANSLATION_TREBLE:
  372. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  373. change = -EIO;
  374. goto __error;
  375. }
  376. for (j = 0; j < 5; j++)
  377. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
  378. break;
  379. case EMU10K1_GPR_TRANSLATION_ONOFF:
  380. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
  381. break;
  382. }
  383. }
  384. __error:
  385. spin_unlock_irqrestore(&emu->reg_lock, flags);
  386. return change;
  387. }
  388. /*
  389. * Interrupt handler
  390. */
  391. static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
  392. {
  393. struct snd_emu10k1_fx8010_irq *irq, *nirq;
  394. irq = emu->fx8010.irq_handlers;
  395. while (irq) {
  396. nirq = irq->next; /* irq ptr can be removed from list */
  397. if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
  398. if (irq->handler)
  399. irq->handler(emu, irq->private_data);
  400. snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
  401. }
  402. irq = nirq;
  403. }
  404. }
  405. int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
  406. snd_fx8010_irq_handler_t *handler,
  407. unsigned char gpr_running,
  408. void *private_data,
  409. struct snd_emu10k1_fx8010_irq **r_irq)
  410. {
  411. struct snd_emu10k1_fx8010_irq *irq;
  412. unsigned long flags;
  413. irq = kmalloc(sizeof(*irq), GFP_ATOMIC);
  414. if (irq == NULL)
  415. return -ENOMEM;
  416. irq->handler = handler;
  417. irq->gpr_running = gpr_running;
  418. irq->private_data = private_data;
  419. irq->next = NULL;
  420. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  421. if (emu->fx8010.irq_handlers == NULL) {
  422. emu->fx8010.irq_handlers = irq;
  423. emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
  424. snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
  425. } else {
  426. irq->next = emu->fx8010.irq_handlers;
  427. emu->fx8010.irq_handlers = irq;
  428. }
  429. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  430. if (r_irq)
  431. *r_irq = irq;
  432. return 0;
  433. }
  434. int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
  435. struct snd_emu10k1_fx8010_irq *irq)
  436. {
  437. struct snd_emu10k1_fx8010_irq *tmp;
  438. unsigned long flags;
  439. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  440. if ((tmp = emu->fx8010.irq_handlers) == irq) {
  441. emu->fx8010.irq_handlers = tmp->next;
  442. if (emu->fx8010.irq_handlers == NULL) {
  443. snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
  444. emu->dsp_interrupt = NULL;
  445. }
  446. } else {
  447. while (tmp && tmp->next != irq)
  448. tmp = tmp->next;
  449. if (tmp)
  450. tmp->next = tmp->next->next;
  451. }
  452. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  453. kfree(irq);
  454. return 0;
  455. }
  456. /*************************************************************************
  457. * EMU10K1 effect manager
  458. *************************************************************************/
  459. static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
  460. unsigned int *ptr,
  461. u32 op, u32 r, u32 a, u32 x, u32 y)
  462. {
  463. u_int32_t *code;
  464. if (snd_BUG_ON(*ptr >= 512))
  465. return;
  466. code = (u_int32_t __force *)icode->code + (*ptr) * 2;
  467. set_bit(*ptr, icode->code_valid);
  468. code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
  469. code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
  470. (*ptr)++;
  471. }
  472. #define OP(icode, ptr, op, r, a, x, y) \
  473. snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
  474. static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
  475. unsigned int *ptr,
  476. u32 op, u32 r, u32 a, u32 x, u32 y)
  477. {
  478. u_int32_t *code;
  479. if (snd_BUG_ON(*ptr >= 1024))
  480. return;
  481. code = (u_int32_t __force *)icode->code + (*ptr) * 2;
  482. set_bit(*ptr, icode->code_valid);
  483. code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
  484. code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
  485. (*ptr)++;
  486. }
  487. #define A_OP(icode, ptr, op, r, a, x, y) \
  488. snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
  489. static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
  490. {
  491. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  492. snd_emu10k1_ptr_write(emu, pc, 0, data);
  493. }
  494. unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
  495. {
  496. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  497. return snd_emu10k1_ptr_read(emu, pc, 0);
  498. }
  499. static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
  500. struct snd_emu10k1_fx8010_code *icode)
  501. {
  502. int gpr;
  503. u32 val;
  504. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  505. if (!test_bit(gpr, icode->gpr_valid))
  506. continue;
  507. if (get_user(val, &icode->gpr_map[gpr]))
  508. return -EFAULT;
  509. snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
  510. }
  511. return 0;
  512. }
  513. static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
  514. struct snd_emu10k1_fx8010_code *icode)
  515. {
  516. int gpr;
  517. u32 val;
  518. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  519. set_bit(gpr, icode->gpr_valid);
  520. val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
  521. if (put_user(val, &icode->gpr_map[gpr]))
  522. return -EFAULT;
  523. }
  524. return 0;
  525. }
  526. static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
  527. struct snd_emu10k1_fx8010_code *icode)
  528. {
  529. int tram;
  530. u32 addr, val;
  531. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  532. if (!test_bit(tram, icode->tram_valid))
  533. continue;
  534. if (get_user(val, &icode->tram_data_map[tram]) ||
  535. get_user(addr, &icode->tram_addr_map[tram]))
  536. return -EFAULT;
  537. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
  538. if (!emu->audigy) {
  539. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
  540. } else {
  541. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
  542. snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
  543. }
  544. }
  545. return 0;
  546. }
  547. static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
  548. struct snd_emu10k1_fx8010_code *icode)
  549. {
  550. int tram;
  551. u32 val, addr;
  552. memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
  553. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  554. set_bit(tram, icode->tram_valid);
  555. val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
  556. if (!emu->audigy) {
  557. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
  558. } else {
  559. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
  560. addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
  561. }
  562. if (put_user(val, &icode->tram_data_map[tram]) ||
  563. put_user(addr, &icode->tram_addr_map[tram]))
  564. return -EFAULT;
  565. }
  566. return 0;
  567. }
  568. static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
  569. struct snd_emu10k1_fx8010_code *icode)
  570. {
  571. u32 pc, lo, hi;
  572. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  573. if (!test_bit(pc / 2, icode->code_valid))
  574. continue;
  575. if (get_user(lo, &icode->code[pc + 0]) ||
  576. get_user(hi, &icode->code[pc + 1]))
  577. return -EFAULT;
  578. snd_emu10k1_efx_write(emu, pc + 0, lo);
  579. snd_emu10k1_efx_write(emu, pc + 1, hi);
  580. }
  581. return 0;
  582. }
  583. static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
  584. struct snd_emu10k1_fx8010_code *icode)
  585. {
  586. u32 pc;
  587. memset(icode->code_valid, 0, sizeof(icode->code_valid));
  588. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  589. set_bit(pc / 2, icode->code_valid);
  590. if (put_user(snd_emu10k1_efx_read(emu, pc + 0), &icode->code[pc + 0]))
  591. return -EFAULT;
  592. if (put_user(snd_emu10k1_efx_read(emu, pc + 1), &icode->code[pc + 1]))
  593. return -EFAULT;
  594. }
  595. return 0;
  596. }
  597. static struct snd_emu10k1_fx8010_ctl *
  598. snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, struct snd_ctl_elem_id *id)
  599. {
  600. struct snd_emu10k1_fx8010_ctl *ctl;
  601. struct snd_kcontrol *kcontrol;
  602. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  603. kcontrol = ctl->kcontrol;
  604. if (kcontrol->id.iface == id->iface &&
  605. !strcmp(kcontrol->id.name, id->name) &&
  606. kcontrol->id.index == id->index)
  607. return ctl;
  608. }
  609. return NULL;
  610. }
  611. #define MAX_TLV_SIZE 256
  612. static unsigned int *copy_tlv(const unsigned int __user *_tlv)
  613. {
  614. unsigned int data[2];
  615. unsigned int *tlv;
  616. if (!_tlv)
  617. return NULL;
  618. if (copy_from_user(data, _tlv, sizeof(data)))
  619. return NULL;
  620. if (data[1] >= MAX_TLV_SIZE)
  621. return NULL;
  622. tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
  623. if (!tlv)
  624. return NULL;
  625. memcpy(tlv, data, sizeof(data));
  626. if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
  627. kfree(tlv);
  628. return NULL;
  629. }
  630. return tlv;
  631. }
  632. static int copy_gctl(struct snd_emu10k1 *emu,
  633. struct snd_emu10k1_fx8010_control_gpr *gctl,
  634. struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
  635. int idx)
  636. {
  637. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  638. if (emu->support_tlv)
  639. return copy_from_user(gctl, &_gctl[idx], sizeof(*gctl));
  640. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
  641. if (copy_from_user(gctl, &octl[idx], sizeof(*octl)))
  642. return -EFAULT;
  643. gctl->tlv = NULL;
  644. return 0;
  645. }
  646. static int copy_gctl_to_user(struct snd_emu10k1 *emu,
  647. struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
  648. struct snd_emu10k1_fx8010_control_gpr *gctl,
  649. int idx)
  650. {
  651. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  652. if (emu->support_tlv)
  653. return copy_to_user(&_gctl[idx], gctl, sizeof(*gctl));
  654. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
  655. return copy_to_user(&octl[idx], gctl, sizeof(*octl));
  656. }
  657. static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
  658. struct snd_emu10k1_fx8010_code *icode)
  659. {
  660. unsigned int i;
  661. struct snd_ctl_elem_id __user *_id;
  662. struct snd_ctl_elem_id id;
  663. struct snd_emu10k1_fx8010_control_gpr *gctl;
  664. int err;
  665. for (i = 0, _id = icode->gpr_del_controls;
  666. i < icode->gpr_del_control_count; i++, _id++) {
  667. if (copy_from_user(&id, _id, sizeof(id)))
  668. return -EFAULT;
  669. if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
  670. return -ENOENT;
  671. }
  672. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  673. if (! gctl)
  674. return -ENOMEM;
  675. err = 0;
  676. for (i = 0; i < icode->gpr_add_control_count; i++) {
  677. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
  678. err = -EFAULT;
  679. goto __error;
  680. }
  681. if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
  682. continue;
  683. down_read(&emu->card->controls_rwsem);
  684. if (snd_ctl_find_id(emu->card, &gctl->id) != NULL) {
  685. up_read(&emu->card->controls_rwsem);
  686. err = -EEXIST;
  687. goto __error;
  688. }
  689. up_read(&emu->card->controls_rwsem);
  690. if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  691. gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  692. err = -EINVAL;
  693. goto __error;
  694. }
  695. }
  696. for (i = 0; i < icode->gpr_list_control_count; i++) {
  697. /* FIXME: we need to check the WRITE access */
  698. if (copy_gctl(emu, gctl, icode->gpr_list_controls, i)) {
  699. err = -EFAULT;
  700. goto __error;
  701. }
  702. }
  703. __error:
  704. kfree(gctl);
  705. return err;
  706. }
  707. static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
  708. {
  709. struct snd_emu10k1_fx8010_ctl *ctl;
  710. ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
  711. kctl->private_value = 0;
  712. list_del(&ctl->list);
  713. kfree(ctl);
  714. if (kctl->tlv.p)
  715. kfree(kctl->tlv.p);
  716. }
  717. static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
  718. struct snd_emu10k1_fx8010_code *icode)
  719. {
  720. unsigned int i, j;
  721. struct snd_emu10k1_fx8010_control_gpr *gctl;
  722. struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
  723. struct snd_kcontrol_new knew;
  724. struct snd_kcontrol *kctl;
  725. struct snd_ctl_elem_value *val;
  726. int err = 0;
  727. val = kmalloc(sizeof(*val), GFP_KERNEL);
  728. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  729. nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
  730. if (!val || !gctl || !nctl) {
  731. err = -ENOMEM;
  732. goto __error;
  733. }
  734. for (i = 0; i < icode->gpr_add_control_count; i++) {
  735. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
  736. err = -EFAULT;
  737. goto __error;
  738. }
  739. if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  740. gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  741. err = -EINVAL;
  742. goto __error;
  743. }
  744. if (! gctl->id.name[0]) {
  745. err = -EINVAL;
  746. goto __error;
  747. }
  748. ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
  749. memset(&knew, 0, sizeof(knew));
  750. knew.iface = gctl->id.iface;
  751. knew.name = gctl->id.name;
  752. knew.index = gctl->id.index;
  753. knew.device = gctl->id.device;
  754. knew.subdevice = gctl->id.subdevice;
  755. knew.info = snd_emu10k1_gpr_ctl_info;
  756. knew.tlv.p = copy_tlv(gctl->tlv);
  757. if (knew.tlv.p)
  758. knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  759. SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  760. knew.get = snd_emu10k1_gpr_ctl_get;
  761. knew.put = snd_emu10k1_gpr_ctl_put;
  762. memset(nctl, 0, sizeof(*nctl));
  763. nctl->vcount = gctl->vcount;
  764. nctl->count = gctl->count;
  765. for (j = 0; j < 32; j++) {
  766. nctl->gpr[j] = gctl->gpr[j];
  767. nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
  768. val->value.integer.value[j] = gctl->value[j];
  769. }
  770. nctl->min = gctl->min;
  771. nctl->max = gctl->max;
  772. nctl->translation = gctl->translation;
  773. if (ctl == NULL) {
  774. ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
  775. if (ctl == NULL) {
  776. err = -ENOMEM;
  777. kfree(knew.tlv.p);
  778. goto __error;
  779. }
  780. knew.private_value = (unsigned long)ctl;
  781. *ctl = *nctl;
  782. if ((err = snd_ctl_add(emu->card, kctl = snd_ctl_new1(&knew, emu))) < 0) {
  783. kfree(ctl);
  784. kfree(knew.tlv.p);
  785. goto __error;
  786. }
  787. kctl->private_free = snd_emu10k1_ctl_private_free;
  788. ctl->kcontrol = kctl;
  789. list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
  790. } else {
  791. /* overwrite */
  792. nctl->list = ctl->list;
  793. nctl->kcontrol = ctl->kcontrol;
  794. *ctl = *nctl;
  795. snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
  796. SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
  797. }
  798. snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
  799. }
  800. __error:
  801. kfree(nctl);
  802. kfree(gctl);
  803. kfree(val);
  804. return err;
  805. }
  806. static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
  807. struct snd_emu10k1_fx8010_code *icode)
  808. {
  809. unsigned int i;
  810. struct snd_ctl_elem_id id;
  811. struct snd_ctl_elem_id __user *_id;
  812. struct snd_emu10k1_fx8010_ctl *ctl;
  813. struct snd_card *card = emu->card;
  814. for (i = 0, _id = icode->gpr_del_controls;
  815. i < icode->gpr_del_control_count; i++, _id++) {
  816. if (copy_from_user(&id, _id, sizeof(id)))
  817. return -EFAULT;
  818. down_write(&card->controls_rwsem);
  819. ctl = snd_emu10k1_look_for_ctl(emu, &id);
  820. if (ctl)
  821. snd_ctl_remove(card, ctl->kcontrol);
  822. up_write(&card->controls_rwsem);
  823. }
  824. return 0;
  825. }
  826. static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
  827. struct snd_emu10k1_fx8010_code *icode)
  828. {
  829. unsigned int i = 0, j;
  830. unsigned int total = 0;
  831. struct snd_emu10k1_fx8010_control_gpr *gctl;
  832. struct snd_emu10k1_fx8010_ctl *ctl;
  833. struct snd_ctl_elem_id *id;
  834. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  835. if (! gctl)
  836. return -ENOMEM;
  837. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  838. total++;
  839. if (icode->gpr_list_controls &&
  840. i < icode->gpr_list_control_count) {
  841. memset(gctl, 0, sizeof(*gctl));
  842. id = &ctl->kcontrol->id;
  843. gctl->id.iface = id->iface;
  844. strlcpy(gctl->id.name, id->name, sizeof(gctl->id.name));
  845. gctl->id.index = id->index;
  846. gctl->id.device = id->device;
  847. gctl->id.subdevice = id->subdevice;
  848. gctl->vcount = ctl->vcount;
  849. gctl->count = ctl->count;
  850. for (j = 0; j < 32; j++) {
  851. gctl->gpr[j] = ctl->gpr[j];
  852. gctl->value[j] = ctl->value[j];
  853. }
  854. gctl->min = ctl->min;
  855. gctl->max = ctl->max;
  856. gctl->translation = ctl->translation;
  857. if (copy_gctl_to_user(emu, icode->gpr_list_controls,
  858. gctl, i)) {
  859. kfree(gctl);
  860. return -EFAULT;
  861. }
  862. i++;
  863. }
  864. }
  865. icode->gpr_list_control_total = total;
  866. kfree(gctl);
  867. return 0;
  868. }
  869. static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
  870. struct snd_emu10k1_fx8010_code *icode)
  871. {
  872. int err = 0;
  873. mutex_lock(&emu->fx8010.lock);
  874. if ((err = snd_emu10k1_verify_controls(emu, icode)) < 0)
  875. goto __error;
  876. strlcpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
  877. /* stop FX processor - this may be dangerous, but it's better to miss
  878. some samples than generate wrong ones - [jk] */
  879. if (emu->audigy)
  880. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  881. else
  882. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  883. /* ok, do the main job */
  884. if ((err = snd_emu10k1_del_controls(emu, icode)) < 0 ||
  885. (err = snd_emu10k1_gpr_poke(emu, icode)) < 0 ||
  886. (err = snd_emu10k1_tram_poke(emu, icode)) < 0 ||
  887. (err = snd_emu10k1_code_poke(emu, icode)) < 0 ||
  888. (err = snd_emu10k1_add_controls(emu, icode)) < 0)
  889. goto __error;
  890. /* start FX processor when the DSP code is updated */
  891. if (emu->audigy)
  892. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  893. else
  894. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  895. __error:
  896. mutex_unlock(&emu->fx8010.lock);
  897. return err;
  898. }
  899. static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
  900. struct snd_emu10k1_fx8010_code *icode)
  901. {
  902. int err;
  903. mutex_lock(&emu->fx8010.lock);
  904. strlcpy(icode->name, emu->fx8010.name, sizeof(icode->name));
  905. /* ok, do the main job */
  906. err = snd_emu10k1_gpr_peek(emu, icode);
  907. if (err >= 0)
  908. err = snd_emu10k1_tram_peek(emu, icode);
  909. if (err >= 0)
  910. err = snd_emu10k1_code_peek(emu, icode);
  911. if (err >= 0)
  912. err = snd_emu10k1_list_controls(emu, icode);
  913. mutex_unlock(&emu->fx8010.lock);
  914. return err;
  915. }
  916. static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
  917. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  918. {
  919. unsigned int i;
  920. int err = 0;
  921. struct snd_emu10k1_fx8010_pcm *pcm;
  922. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  923. return -EINVAL;
  924. if (ipcm->channels > 32)
  925. return -EINVAL;
  926. pcm = &emu->fx8010.pcm[ipcm->substream];
  927. mutex_lock(&emu->fx8010.lock);
  928. spin_lock_irq(&emu->reg_lock);
  929. if (pcm->opened) {
  930. err = -EBUSY;
  931. goto __error;
  932. }
  933. if (ipcm->channels == 0) { /* remove */
  934. pcm->valid = 0;
  935. } else {
  936. /* FIXME: we need to add universal code to the PCM transfer routine */
  937. if (ipcm->channels != 2) {
  938. err = -EINVAL;
  939. goto __error;
  940. }
  941. pcm->valid = 1;
  942. pcm->opened = 0;
  943. pcm->channels = ipcm->channels;
  944. pcm->tram_start = ipcm->tram_start;
  945. pcm->buffer_size = ipcm->buffer_size;
  946. pcm->gpr_size = ipcm->gpr_size;
  947. pcm->gpr_count = ipcm->gpr_count;
  948. pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
  949. pcm->gpr_ptr = ipcm->gpr_ptr;
  950. pcm->gpr_trigger = ipcm->gpr_trigger;
  951. pcm->gpr_running = ipcm->gpr_running;
  952. for (i = 0; i < pcm->channels; i++)
  953. pcm->etram[i] = ipcm->etram[i];
  954. }
  955. __error:
  956. spin_unlock_irq(&emu->reg_lock);
  957. mutex_unlock(&emu->fx8010.lock);
  958. return err;
  959. }
  960. static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
  961. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  962. {
  963. unsigned int i;
  964. int err = 0;
  965. struct snd_emu10k1_fx8010_pcm *pcm;
  966. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  967. return -EINVAL;
  968. pcm = &emu->fx8010.pcm[ipcm->substream];
  969. mutex_lock(&emu->fx8010.lock);
  970. spin_lock_irq(&emu->reg_lock);
  971. ipcm->channels = pcm->channels;
  972. ipcm->tram_start = pcm->tram_start;
  973. ipcm->buffer_size = pcm->buffer_size;
  974. ipcm->gpr_size = pcm->gpr_size;
  975. ipcm->gpr_ptr = pcm->gpr_ptr;
  976. ipcm->gpr_count = pcm->gpr_count;
  977. ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
  978. ipcm->gpr_trigger = pcm->gpr_trigger;
  979. ipcm->gpr_running = pcm->gpr_running;
  980. for (i = 0; i < pcm->channels; i++)
  981. ipcm->etram[i] = pcm->etram[i];
  982. ipcm->res1 = ipcm->res2 = 0;
  983. ipcm->pad = 0;
  984. spin_unlock_irq(&emu->reg_lock);
  985. mutex_unlock(&emu->fx8010.lock);
  986. return err;
  987. }
  988. #define SND_EMU10K1_GPR_CONTROLS 44
  989. #define SND_EMU10K1_INPUTS 12
  990. #define SND_EMU10K1_PLAYBACK_CHANNELS 8
  991. #define SND_EMU10K1_CAPTURE_CHANNELS 4
  992. static void __devinit
  993. snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  994. const char *name, int gpr, int defval)
  995. {
  996. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  997. strcpy(ctl->id.name, name);
  998. ctl->vcount = ctl->count = 1;
  999. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1000. if (high_res_gpr_volume) {
  1001. ctl->min = 0;
  1002. ctl->max = 0x7fffffff;
  1003. ctl->tlv = snd_emu10k1_db_linear;
  1004. ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
  1005. } else {
  1006. ctl->min = 0;
  1007. ctl->max = 100;
  1008. ctl->tlv = snd_emu10k1_db_scale1;
  1009. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1010. }
  1011. }
  1012. static void __devinit
  1013. snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1014. const char *name, int gpr, int defval)
  1015. {
  1016. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1017. strcpy(ctl->id.name, name);
  1018. ctl->vcount = ctl->count = 2;
  1019. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1020. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1021. if (high_res_gpr_volume) {
  1022. ctl->min = 0;
  1023. ctl->max = 0x7fffffff;
  1024. ctl->tlv = snd_emu10k1_db_linear;
  1025. ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
  1026. } else {
  1027. ctl->min = 0;
  1028. ctl->max = 100;
  1029. ctl->tlv = snd_emu10k1_db_scale1;
  1030. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1031. }
  1032. }
  1033. static void __devinit
  1034. snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1035. const char *name, int gpr, int defval)
  1036. {
  1037. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1038. strcpy(ctl->id.name, name);
  1039. ctl->vcount = ctl->count = 1;
  1040. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1041. ctl->min = 0;
  1042. ctl->max = 1;
  1043. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1044. }
  1045. static void __devinit
  1046. snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1047. const char *name, int gpr, int defval)
  1048. {
  1049. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1050. strcpy(ctl->id.name, name);
  1051. ctl->vcount = ctl->count = 2;
  1052. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1053. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1054. ctl->min = 0;
  1055. ctl->max = 1;
  1056. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1057. }
  1058. /*
  1059. * Used for emu1010 - conversion from 32-bit capture inputs from HANA
  1060. * to 2 x 16-bit registers in audigy - their values are read via DMA.
  1061. * Conversion is performed by Audigy DSP instructions of FX8010.
  1062. */
  1063. static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
  1064. struct snd_emu10k1_fx8010_code *icode,
  1065. u32 *ptr, int tmp, int bit_shifter16,
  1066. int reg_in, int reg_out)
  1067. {
  1068. A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000);
  1069. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000);
  1070. A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2));
  1071. A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000);
  1072. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000);
  1073. A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000);
  1074. A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2));
  1075. A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000);
  1076. return 1;
  1077. }
  1078. /*
  1079. * initial DSP configuration for Audigy
  1080. */
  1081. static int __devinit _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
  1082. {
  1083. int err, i, z, gpr, nctl;
  1084. int bit_shifter16;
  1085. const int playback = 10;
  1086. const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */
  1087. const int stereo_mix = capture + 2;
  1088. const int tmp = 0x88;
  1089. u32 ptr;
  1090. struct snd_emu10k1_fx8010_code *icode = NULL;
  1091. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1092. u32 *gpr_map;
  1093. mm_segment_t seg;
  1094. if ((icode = kzalloc(sizeof(*icode), GFP_KERNEL)) == NULL ||
  1095. (icode->gpr_map = (u_int32_t __user *)
  1096. kcalloc(512 + 256 + 256 + 2 * 1024, sizeof(u_int32_t),
  1097. GFP_KERNEL)) == NULL ||
  1098. (controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1099. sizeof(*controls), GFP_KERNEL)) == NULL) {
  1100. err = -ENOMEM;
  1101. goto __err;
  1102. }
  1103. gpr_map = (u32 __force *)icode->gpr_map;
  1104. icode->tram_data_map = icode->gpr_map + 512;
  1105. icode->tram_addr_map = icode->tram_data_map + 256;
  1106. icode->code = icode->tram_addr_map + 256;
  1107. /* clear free GPRs */
  1108. for (i = 0; i < 512; i++)
  1109. set_bit(i, icode->gpr_valid);
  1110. /* clear TRAM data & address lines */
  1111. for (i = 0; i < 256; i++)
  1112. set_bit(i, icode->tram_valid);
  1113. strcpy(icode->name, "Audigy DSP code for ALSA");
  1114. ptr = 0;
  1115. nctl = 0;
  1116. gpr = stereo_mix + 10;
  1117. gpr_map[gpr++] = 0x00007fff;
  1118. gpr_map[gpr++] = 0x00008000;
  1119. gpr_map[gpr++] = 0x0000ffff;
  1120. bit_shifter16 = gpr;
  1121. /* stop FX processor */
  1122. snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
  1123. #if 1
  1124. /* PCM front Playback Volume (independent from stereo mix)
  1125. * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
  1126. * where gpr contains attenuation from corresponding mixer control
  1127. * (snd_emu10k1_init_stereo_control)
  1128. */
  1129. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
  1130. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
  1131. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
  1132. gpr += 2;
  1133. /* PCM Surround Playback (independent from stereo mix) */
  1134. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
  1135. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
  1136. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
  1137. gpr += 2;
  1138. /* PCM Side Playback (independent from stereo mix) */
  1139. if (emu->card_capabilities->spk71) {
  1140. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
  1141. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
  1142. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
  1143. gpr += 2;
  1144. }
  1145. /* PCM Center Playback (independent from stereo mix) */
  1146. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
  1147. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
  1148. gpr++;
  1149. /* PCM LFE Playback (independent from stereo mix) */
  1150. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
  1151. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
  1152. gpr++;
  1153. /*
  1154. * Stereo Mix
  1155. */
  1156. /* Wave (PCM) Playback Volume (will be renamed later) */
  1157. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1158. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1159. snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
  1160. gpr += 2;
  1161. /* Synth Playback */
  1162. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1163. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1164. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
  1165. gpr += 2;
  1166. /* Wave (PCM) Capture */
  1167. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1168. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1169. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
  1170. gpr += 2;
  1171. /* Synth Capture */
  1172. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1173. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1174. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
  1175. gpr += 2;
  1176. /*
  1177. * inputs
  1178. */
  1179. #define A_ADD_VOLUME_IN(var,vol,input) \
  1180. A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
  1181. /* emu1212 DSP 0 and DSP 1 Capture */
  1182. if (emu->card_capabilities->emu_model) {
  1183. if (emu->card_capabilities->ca0108_chip) {
  1184. /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */
  1185. A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);
  1186. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp));
  1187. A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001);
  1188. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp));
  1189. } else {
  1190. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));
  1191. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));
  1192. }
  1193. snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
  1194. gpr += 2;
  1195. }
  1196. /* AC'97 Playback Volume - used only for mic (renamed later) */
  1197. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
  1198. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
  1199. snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
  1200. gpr += 2;
  1201. /* AC'97 Capture Volume - used only for mic */
  1202. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
  1203. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
  1204. snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
  1205. gpr += 2;
  1206. /* mic capture buffer */
  1207. A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
  1208. /* Audigy CD Playback Volume */
  1209. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
  1210. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1211. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1212. emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
  1213. gpr, 0);
  1214. gpr += 2;
  1215. /* Audigy CD Capture Volume */
  1216. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
  1217. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1218. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1219. emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
  1220. gpr, 0);
  1221. gpr += 2;
  1222. /* Optical SPDIF Playback Volume */
  1223. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
  1224. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1225. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
  1226. gpr += 2;
  1227. /* Optical SPDIF Capture Volume */
  1228. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
  1229. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1230. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
  1231. gpr += 2;
  1232. /* Line2 Playback Volume */
  1233. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
  1234. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
  1235. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1236. emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
  1237. gpr, 0);
  1238. gpr += 2;
  1239. /* Line2 Capture Volume */
  1240. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
  1241. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
  1242. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1243. emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
  1244. gpr, 0);
  1245. gpr += 2;
  1246. /* Philips ADC Playback Volume */
  1247. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
  1248. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
  1249. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
  1250. gpr += 2;
  1251. /* Philips ADC Capture Volume */
  1252. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
  1253. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
  1254. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
  1255. gpr += 2;
  1256. /* Aux2 Playback Volume */
  1257. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
  1258. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
  1259. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1260. emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
  1261. gpr, 0);
  1262. gpr += 2;
  1263. /* Aux2 Capture Volume */
  1264. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
  1265. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
  1266. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1267. emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
  1268. gpr, 0);
  1269. gpr += 2;
  1270. /* Stereo Mix Front Playback Volume */
  1271. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
  1272. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1273. snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
  1274. gpr += 2;
  1275. /* Stereo Mix Surround Playback */
  1276. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
  1277. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1278. snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
  1279. gpr += 2;
  1280. /* Stereo Mix Center Playback */
  1281. /* Center = sub = Left/2 + Right/2 */
  1282. A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
  1283. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
  1284. snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
  1285. gpr++;
  1286. /* Stereo Mix LFE Playback */
  1287. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
  1288. snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
  1289. gpr++;
  1290. if (emu->card_capabilities->spk71) {
  1291. /* Stereo Mix Side Playback */
  1292. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
  1293. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1294. snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
  1295. gpr += 2;
  1296. }
  1297. /*
  1298. * outputs
  1299. */
  1300. #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
  1301. #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
  1302. {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
  1303. #define _A_SWITCH(icode, ptr, dst, src, sw) \
  1304. A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
  1305. #define A_SWITCH(icode, ptr, dst, src, sw) \
  1306. _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
  1307. #define _A_SWITCH_NEG(icode, ptr, dst, src) \
  1308. A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
  1309. #define A_SWITCH_NEG(icode, ptr, dst, src) \
  1310. _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
  1311. /*
  1312. * Process tone control
  1313. */
  1314. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */
  1315. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */
  1316. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */
  1317. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */
  1318. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */
  1319. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */
  1320. if (emu->card_capabilities->spk71) {
  1321. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */
  1322. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */
  1323. }
  1324. ctl = &controls[nctl + 0];
  1325. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1326. strcpy(ctl->id.name, "Tone Control - Bass");
  1327. ctl->vcount = 2;
  1328. ctl->count = 10;
  1329. ctl->min = 0;
  1330. ctl->max = 40;
  1331. ctl->value[0] = ctl->value[1] = 20;
  1332. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1333. ctl = &controls[nctl + 1];
  1334. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1335. strcpy(ctl->id.name, "Tone Control - Treble");
  1336. ctl->vcount = 2;
  1337. ctl->count = 10;
  1338. ctl->min = 0;
  1339. ctl->max = 40;
  1340. ctl->value[0] = ctl->value[1] = 20;
  1341. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1342. #define BASS_GPR 0x8c
  1343. #define TREBLE_GPR 0x96
  1344. for (z = 0; z < 5; z++) {
  1345. int j;
  1346. for (j = 0; j < 2; j++) {
  1347. controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1348. controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1349. }
  1350. }
  1351. for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
  1352. int j, k, l, d;
  1353. for (j = 0; j < 2; j++) { /* left/right */
  1354. k = 0xb0 + (z * 8) + (j * 4);
  1355. l = 0xe0 + (z * 8) + (j * 4);
  1356. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  1357. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));
  1358. A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));
  1359. A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));
  1360. A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));
  1361. A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));
  1362. A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
  1363. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));
  1364. A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));
  1365. A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));
  1366. A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));
  1367. A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));
  1368. A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
  1369. A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
  1370. if (z == 2) /* center */
  1371. break;
  1372. }
  1373. }
  1374. nctl += 2;
  1375. #undef BASS_GPR
  1376. #undef TREBLE_GPR
  1377. for (z = 0; z < 8; z++) {
  1378. A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  1379. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  1380. A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  1381. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1382. }
  1383. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
  1384. gpr += 2;
  1385. /* Master volume (will be renamed later) */
  1386. A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS));
  1387. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS));
  1388. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS));
  1389. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS));
  1390. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS));
  1391. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS));
  1392. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS));
  1393. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS));
  1394. snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
  1395. gpr += 2;
  1396. /* analog speakers */
  1397. A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1398. A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1399. A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1400. A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1401. if (emu->card_capabilities->spk71)
  1402. A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1403. /* headphone */
  1404. A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1405. /* digital outputs */
  1406. /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */
  1407. if (emu->card_capabilities->emu_model) {
  1408. /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
  1409. snd_printk(KERN_INFO "EMU outputs on\n");
  1410. for (z = 0; z < 8; z++) {
  1411. if (emu->card_capabilities->ca0108_chip) {
  1412. A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
  1413. } else {
  1414. A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
  1415. }
  1416. }
  1417. }
  1418. /* IEC958 Optical Raw Playback Switch */
  1419. gpr_map[gpr++] = 0;
  1420. gpr_map[gpr++] = 0x1008;
  1421. gpr_map[gpr++] = 0xffff0000;
  1422. for (z = 0; z < 2; z++) {
  1423. A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
  1424. A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
  1425. A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
  1426. A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
  1427. A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
  1428. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  1429. A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  1430. if ((z==1) && (emu->card_capabilities->spdif_bug)) {
  1431. /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
  1432. snd_printk(KERN_INFO "Installing spdif_bug patch: %s\n", emu->card_capabilities->name);
  1433. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
  1434. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1435. } else {
  1436. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1437. }
  1438. }
  1439. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  1440. gpr += 2;
  1441. A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1442. A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1443. A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1444. /* ADC buffer */
  1445. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  1446. A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1447. #else
  1448. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
  1449. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
  1450. #endif
  1451. if (emu->card_capabilities->emu_model) {
  1452. if (emu->card_capabilities->ca0108_chip) {
  1453. snd_printk(KERN_INFO "EMU2 inputs on\n");
  1454. for (z = 0; z < 0x10; z++) {
  1455. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
  1456. bit_shifter16,
  1457. A3_EMU32IN(z),
  1458. A_FXBUS2(z*2) );
  1459. }
  1460. } else {
  1461. snd_printk(KERN_INFO "EMU inputs on\n");
  1462. /* Capture 16 (originally 8) channels of S32_LE sound */
  1463. /*
  1464. printk(KERN_DEBUG "emufx.c: gpr=0x%x, tmp=0x%x\n",
  1465. gpr, tmp);
  1466. */
  1467. /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */
  1468. /* A_P16VIN(0) is delayed by one sample,
  1469. * so all other A_P16VIN channels will need to also be delayed
  1470. */
  1471. /* Left ADC in. 1 of 2 */
  1472. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
  1473. /* Right ADC in 1 of 2 */
  1474. gpr_map[gpr++] = 0x00000000;
  1475. /* Delaying by one sample: instead of copying the input
  1476. * value A_P16VIN to output A_FXBUS2 as in the first channel,
  1477. * we use an auxiliary register, delaying the value by one
  1478. * sample
  1479. */
  1480. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );
  1481. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
  1482. gpr_map[gpr++] = 0x00000000;
  1483. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) );
  1484. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000);
  1485. gpr_map[gpr++] = 0x00000000;
  1486. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) );
  1487. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000);
  1488. /* For 96kHz mode */
  1489. /* Left ADC in. 2 of 2 */
  1490. gpr_map[gpr++] = 0x00000000;
  1491. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) );
  1492. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000);
  1493. /* Right ADC in 2 of 2 */
  1494. gpr_map[gpr++] = 0x00000000;
  1495. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) );
  1496. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000);
  1497. gpr_map[gpr++] = 0x00000000;
  1498. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) );
  1499. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000);
  1500. gpr_map[gpr++] = 0x00000000;
  1501. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );
  1502. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);
  1503. /* Pavel Hofman - we still have voices, A_FXBUS2s, and
  1504. * A_P16VINs available -
  1505. * let's add 8 more capture channels - total of 16
  1506. */
  1507. gpr_map[gpr++] = 0x00000000;
  1508. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1509. bit_shifter16,
  1510. A_GPR(gpr - 1),
  1511. A_FXBUS2(0x10));
  1512. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),
  1513. A_C_00000000, A_C_00000000);
  1514. gpr_map[gpr++] = 0x00000000;
  1515. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1516. bit_shifter16,
  1517. A_GPR(gpr - 1),
  1518. A_FXBUS2(0x12));
  1519. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),
  1520. A_C_00000000, A_C_00000000);
  1521. gpr_map[gpr++] = 0x00000000;
  1522. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1523. bit_shifter16,
  1524. A_GPR(gpr - 1),
  1525. A_FXBUS2(0x14));
  1526. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),
  1527. A_C_00000000, A_C_00000000);
  1528. gpr_map[gpr++] = 0x00000000;
  1529. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1530. bit_shifter16,
  1531. A_GPR(gpr - 1),
  1532. A_FXBUS2(0x16));
  1533. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),
  1534. A_C_00000000, A_C_00000000);
  1535. gpr_map[gpr++] = 0x00000000;
  1536. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1537. bit_shifter16,
  1538. A_GPR(gpr - 1),
  1539. A_FXBUS2(0x18));
  1540. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),
  1541. A_C_00000000, A_C_00000000);
  1542. gpr_map[gpr++] = 0x00000000;
  1543. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1544. bit_shifter16,
  1545. A_GPR(gpr - 1),
  1546. A_FXBUS2(0x1a));
  1547. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),
  1548. A_C_00000000, A_C_00000000);
  1549. gpr_map[gpr++] = 0x00000000;
  1550. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1551. bit_shifter16,
  1552. A_GPR(gpr - 1),
  1553. A_FXBUS2(0x1c));
  1554. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),
  1555. A_C_00000000, A_C_00000000);
  1556. gpr_map[gpr++] = 0x00000000;
  1557. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1558. bit_shifter16,
  1559. A_GPR(gpr - 1),
  1560. A_FXBUS2(0x1e));
  1561. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),
  1562. A_C_00000000, A_C_00000000);
  1563. }
  1564. #if 0
  1565. for (z = 4; z < 8; z++) {
  1566. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1567. }
  1568. for (z = 0xc; z < 0x10; z++) {
  1569. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1570. }
  1571. #endif
  1572. } else {
  1573. /* EFX capture - capture the 16 EXTINs */
  1574. /* Capture 16 channels of S16_LE sound */
  1575. for (z = 0; z < 16; z++) {
  1576. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
  1577. }
  1578. }
  1579. #endif /* JCD test */
  1580. /*
  1581. * ok, set up done..
  1582. */
  1583. if (gpr > tmp) {
  1584. snd_BUG();
  1585. err = -EIO;
  1586. goto __err;
  1587. }
  1588. /* clear remaining instruction memory */
  1589. while (ptr < 0x400)
  1590. A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
  1591. seg = snd_enter_user();
  1592. icode->gpr_add_control_count = nctl;
  1593. icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
  1594. emu->support_tlv = 1; /* support TLV */
  1595. err = snd_emu10k1_icode_poke(emu, icode);
  1596. emu->support_tlv = 0; /* clear again */
  1597. snd_leave_user(seg);
  1598. __err:
  1599. kfree(controls);
  1600. if (icode != NULL) {
  1601. kfree((void __force *)icode->gpr_map);
  1602. kfree(icode);
  1603. }
  1604. return err;
  1605. }
  1606. /*
  1607. * initial DSP configuration for Emu10k1
  1608. */
  1609. /* when volume = max, then copy only to avoid volume modification */
  1610. /* with iMAC0 (negative values) */
  1611. static void __devinit _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1612. {
  1613. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1614. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1615. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001);
  1616. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1617. }
  1618. static void __devinit _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1619. {
  1620. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1621. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1622. OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001);
  1623. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1624. OP(icode, ptr, iMAC0, dst, dst, src, vol);
  1625. }
  1626. static void __devinit _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1627. {
  1628. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1629. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1630. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1631. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1632. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1633. }
  1634. #define VOLUME(icode, ptr, dst, src, vol) \
  1635. _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1636. #define VOLUME_IN(icode, ptr, dst, src, vol) \
  1637. _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1638. #define VOLUME_ADD(icode, ptr, dst, src, vol) \
  1639. _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1640. #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
  1641. _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1642. #define VOLUME_OUT(icode, ptr, dst, src, vol) \
  1643. _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
  1644. #define _SWITCH(icode, ptr, dst, src, sw) \
  1645. OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
  1646. #define SWITCH(icode, ptr, dst, src, sw) \
  1647. _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
  1648. #define SWITCH_IN(icode, ptr, dst, src, sw) \
  1649. _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
  1650. #define _SWITCH_NEG(icode, ptr, dst, src) \
  1651. OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
  1652. #define SWITCH_NEG(icode, ptr, dst, src) \
  1653. _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
  1654. static int __devinit _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  1655. {
  1656. int err, i, z, gpr, tmp, playback, capture;
  1657. u32 ptr;
  1658. struct snd_emu10k1_fx8010_code *icode;
  1659. struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
  1660. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1661. u32 *gpr_map;
  1662. mm_segment_t seg;
  1663. if ((icode = kzalloc(sizeof(*icode), GFP_KERNEL)) == NULL)
  1664. return -ENOMEM;
  1665. if ((icode->gpr_map = (u_int32_t __user *)
  1666. kcalloc(256 + 160 + 160 + 2 * 512, sizeof(u_int32_t),
  1667. GFP_KERNEL)) == NULL ||
  1668. (controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1669. sizeof(struct snd_emu10k1_fx8010_control_gpr),
  1670. GFP_KERNEL)) == NULL ||
  1671. (ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL)) == NULL) {
  1672. err = -ENOMEM;
  1673. goto __err;
  1674. }
  1675. gpr_map = (u32 __force *)icode->gpr_map;
  1676. icode->tram_data_map = icode->gpr_map + 256;
  1677. icode->tram_addr_map = icode->tram_data_map + 160;
  1678. icode->code = icode->tram_addr_map + 160;
  1679. /* clear free GPRs */
  1680. for (i = 0; i < 256; i++)
  1681. set_bit(i, icode->gpr_valid);
  1682. /* clear TRAM data & address lines */
  1683. for (i = 0; i < 160; i++)
  1684. set_bit(i, icode->tram_valid);
  1685. strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
  1686. ptr = 0; i = 0;
  1687. /* we have 12 inputs */
  1688. playback = SND_EMU10K1_INPUTS;
  1689. /* we have 6 playback channels and tone control doubles */
  1690. capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);
  1691. gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
  1692. tmp = 0x88; /* we need 4 temporary GPR */
  1693. /* from 0x8c to 0xff is the area for tone control */
  1694. /* stop FX processor */
  1695. snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);
  1696. /*
  1697. * Process FX Buses
  1698. */
  1699. OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);
  1700. OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);
  1701. OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);
  1702. OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);
  1703. OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);
  1704. OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);
  1705. OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);
  1706. OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);
  1707. OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
  1708. OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
  1709. OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);
  1710. OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);
  1711. /* Raw S/PDIF PCM */
  1712. ipcm->substream = 0;
  1713. ipcm->channels = 2;
  1714. ipcm->tram_start = 0;
  1715. ipcm->buffer_size = (64 * 1024) / 2;
  1716. ipcm->gpr_size = gpr++;
  1717. ipcm->gpr_ptr = gpr++;
  1718. ipcm->gpr_count = gpr++;
  1719. ipcm->gpr_tmpcount = gpr++;
  1720. ipcm->gpr_trigger = gpr++;
  1721. ipcm->gpr_running = gpr++;
  1722. ipcm->etram[0] = 0;
  1723. ipcm->etram[1] = 1;
  1724. gpr_map[gpr + 0] = 0xfffff000;
  1725. gpr_map[gpr + 1] = 0xffff0000;
  1726. gpr_map[gpr + 2] = 0x70000000;
  1727. gpr_map[gpr + 3] = 0x00000007;
  1728. gpr_map[gpr + 4] = 0x001f << 11;
  1729. gpr_map[gpr + 5] = 0x001c << 11;
  1730. gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
  1731. gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
  1732. gpr_map[gpr + 8] = 0x2000000 + (2<<11);
  1733. gpr_map[gpr + 9] = 0x4000000 + (2<<11);
  1734. gpr_map[gpr + 10] = 1<<11;
  1735. gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
  1736. gpr_map[gpr + 12] = 0;
  1737. /* if the trigger flag is not set, skip */
  1738. /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
  1739. /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
  1740. /* if the running flag is set, we're running */
  1741. /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
  1742. /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
  1743. /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
  1744. /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
  1745. /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
  1746. /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
  1747. /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
  1748. /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
  1749. /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
  1750. /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
  1751. /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
  1752. /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
  1753. /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1754. /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1755. /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1756. /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
  1757. /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
  1758. /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1759. /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1760. /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1761. /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
  1762. /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
  1763. /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
  1764. /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
  1765. /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
  1766. /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
  1767. /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
  1768. /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1769. /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
  1770. /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
  1771. /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
  1772. /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
  1773. /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
  1774. /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
  1775. /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
  1776. /* 24: */
  1777. gpr += 13;
  1778. /* Wave Playback Volume */
  1779. for (z = 0; z < 2; z++)
  1780. VOLUME(icode, &ptr, playback + z, z, gpr + z);
  1781. snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
  1782. gpr += 2;
  1783. /* Wave Surround Playback Volume */
  1784. for (z = 0; z < 2; z++)
  1785. VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
  1786. snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
  1787. gpr += 2;
  1788. /* Wave Center/LFE Playback Volume */
  1789. OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
  1790. OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);
  1791. VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
  1792. snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
  1793. VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
  1794. snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
  1795. /* Wave Capture Volume + Switch */
  1796. for (z = 0; z < 2; z++) {
  1797. SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
  1798. VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1799. }
  1800. snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
  1801. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
  1802. gpr += 4;
  1803. /* Synth Playback Volume */
  1804. for (z = 0; z < 2; z++)
  1805. VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
  1806. snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
  1807. gpr += 2;
  1808. /* Synth Capture Volume + Switch */
  1809. for (z = 0; z < 2; z++) {
  1810. SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
  1811. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1812. }
  1813. snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
  1814. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
  1815. gpr += 4;
  1816. /* Surround Digital Playback Volume (renamed later without Digital) */
  1817. for (z = 0; z < 2; z++)
  1818. VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
  1819. snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
  1820. gpr += 2;
  1821. /* Surround Capture Volume + Switch */
  1822. for (z = 0; z < 2; z++) {
  1823. SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
  1824. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1825. }
  1826. snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
  1827. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
  1828. gpr += 4;
  1829. /* Center Playback Volume (renamed later without Digital) */
  1830. VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
  1831. snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
  1832. /* LFE Playback Volume + Switch (renamed later without Digital) */
  1833. VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
  1834. snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
  1835. /* Front Playback Volume */
  1836. for (z = 0; z < 2; z++)
  1837. VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
  1838. snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
  1839. gpr += 2;
  1840. /* Front Capture Volume + Switch */
  1841. for (z = 0; z < 2; z++) {
  1842. SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
  1843. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1844. }
  1845. snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
  1846. snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
  1847. gpr += 3;
  1848. /*
  1849. * Process inputs
  1850. */
  1851. if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
  1852. /* AC'97 Playback Volume */
  1853. VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
  1854. VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
  1855. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
  1856. /* AC'97 Capture Volume */
  1857. VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
  1858. VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
  1859. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
  1860. }
  1861. if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
  1862. /* IEC958 TTL Playback Volume */
  1863. for (z = 0; z < 2; z++)
  1864. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
  1865. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
  1866. gpr += 2;
  1867. /* IEC958 TTL Capture Volume + Switch */
  1868. for (z = 0; z < 2; z++) {
  1869. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
  1870. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1871. }
  1872. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
  1873. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
  1874. gpr += 4;
  1875. }
  1876. if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
  1877. /* Zoom Video Playback Volume */
  1878. for (z = 0; z < 2; z++)
  1879. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
  1880. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
  1881. gpr += 2;
  1882. /* Zoom Video Capture Volume + Switch */
  1883. for (z = 0; z < 2; z++) {
  1884. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
  1885. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1886. }
  1887. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
  1888. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
  1889. gpr += 4;
  1890. }
  1891. if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
  1892. /* IEC958 Optical Playback Volume */
  1893. for (z = 0; z < 2; z++)
  1894. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
  1895. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
  1896. gpr += 2;
  1897. /* IEC958 Optical Capture Volume */
  1898. for (z = 0; z < 2; z++) {
  1899. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
  1900. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1901. }
  1902. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
  1903. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
  1904. gpr += 4;
  1905. }
  1906. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
  1907. /* Line LiveDrive Playback Volume */
  1908. for (z = 0; z < 2; z++)
  1909. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
  1910. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
  1911. gpr += 2;
  1912. /* Line LiveDrive Capture Volume + Switch */
  1913. for (z = 0; z < 2; z++) {
  1914. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
  1915. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1916. }
  1917. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
  1918. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
  1919. gpr += 4;
  1920. }
  1921. if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
  1922. /* IEC958 Coax Playback Volume */
  1923. for (z = 0; z < 2; z++)
  1924. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
  1925. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
  1926. gpr += 2;
  1927. /* IEC958 Coax Capture Volume + Switch */
  1928. for (z = 0; z < 2; z++) {
  1929. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
  1930. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1931. }
  1932. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
  1933. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
  1934. gpr += 4;
  1935. }
  1936. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
  1937. /* Line LiveDrive Playback Volume */
  1938. for (z = 0; z < 2; z++)
  1939. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
  1940. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
  1941. controls[i-1].id.index = 1;
  1942. gpr += 2;
  1943. /* Line LiveDrive Capture Volume */
  1944. for (z = 0; z < 2; z++) {
  1945. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
  1946. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1947. }
  1948. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
  1949. controls[i-1].id.index = 1;
  1950. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
  1951. controls[i-1].id.index = 1;
  1952. gpr += 4;
  1953. }
  1954. /*
  1955. * Process tone control
  1956. */
  1957. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */
  1958. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */
  1959. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */
  1960. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */
  1961. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */
  1962. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */
  1963. ctl = &controls[i + 0];
  1964. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1965. strcpy(ctl->id.name, "Tone Control - Bass");
  1966. ctl->vcount = 2;
  1967. ctl->count = 10;
  1968. ctl->min = 0;
  1969. ctl->max = 40;
  1970. ctl->value[0] = ctl->value[1] = 20;
  1971. ctl->tlv = snd_emu10k1_bass_treble_db_scale;
  1972. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1973. ctl = &controls[i + 1];
  1974. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1975. strcpy(ctl->id.name, "Tone Control - Treble");
  1976. ctl->vcount = 2;
  1977. ctl->count = 10;
  1978. ctl->min = 0;
  1979. ctl->max = 40;
  1980. ctl->value[0] = ctl->value[1] = 20;
  1981. ctl->tlv = snd_emu10k1_bass_treble_db_scale;
  1982. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1983. #define BASS_GPR 0x8c
  1984. #define TREBLE_GPR 0x96
  1985. for (z = 0; z < 5; z++) {
  1986. int j;
  1987. for (j = 0; j < 2; j++) {
  1988. controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1989. controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1990. }
  1991. }
  1992. for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
  1993. int j, k, l, d;
  1994. for (j = 0; j < 2; j++) { /* left/right */
  1995. k = 0xa0 + (z * 8) + (j * 4);
  1996. l = 0xd0 + (z * 8) + (j * 4);
  1997. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  1998. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
  1999. OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
  2000. OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
  2001. OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
  2002. OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
  2003. OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
  2004. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
  2005. OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
  2006. OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
  2007. OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
  2008. OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
  2009. OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
  2010. OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
  2011. if (z == 2) /* center */
  2012. break;
  2013. }
  2014. }
  2015. i += 2;
  2016. #undef BASS_GPR
  2017. #undef TREBLE_GPR
  2018. for (z = 0; z < 6; z++) {
  2019. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  2020. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  2021. SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  2022. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2023. }
  2024. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
  2025. gpr += 2;
  2026. /*
  2027. * Process outputs
  2028. */
  2029. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
  2030. /* AC'97 Playback Volume */
  2031. for (z = 0; z < 2; z++)
  2032. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);
  2033. }
  2034. if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
  2035. /* IEC958 Optical Raw Playback Switch */
  2036. for (z = 0; z < 2; z++) {
  2037. SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
  2038. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  2039. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  2040. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2041. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  2042. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2043. #endif
  2044. }
  2045. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  2046. gpr += 2;
  2047. }
  2048. if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
  2049. /* Headphone Playback Volume */
  2050. for (z = 0; z < 2; z++) {
  2051. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);
  2052. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
  2053. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  2054. OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2055. VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
  2056. }
  2057. snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
  2058. controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
  2059. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
  2060. controls[i-1].id.index = 1;
  2061. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
  2062. controls[i-1].id.index = 1;
  2063. gpr += 4;
  2064. }
  2065. if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
  2066. for (z = 0; z < 2; z++)
  2067. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2068. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
  2069. for (z = 0; z < 2; z++)
  2070. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2071. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
  2072. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2073. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2074. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2075. #else
  2076. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2077. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2078. #endif
  2079. }
  2080. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
  2081. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2082. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2083. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2084. #else
  2085. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2086. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2087. #endif
  2088. }
  2089. #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
  2090. for (z = 0; z < 2; z++)
  2091. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
  2092. #endif
  2093. if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
  2094. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
  2095. /* EFX capture - capture the 16 EXTINS */
  2096. if (emu->card_capabilities->sblive51) {
  2097. /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER
  2098. * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
  2099. *
  2100. * Since only 14 of the 16 EXTINs are used, this is not a big problem.
  2101. * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture
  2102. * 0 and 3, then the rest of the EXTINs to the corresponding FX capture
  2103. * channel. Multitrack recorders will still see the center/lfe output signal
  2104. * on the second and third channels.
  2105. */
  2106. OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));
  2107. OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));
  2108. OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));
  2109. OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));
  2110. for (z = 4; z < 14; z++)
  2111. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2112. } else {
  2113. for (z = 0; z < 16; z++)
  2114. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2115. }
  2116. if (gpr > tmp) {
  2117. snd_BUG();
  2118. err = -EIO;
  2119. goto __err;
  2120. }
  2121. if (i > SND_EMU10K1_GPR_CONTROLS) {
  2122. snd_BUG();
  2123. err = -EIO;
  2124. goto __err;
  2125. }
  2126. /* clear remaining instruction memory */
  2127. while (ptr < 0x200)
  2128. OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
  2129. if ((err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size)) < 0)
  2130. goto __err;
  2131. seg = snd_enter_user();
  2132. icode->gpr_add_control_count = i;
  2133. icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
  2134. emu->support_tlv = 1; /* support TLV */
  2135. err = snd_emu10k1_icode_poke(emu, icode);
  2136. emu->support_tlv = 0; /* clear again */
  2137. snd_leave_user(seg);
  2138. if (err >= 0)
  2139. err = snd_emu10k1_ipcm_poke(emu, ipcm);
  2140. __err:
  2141. kfree(ipcm);
  2142. kfree(controls);
  2143. if (icode != NULL) {
  2144. kfree((void __force *)icode->gpr_map);
  2145. kfree(icode);
  2146. }
  2147. return err;
  2148. }
  2149. int __devinit snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  2150. {
  2151. spin_lock_init(&emu->fx8010.irq_lock);
  2152. INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
  2153. if (emu->audigy)
  2154. return _snd_emu10k1_audigy_init_efx(emu);
  2155. else
  2156. return _snd_emu10k1_init_efx(emu);
  2157. }
  2158. void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
  2159. {
  2160. /* stop processor */
  2161. if (emu->audigy)
  2162. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
  2163. else
  2164. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
  2165. }
  2166. #if 0 /* FIXME: who use them? */
  2167. int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
  2168. {
  2169. if (output < 0 || output >= 6)
  2170. return -EINVAL;
  2171. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
  2172. return 0;
  2173. }
  2174. int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
  2175. {
  2176. if (output < 0 || output >= 6)
  2177. return -EINVAL;
  2178. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
  2179. return 0;
  2180. }
  2181. #endif
  2182. int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
  2183. {
  2184. u8 size_reg = 0;
  2185. /* size is in samples */
  2186. if (size != 0) {
  2187. size = (size - 1) >> 13;
  2188. while (size) {
  2189. size >>= 1;
  2190. size_reg++;
  2191. }
  2192. size = 0x2000 << size_reg;
  2193. }
  2194. if ((emu->fx8010.etram_pages.bytes / 2) == size)
  2195. return 0;
  2196. spin_lock_irq(&emu->emu_lock);
  2197. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2198. spin_unlock_irq(&emu->emu_lock);
  2199. snd_emu10k1_ptr_write(emu, TCB, 0, 0);
  2200. snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
  2201. if (emu->fx8010.etram_pages.area != NULL) {
  2202. snd_dma_free_pages(&emu->fx8010.etram_pages);
  2203. emu->fx8010.etram_pages.area = NULL;
  2204. emu->fx8010.etram_pages.bytes = 0;
  2205. }
  2206. if (size > 0) {
  2207. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(emu->pci),
  2208. size * 2, &emu->fx8010.etram_pages) < 0)
  2209. return -ENOMEM;
  2210. memset(emu->fx8010.etram_pages.area, 0, size * 2);
  2211. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2212. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2213. spin_lock_irq(&emu->emu_lock);
  2214. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2215. spin_unlock_irq(&emu->emu_lock);
  2216. }
  2217. return 0;
  2218. }
  2219. static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
  2220. {
  2221. return 0;
  2222. }
  2223. static void copy_string(char *dst, char *src, char *null, int idx)
  2224. {
  2225. if (src == NULL)
  2226. sprintf(dst, "%s %02X", null, idx);
  2227. else
  2228. strcpy(dst, src);
  2229. }
  2230. static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
  2231. struct snd_emu10k1_fx8010_info *info)
  2232. {
  2233. char **fxbus, **extin, **extout;
  2234. unsigned short fxbus_mask, extin_mask, extout_mask;
  2235. int res;
  2236. info->internal_tram_size = emu->fx8010.itram_size;
  2237. info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
  2238. fxbus = fxbuses;
  2239. extin = emu->audigy ? audigy_ins : creative_ins;
  2240. extout = emu->audigy ? audigy_outs : creative_outs;
  2241. fxbus_mask = emu->fx8010.fxbus_mask;
  2242. extin_mask = emu->fx8010.extin_mask;
  2243. extout_mask = emu->fx8010.extout_mask;
  2244. for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
  2245. copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);
  2246. copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
  2247. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2248. }
  2249. for (res = 16; res < 32; res++, extout++)
  2250. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2251. info->gpr_controls = emu->fx8010.gpr_count;
  2252. }
  2253. static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
  2254. {
  2255. struct snd_emu10k1 *emu = hw->private_data;
  2256. struct snd_emu10k1_fx8010_info *info;
  2257. struct snd_emu10k1_fx8010_code *icode;
  2258. struct snd_emu10k1_fx8010_pcm_rec *ipcm;
  2259. unsigned int addr;
  2260. void __user *argp = (void __user *)arg;
  2261. int res;
  2262. switch (cmd) {
  2263. case SNDRV_EMU10K1_IOCTL_PVERSION:
  2264. emu->support_tlv = 1;
  2265. return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
  2266. case SNDRV_EMU10K1_IOCTL_INFO:
  2267. info = kmalloc(sizeof(*info), GFP_KERNEL);
  2268. if (!info)
  2269. return -ENOMEM;
  2270. snd_emu10k1_fx8010_info(emu, info);
  2271. if (copy_to_user(argp, info, sizeof(*info))) {
  2272. kfree(info);
  2273. return -EFAULT;
  2274. }
  2275. kfree(info);
  2276. return 0;
  2277. case SNDRV_EMU10K1_IOCTL_CODE_POKE:
  2278. if (!capable(CAP_SYS_ADMIN))
  2279. return -EPERM;
  2280. icode = memdup_user(argp, sizeof(*icode));
  2281. if (IS_ERR(icode))
  2282. return PTR_ERR(icode);
  2283. res = snd_emu10k1_icode_poke(emu, icode);
  2284. kfree(icode);
  2285. return res;
  2286. case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
  2287. icode = memdup_user(argp, sizeof(*icode));
  2288. if (IS_ERR(icode))
  2289. return PTR_ERR(icode);
  2290. res = snd_emu10k1_icode_peek(emu, icode);
  2291. if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
  2292. kfree(icode);
  2293. return -EFAULT;
  2294. }
  2295. kfree(icode);
  2296. return res;
  2297. case SNDRV_EMU10K1_IOCTL_PCM_POKE:
  2298. ipcm = memdup_user(argp, sizeof(*ipcm));
  2299. if (IS_ERR(ipcm))
  2300. return PTR_ERR(ipcm);
  2301. res = snd_emu10k1_ipcm_poke(emu, ipcm);
  2302. kfree(ipcm);
  2303. return res;
  2304. case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
  2305. ipcm = memdup_user(argp, sizeof(*ipcm));
  2306. if (IS_ERR(ipcm))
  2307. return PTR_ERR(ipcm);
  2308. res = snd_emu10k1_ipcm_peek(emu, ipcm);
  2309. if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
  2310. kfree(ipcm);
  2311. return -EFAULT;
  2312. }
  2313. kfree(ipcm);
  2314. return res;
  2315. case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
  2316. if (!capable(CAP_SYS_ADMIN))
  2317. return -EPERM;
  2318. if (get_user(addr, (unsigned int __user *)argp))
  2319. return -EFAULT;
  2320. mutex_lock(&emu->fx8010.lock);
  2321. res = snd_emu10k1_fx8010_tram_setup(emu, addr);
  2322. mutex_unlock(&emu->fx8010.lock);
  2323. return res;
  2324. case SNDRV_EMU10K1_IOCTL_STOP:
  2325. if (!capable(CAP_SYS_ADMIN))
  2326. return -EPERM;
  2327. if (emu->audigy)
  2328. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
  2329. else
  2330. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
  2331. return 0;
  2332. case SNDRV_EMU10K1_IOCTL_CONTINUE:
  2333. if (!capable(CAP_SYS_ADMIN))
  2334. return -EPERM;
  2335. if (emu->audigy)
  2336. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
  2337. else
  2338. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
  2339. return 0;
  2340. case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
  2341. if (!capable(CAP_SYS_ADMIN))
  2342. return -EPERM;
  2343. if (emu->audigy)
  2344. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
  2345. else
  2346. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
  2347. udelay(10);
  2348. if (emu->audigy)
  2349. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2350. else
  2351. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2352. return 0;
  2353. case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
  2354. if (!capable(CAP_SYS_ADMIN))
  2355. return -EPERM;
  2356. if (get_user(addr, (unsigned int __user *)argp))
  2357. return -EFAULT;
  2358. if (addr > 0x1ff)
  2359. return -EINVAL;
  2360. if (emu->audigy)
  2361. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr);
  2362. else
  2363. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr);
  2364. udelay(10);
  2365. if (emu->audigy)
  2366. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr);
  2367. else
  2368. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr);
  2369. return 0;
  2370. case SNDRV_EMU10K1_IOCTL_DBG_READ:
  2371. if (emu->audigy)
  2372. addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
  2373. else
  2374. addr = snd_emu10k1_ptr_read(emu, DBG, 0);
  2375. if (put_user(addr, (unsigned int __user *)argp))
  2376. return -EFAULT;
  2377. return 0;
  2378. }
  2379. return -ENOTTY;
  2380. }
  2381. static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
  2382. {
  2383. return 0;
  2384. }
  2385. int __devinit snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep)
  2386. {
  2387. struct snd_hwdep *hw;
  2388. int err;
  2389. if (rhwdep)
  2390. *rhwdep = NULL;
  2391. if ((err = snd_hwdep_new(emu->card, "FX8010", device, &hw)) < 0)
  2392. return err;
  2393. strcpy(hw->name, "EMU10K1 (FX8010)");
  2394. hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
  2395. hw->ops.open = snd_emu10k1_fx8010_open;
  2396. hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
  2397. hw->ops.release = snd_emu10k1_fx8010_release;
  2398. hw->private_data = emu;
  2399. if (rhwdep)
  2400. *rhwdep = hw;
  2401. return 0;
  2402. }
  2403. #ifdef CONFIG_PM
  2404. int __devinit snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
  2405. {
  2406. int len;
  2407. len = emu->audigy ? 0x200 : 0x100;
  2408. emu->saved_gpr = kmalloc(len * 4, GFP_KERNEL);
  2409. if (! emu->saved_gpr)
  2410. return -ENOMEM;
  2411. len = emu->audigy ? 0x100 : 0xa0;
  2412. emu->tram_val_saved = kmalloc(len * 4, GFP_KERNEL);
  2413. emu->tram_addr_saved = kmalloc(len * 4, GFP_KERNEL);
  2414. if (! emu->tram_val_saved || ! emu->tram_addr_saved)
  2415. return -ENOMEM;
  2416. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2417. emu->saved_icode = vmalloc(len * 4);
  2418. if (! emu->saved_icode)
  2419. return -ENOMEM;
  2420. return 0;
  2421. }
  2422. void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
  2423. {
  2424. kfree(emu->saved_gpr);
  2425. kfree(emu->tram_val_saved);
  2426. kfree(emu->tram_addr_saved);
  2427. vfree(emu->saved_icode);
  2428. }
  2429. /*
  2430. * save/restore GPR, TRAM and codes
  2431. */
  2432. void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
  2433. {
  2434. int i, len;
  2435. len = emu->audigy ? 0x200 : 0x100;
  2436. for (i = 0; i < len; i++)
  2437. emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
  2438. len = emu->audigy ? 0x100 : 0xa0;
  2439. for (i = 0; i < len; i++) {
  2440. emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
  2441. emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
  2442. if (emu->audigy) {
  2443. emu->tram_addr_saved[i] >>= 12;
  2444. emu->tram_addr_saved[i] |=
  2445. snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
  2446. }
  2447. }
  2448. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2449. for (i = 0; i < len; i++)
  2450. emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
  2451. }
  2452. void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
  2453. {
  2454. int i, len;
  2455. /* set up TRAM */
  2456. if (emu->fx8010.etram_pages.bytes > 0) {
  2457. unsigned size, size_reg = 0;
  2458. size = emu->fx8010.etram_pages.bytes / 2;
  2459. size = (size - 1) >> 13;
  2460. while (size) {
  2461. size >>= 1;
  2462. size_reg++;
  2463. }
  2464. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2465. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2466. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2467. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2468. }
  2469. if (emu->audigy)
  2470. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  2471. else
  2472. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  2473. len = emu->audigy ? 0x200 : 0x100;
  2474. for (i = 0; i < len; i++)
  2475. snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
  2476. len = emu->audigy ? 0x100 : 0xa0;
  2477. for (i = 0; i < len; i++) {
  2478. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
  2479. emu->tram_val_saved[i]);
  2480. if (! emu->audigy)
  2481. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2482. emu->tram_addr_saved[i]);
  2483. else {
  2484. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2485. emu->tram_addr_saved[i] << 12);
  2486. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2487. emu->tram_addr_saved[i] >> 20);
  2488. }
  2489. }
  2490. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2491. for (i = 0; i < len; i++)
  2492. snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
  2493. /* start FX processor when the DSP code is updated */
  2494. if (emu->audigy)
  2495. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2496. else
  2497. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2498. }
  2499. #endif