gpio.c 6.4 KB

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  1. /*
  2. * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two
  3. * types of registers. The data register sets the output level when in output
  4. * mode and when in input mode will contain the value at the input. The config
  5. * register sets the various modes for each gpio.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * @author Patrick Glass <patrickglass@gmail.com>
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/init.h>
  16. #include <linux/gpio.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/io.h>
  19. #define MSP71XX_CFG_OFFSET(gpio) (4 * (gpio))
  20. #define CONF_MASK 0x0F
  21. #define MSP71XX_GPIO_INPUT 0x01
  22. #define MSP71XX_GPIO_OUTPUT 0x08
  23. #define MSP71XX_GPIO_BASE 0x0B8400000L
  24. #define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip)
  25. static spinlock_t gpio_lock;
  26. /*
  27. * struct msp71xx_gpio_chip - container for gpio chip and registers
  28. * @chip: chip structure for the specified gpio bank
  29. * @data_reg: register for reading and writing the gpio pin value
  30. * @config_reg: register to set the mode for the gpio pin bank
  31. * @out_drive_reg: register to set the output drive mode for the gpio pin bank
  32. */
  33. struct msp71xx_gpio_chip {
  34. struct gpio_chip chip;
  35. void __iomem *data_reg;
  36. void __iomem *config_reg;
  37. void __iomem *out_drive_reg;
  38. };
  39. /*
  40. * msp71xx_gpio_get() - return the chip's gpio value
  41. * @chip: chip structure which controls the specified gpio
  42. * @offset: gpio whose value will be returned
  43. *
  44. * It will return 0 if gpio value is low and other if high.
  45. */
  46. static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset)
  47. {
  48. struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
  49. return __raw_readl(msp_chip->data_reg) & (1 << offset);
  50. }
  51. /*
  52. * msp71xx_gpio_set() - set the output value for the gpio
  53. * @chip: chip structure who controls the specified gpio
  54. * @offset: gpio whose value will be assigned
  55. * @value: logic level to assign to the gpio initially
  56. *
  57. * This will set the gpio bit specified to the desired value. It will set the
  58. * gpio pin low if value is 0 otherwise it will be high.
  59. */
  60. static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  61. {
  62. struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
  63. unsigned long flags;
  64. u32 data;
  65. spin_lock_irqsave(&gpio_lock, flags);
  66. data = __raw_readl(msp_chip->data_reg);
  67. if (value)
  68. data |= (1 << offset);
  69. else
  70. data &= ~(1 << offset);
  71. __raw_writel(data, msp_chip->data_reg);
  72. spin_unlock_irqrestore(&gpio_lock, flags);
  73. }
  74. /*
  75. * msp71xx_set_gpio_mode() - declare the mode for a gpio
  76. * @chip: chip structure which controls the specified gpio
  77. * @offset: gpio whose value will be assigned
  78. * @mode: desired configuration for the gpio (see datasheet)
  79. *
  80. * It will set the gpio pin config to the @mode value passed in.
  81. */
  82. static int msp71xx_set_gpio_mode(struct gpio_chip *chip,
  83. unsigned offset, int mode)
  84. {
  85. struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
  86. const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset);
  87. unsigned long flags;
  88. u32 cfg;
  89. spin_lock_irqsave(&gpio_lock, flags);
  90. cfg = __raw_readl(msp_chip->config_reg);
  91. cfg &= ~(CONF_MASK << bit_offset);
  92. cfg |= (mode << bit_offset);
  93. __raw_writel(cfg, msp_chip->config_reg);
  94. spin_unlock_irqrestore(&gpio_lock, flags);
  95. return 0;
  96. }
  97. /*
  98. * msp71xx_direction_output() - declare the direction mode for a gpio
  99. * @chip: chip structure which controls the specified gpio
  100. * @offset: gpio whose value will be assigned
  101. * @value: logic level to assign to the gpio initially
  102. *
  103. * This call will set the mode for the @gpio to output. It will set the
  104. * gpio pin low if value is 0 otherwise it will be high.
  105. */
  106. static int msp71xx_direction_output(struct gpio_chip *chip,
  107. unsigned offset, int value)
  108. {
  109. msp71xx_gpio_set(chip, offset, value);
  110. return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT);
  111. }
  112. /*
  113. * msp71xx_direction_input() - declare the direction mode for a gpio
  114. * @chip: chip structure which controls the specified gpio
  115. * @offset: gpio whose to which the value will be assigned
  116. *
  117. * This call will set the mode for the @gpio to input.
  118. */
  119. static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset)
  120. {
  121. return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT);
  122. }
  123. /*
  124. * msp71xx_set_output_drive() - declare the output drive for the gpio line
  125. * @gpio: gpio pin whose output drive you wish to modify
  126. * @value: zero for active drain 1 for open drain drive
  127. *
  128. * This call will set the output drive mode for the @gpio to output.
  129. */
  130. int msp71xx_set_output_drive(unsigned gpio, int value)
  131. {
  132. unsigned long flags;
  133. u32 data;
  134. if (gpio > 15 || gpio < 0)
  135. return -EINVAL;
  136. spin_lock_irqsave(&gpio_lock, flags);
  137. data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
  138. if (value)
  139. data |= (1 << gpio);
  140. else
  141. data &= ~(1 << gpio);
  142. __raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
  143. spin_unlock_irqrestore(&gpio_lock, flags);
  144. return 0;
  145. }
  146. EXPORT_SYMBOL(msp71xx_set_output_drive);
  147. #define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \
  148. { \
  149. .chip = { \
  150. .label = name, \
  151. .direction_input = msp71xx_direction_input, \
  152. .direction_output = msp71xx_direction_output, \
  153. .get = msp71xx_gpio_get, \
  154. .set = msp71xx_gpio_set, \
  155. .base = base_gpio, \
  156. .ngpio = num_gpio \
  157. }, \
  158. .data_reg = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \
  159. .config_reg = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \
  160. .out_drive_reg = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \
  161. }
  162. /*
  163. * struct msp71xx_gpio_banks[] - container array of gpio banks
  164. * @chip: chip structure for the specified gpio bank
  165. * @data_reg: register for reading and writing the gpio pin value
  166. * @config_reg: register to set the mode for the gpio pin bank
  167. *
  168. * This array structure defines the gpio banks for the PMC MIPS Processor.
  169. * We specify the bank name, the data register, the config register, base
  170. * starting gpio number, and the number of gpios exposed by the bank.
  171. */
  172. static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = {
  173. MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2),
  174. MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4),
  175. MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4),
  176. MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6),
  177. };
  178. void __init msp71xx_init_gpio(void)
  179. {
  180. int i;
  181. spin_lock_init(&gpio_lock);
  182. for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++)
  183. gpiochip_add(&msp71xx_gpio_banks[i].chip);
  184. }