smpboot.c 22 KB

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  1. /*
  2. * SMP boot-related support
  3. *
  4. * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
  5. * David Mosberger-Tang <davidm@hpl.hp.com>
  6. * Copyright (C) 2001, 2004-2005 Intel Corp
  7. * Rohit Seth <rohit.seth@intel.com>
  8. * Suresh Siddha <suresh.b.siddha@intel.com>
  9. * Gordon Jin <gordon.jin@intel.com>
  10. * Ashok Raj <ashok.raj@intel.com>
  11. *
  12. * 01/05/16 Rohit Seth <rohit.seth@intel.com> Moved SMP booting functions from smp.c to here.
  13. * 01/04/27 David Mosberger <davidm@hpl.hp.com> Added ITC synching code.
  14. * 02/07/31 David Mosberger <davidm@hpl.hp.com> Switch over to hotplug-CPU boot-sequence.
  15. * smp_boot_cpus()/smp_commence() is replaced by
  16. * smp_prepare_cpus()/__cpu_up()/smp_cpus_done().
  17. * 04/06/21 Ashok Raj <ashok.raj@intel.com> Added CPU Hotplug Support
  18. * 04/12/26 Jin Gordon <gordon.jin@intel.com>
  19. * 04/12/26 Rohit Seth <rohit.seth@intel.com>
  20. * Add multi-threading and multi-core detection
  21. * 05/01/30 Suresh Siddha <suresh.b.siddha@intel.com>
  22. * Setup cpu_sibling_map and cpu_core_map
  23. */
  24. #include <linux/module.h>
  25. #include <linux/acpi.h>
  26. #include <linux/bootmem.h>
  27. #include <linux/cpu.h>
  28. #include <linux/delay.h>
  29. #include <linux/init.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/irq.h>
  32. #include <linux/kernel.h>
  33. #include <linux/kernel_stat.h>
  34. #include <linux/mm.h>
  35. #include <linux/notifier.h>
  36. #include <linux/smp.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/efi.h>
  39. #include <linux/percpu.h>
  40. #include <linux/bitops.h>
  41. #include <linux/atomic.h>
  42. #include <asm/cache.h>
  43. #include <asm/current.h>
  44. #include <asm/delay.h>
  45. #include <asm/io.h>
  46. #include <asm/irq.h>
  47. #include <asm/machvec.h>
  48. #include <asm/mca.h>
  49. #include <asm/page.h>
  50. #include <asm/paravirt.h>
  51. #include <asm/pgalloc.h>
  52. #include <asm/pgtable.h>
  53. #include <asm/processor.h>
  54. #include <asm/ptrace.h>
  55. #include <asm/sal.h>
  56. #include <asm/tlbflush.h>
  57. #include <asm/unistd.h>
  58. #include <asm/sn/arch.h>
  59. #define SMP_DEBUG 0
  60. #if SMP_DEBUG
  61. #define Dprintk(x...) printk(x)
  62. #else
  63. #define Dprintk(x...)
  64. #endif
  65. #ifdef CONFIG_HOTPLUG_CPU
  66. #ifdef CONFIG_PERMIT_BSP_REMOVE
  67. #define bsp_remove_ok 1
  68. #else
  69. #define bsp_remove_ok 0
  70. #endif
  71. /*
  72. * Store all idle threads, this can be reused instead of creating
  73. * a new thread. Also avoids complicated thread destroy functionality
  74. * for idle threads.
  75. */
  76. struct task_struct *idle_thread_array[NR_CPUS];
  77. /*
  78. * Global array allocated for NR_CPUS at boot time
  79. */
  80. struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
  81. /*
  82. * start_ap in head.S uses this to store current booting cpu
  83. * info.
  84. */
  85. struct sal_to_os_boot *sal_state_for_booting_cpu = &sal_boot_rendez_state[0];
  86. #define set_brendez_area(x) (sal_state_for_booting_cpu = &sal_boot_rendez_state[(x)]);
  87. #define get_idle_for_cpu(x) (idle_thread_array[(x)])
  88. #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p))
  89. #else
  90. #define get_idle_for_cpu(x) (NULL)
  91. #define set_idle_for_cpu(x,p)
  92. #define set_brendez_area(x)
  93. #endif
  94. /*
  95. * ITC synchronization related stuff:
  96. */
  97. #define MASTER (0)
  98. #define SLAVE (SMP_CACHE_BYTES/8)
  99. #define NUM_ROUNDS 64 /* magic value */
  100. #define NUM_ITERS 5 /* likewise */
  101. static DEFINE_SPINLOCK(itc_sync_lock);
  102. static volatile unsigned long go[SLAVE + 1];
  103. #define DEBUG_ITC_SYNC 0
  104. extern void start_ap (void);
  105. extern unsigned long ia64_iobase;
  106. struct task_struct *task_for_booting_cpu;
  107. /*
  108. * State for each CPU
  109. */
  110. DEFINE_PER_CPU(int, cpu_state);
  111. cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
  112. EXPORT_SYMBOL(cpu_core_map);
  113. DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
  114. EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  115. int smp_num_siblings = 1;
  116. /* which logical CPU number maps to which CPU (physical APIC ID) */
  117. volatile int ia64_cpu_to_sapicid[NR_CPUS];
  118. EXPORT_SYMBOL(ia64_cpu_to_sapicid);
  119. static volatile cpumask_t cpu_callin_map;
  120. struct smp_boot_data smp_boot_data __initdata;
  121. unsigned long ap_wakeup_vector = -1; /* External Int use to wakeup APs */
  122. char __initdata no_int_routing;
  123. unsigned char smp_int_redirect; /* are INT and IPI redirectable by the chipset? */
  124. #ifdef CONFIG_FORCE_CPEI_RETARGET
  125. #define CPEI_OVERRIDE_DEFAULT (1)
  126. #else
  127. #define CPEI_OVERRIDE_DEFAULT (0)
  128. #endif
  129. unsigned int force_cpei_retarget = CPEI_OVERRIDE_DEFAULT;
  130. static int __init
  131. cmdl_force_cpei(char *str)
  132. {
  133. int value=0;
  134. get_option (&str, &value);
  135. force_cpei_retarget = value;
  136. return 1;
  137. }
  138. __setup("force_cpei=", cmdl_force_cpei);
  139. static int __init
  140. nointroute (char *str)
  141. {
  142. no_int_routing = 1;
  143. printk ("no_int_routing on\n");
  144. return 1;
  145. }
  146. __setup("nointroute", nointroute);
  147. static void fix_b0_for_bsp(void)
  148. {
  149. #ifdef CONFIG_HOTPLUG_CPU
  150. int cpuid;
  151. static int fix_bsp_b0 = 1;
  152. cpuid = smp_processor_id();
  153. /*
  154. * Cache the b0 value on the first AP that comes up
  155. */
  156. if (!(fix_bsp_b0 && cpuid))
  157. return;
  158. sal_boot_rendez_state[0].br[0] = sal_boot_rendez_state[cpuid].br[0];
  159. printk ("Fixed BSP b0 value from CPU %d\n", cpuid);
  160. fix_bsp_b0 = 0;
  161. #endif
  162. }
  163. void
  164. sync_master (void *arg)
  165. {
  166. unsigned long flags, i;
  167. go[MASTER] = 0;
  168. local_irq_save(flags);
  169. {
  170. for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
  171. while (!go[MASTER])
  172. cpu_relax();
  173. go[MASTER] = 0;
  174. go[SLAVE] = ia64_get_itc();
  175. }
  176. }
  177. local_irq_restore(flags);
  178. }
  179. /*
  180. * Return the number of cycles by which our itc differs from the itc on the master
  181. * (time-keeper) CPU. A positive number indicates our itc is ahead of the master,
  182. * negative that it is behind.
  183. */
  184. static inline long
  185. get_delta (long *rt, long *master)
  186. {
  187. unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
  188. unsigned long tcenter, t0, t1, tm;
  189. long i;
  190. for (i = 0; i < NUM_ITERS; ++i) {
  191. t0 = ia64_get_itc();
  192. go[MASTER] = 1;
  193. while (!(tm = go[SLAVE]))
  194. cpu_relax();
  195. go[SLAVE] = 0;
  196. t1 = ia64_get_itc();
  197. if (t1 - t0 < best_t1 - best_t0)
  198. best_t0 = t0, best_t1 = t1, best_tm = tm;
  199. }
  200. *rt = best_t1 - best_t0;
  201. *master = best_tm - best_t0;
  202. /* average best_t0 and best_t1 without overflow: */
  203. tcenter = (best_t0/2 + best_t1/2);
  204. if (best_t0 % 2 + best_t1 % 2 == 2)
  205. ++tcenter;
  206. return tcenter - best_tm;
  207. }
  208. /*
  209. * Synchronize ar.itc of the current (slave) CPU with the ar.itc of the MASTER CPU
  210. * (normally the time-keeper CPU). We use a closed loop to eliminate the possibility of
  211. * unaccounted-for errors (such as getting a machine check in the middle of a calibration
  212. * step). The basic idea is for the slave to ask the master what itc value it has and to
  213. * read its own itc before and after the master responds. Each iteration gives us three
  214. * timestamps:
  215. *
  216. * slave master
  217. *
  218. * t0 ---\
  219. * ---\
  220. * --->
  221. * tm
  222. * /---
  223. * /---
  224. * t1 <---
  225. *
  226. *
  227. * The goal is to adjust the slave's ar.itc such that tm falls exactly half-way between t0
  228. * and t1. If we achieve this, the clocks are synchronized provided the interconnect
  229. * between the slave and the master is symmetric. Even if the interconnect were
  230. * asymmetric, we would still know that the synchronization error is smaller than the
  231. * roundtrip latency (t0 - t1).
  232. *
  233. * When the interconnect is quiet and symmetric, this lets us synchronize the itc to
  234. * within one or two cycles. However, we can only *guarantee* that the synchronization is
  235. * accurate to within a round-trip time, which is typically in the range of several
  236. * hundred cycles (e.g., ~500 cycles). In practice, this means that the itc's are usually
  237. * almost perfectly synchronized, but we shouldn't assume that the accuracy is much better
  238. * than half a micro second or so.
  239. */
  240. void
  241. ia64_sync_itc (unsigned int master)
  242. {
  243. long i, delta, adj, adjust_latency = 0, done = 0;
  244. unsigned long flags, rt, master_time_stamp, bound;
  245. #if DEBUG_ITC_SYNC
  246. struct {
  247. long rt; /* roundtrip time */
  248. long master; /* master's timestamp */
  249. long diff; /* difference between midpoint and master's timestamp */
  250. long lat; /* estimate of itc adjustment latency */
  251. } t[NUM_ROUNDS];
  252. #endif
  253. /*
  254. * Make sure local timer ticks are disabled while we sync. If
  255. * they were enabled, we'd have to worry about nasty issues
  256. * like setting the ITC ahead of (or a long time before) the
  257. * next scheduled tick.
  258. */
  259. BUG_ON((ia64_get_itv() & (1 << 16)) == 0);
  260. go[MASTER] = 1;
  261. if (smp_call_function_single(master, sync_master, NULL, 0) < 0) {
  262. printk(KERN_ERR "sync_itc: failed to get attention of CPU %u!\n", master);
  263. return;
  264. }
  265. while (go[MASTER])
  266. cpu_relax(); /* wait for master to be ready */
  267. spin_lock_irqsave(&itc_sync_lock, flags);
  268. {
  269. for (i = 0; i < NUM_ROUNDS; ++i) {
  270. delta = get_delta(&rt, &master_time_stamp);
  271. if (delta == 0) {
  272. done = 1; /* let's lock on to this... */
  273. bound = rt;
  274. }
  275. if (!done) {
  276. if (i > 0) {
  277. adjust_latency += -delta;
  278. adj = -delta + adjust_latency/4;
  279. } else
  280. adj = -delta;
  281. ia64_set_itc(ia64_get_itc() + adj);
  282. }
  283. #if DEBUG_ITC_SYNC
  284. t[i].rt = rt;
  285. t[i].master = master_time_stamp;
  286. t[i].diff = delta;
  287. t[i].lat = adjust_latency/4;
  288. #endif
  289. }
  290. }
  291. spin_unlock_irqrestore(&itc_sync_lock, flags);
  292. #if DEBUG_ITC_SYNC
  293. for (i = 0; i < NUM_ROUNDS; ++i)
  294. printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
  295. t[i].rt, t[i].master, t[i].diff, t[i].lat);
  296. #endif
  297. printk(KERN_INFO "CPU %d: synchronized ITC with CPU %u (last diff %ld cycles, "
  298. "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt);
  299. }
  300. /*
  301. * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
  302. */
  303. static inline void __devinit
  304. smp_setup_percpu_timer (void)
  305. {
  306. }
  307. static void __cpuinit
  308. smp_callin (void)
  309. {
  310. int cpuid, phys_id, itc_master;
  311. struct cpuinfo_ia64 *last_cpuinfo, *this_cpuinfo;
  312. extern void ia64_init_itm(void);
  313. extern volatile int time_keeper_id;
  314. #ifdef CONFIG_PERFMON
  315. extern void pfm_init_percpu(void);
  316. #endif
  317. cpuid = smp_processor_id();
  318. phys_id = hard_smp_processor_id();
  319. itc_master = time_keeper_id;
  320. if (cpu_online(cpuid)) {
  321. printk(KERN_ERR "huh, phys CPU#0x%x, CPU#0x%x already present??\n",
  322. phys_id, cpuid);
  323. BUG();
  324. }
  325. fix_b0_for_bsp();
  326. /*
  327. * numa_node_id() works after this.
  328. */
  329. set_numa_node(cpu_to_node_map[cpuid]);
  330. set_numa_mem(local_memory_node(cpu_to_node_map[cpuid]));
  331. ipi_call_lock_irq();
  332. spin_lock(&vector_lock);
  333. /* Setup the per cpu irq handling data structures */
  334. __setup_vector_irq(cpuid);
  335. notify_cpu_starting(cpuid);
  336. set_cpu_online(cpuid, true);
  337. per_cpu(cpu_state, cpuid) = CPU_ONLINE;
  338. spin_unlock(&vector_lock);
  339. ipi_call_unlock_irq();
  340. smp_setup_percpu_timer();
  341. ia64_mca_cmc_vector_setup(); /* Setup vector on AP */
  342. #ifdef CONFIG_PERFMON
  343. pfm_init_percpu();
  344. #endif
  345. local_irq_enable();
  346. if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
  347. /*
  348. * Synchronize the ITC with the BP. Need to do this after irqs are
  349. * enabled because ia64_sync_itc() calls smp_call_function_single(), which
  350. * calls spin_unlock_bh(), which calls spin_unlock_bh(), which calls
  351. * local_bh_enable(), which bugs out if irqs are not enabled...
  352. */
  353. Dprintk("Going to syncup ITC with ITC Master.\n");
  354. ia64_sync_itc(itc_master);
  355. }
  356. /*
  357. * Get our bogomips.
  358. */
  359. ia64_init_itm();
  360. /*
  361. * Delay calibration can be skipped if new processor is identical to the
  362. * previous processor.
  363. */
  364. last_cpuinfo = cpu_data(cpuid - 1);
  365. this_cpuinfo = local_cpu_data;
  366. if (last_cpuinfo->itc_freq != this_cpuinfo->itc_freq ||
  367. last_cpuinfo->proc_freq != this_cpuinfo->proc_freq ||
  368. last_cpuinfo->features != this_cpuinfo->features ||
  369. last_cpuinfo->revision != this_cpuinfo->revision ||
  370. last_cpuinfo->family != this_cpuinfo->family ||
  371. last_cpuinfo->archrev != this_cpuinfo->archrev ||
  372. last_cpuinfo->model != this_cpuinfo->model)
  373. calibrate_delay();
  374. local_cpu_data->loops_per_jiffy = loops_per_jiffy;
  375. /*
  376. * Allow the master to continue.
  377. */
  378. cpu_set(cpuid, cpu_callin_map);
  379. Dprintk("Stack on CPU %d at about %p\n",cpuid, &cpuid);
  380. }
  381. /*
  382. * Activate a secondary processor. head.S calls this.
  383. */
  384. int __cpuinit
  385. start_secondary (void *unused)
  386. {
  387. /* Early console may use I/O ports */
  388. ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
  389. #ifndef CONFIG_PRINTK_TIME
  390. Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
  391. #endif
  392. efi_map_pal_code();
  393. cpu_init();
  394. preempt_disable();
  395. smp_callin();
  396. cpu_idle();
  397. return 0;
  398. }
  399. struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
  400. {
  401. return NULL;
  402. }
  403. struct create_idle {
  404. struct work_struct work;
  405. struct task_struct *idle;
  406. struct completion done;
  407. int cpu;
  408. };
  409. void __cpuinit
  410. do_fork_idle(struct work_struct *work)
  411. {
  412. struct create_idle *c_idle =
  413. container_of(work, struct create_idle, work);
  414. c_idle->idle = fork_idle(c_idle->cpu);
  415. complete(&c_idle->done);
  416. }
  417. static int __cpuinit
  418. do_boot_cpu (int sapicid, int cpu)
  419. {
  420. int timeout;
  421. struct create_idle c_idle = {
  422. .work = __WORK_INITIALIZER(c_idle.work, do_fork_idle),
  423. .cpu = cpu,
  424. .done = COMPLETION_INITIALIZER(c_idle.done),
  425. };
  426. /*
  427. * We can't use kernel_thread since we must avoid to
  428. * reschedule the child.
  429. */
  430. c_idle.idle = get_idle_for_cpu(cpu);
  431. if (c_idle.idle) {
  432. init_idle(c_idle.idle, cpu);
  433. goto do_rest;
  434. }
  435. schedule_work(&c_idle.work);
  436. wait_for_completion(&c_idle.done);
  437. if (IS_ERR(c_idle.idle))
  438. panic("failed fork for CPU %d", cpu);
  439. set_idle_for_cpu(cpu, c_idle.idle);
  440. do_rest:
  441. task_for_booting_cpu = c_idle.idle;
  442. Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
  443. set_brendez_area(cpu);
  444. platform_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
  445. /*
  446. * Wait 10s total for the AP to start
  447. */
  448. Dprintk("Waiting on callin_map ...");
  449. for (timeout = 0; timeout < 100000; timeout++) {
  450. if (cpu_isset(cpu, cpu_callin_map))
  451. break; /* It has booted */
  452. udelay(100);
  453. }
  454. Dprintk("\n");
  455. if (!cpu_isset(cpu, cpu_callin_map)) {
  456. printk(KERN_ERR "Processor 0x%x/0x%x is stuck.\n", cpu, sapicid);
  457. ia64_cpu_to_sapicid[cpu] = -1;
  458. set_cpu_online(cpu, false); /* was set in smp_callin() */
  459. return -EINVAL;
  460. }
  461. return 0;
  462. }
  463. static int __init
  464. decay (char *str)
  465. {
  466. int ticks;
  467. get_option (&str, &ticks);
  468. return 1;
  469. }
  470. __setup("decay=", decay);
  471. /*
  472. * Initialize the logical CPU number to SAPICID mapping
  473. */
  474. void __init
  475. smp_build_cpu_map (void)
  476. {
  477. int sapicid, cpu, i;
  478. int boot_cpu_id = hard_smp_processor_id();
  479. for (cpu = 0; cpu < NR_CPUS; cpu++) {
  480. ia64_cpu_to_sapicid[cpu] = -1;
  481. }
  482. ia64_cpu_to_sapicid[0] = boot_cpu_id;
  483. init_cpu_present(cpumask_of(0));
  484. set_cpu_possible(0, true);
  485. for (cpu = 1, i = 0; i < smp_boot_data.cpu_count; i++) {
  486. sapicid = smp_boot_data.cpu_phys_id[i];
  487. if (sapicid == boot_cpu_id)
  488. continue;
  489. set_cpu_present(cpu, true);
  490. set_cpu_possible(cpu, true);
  491. ia64_cpu_to_sapicid[cpu] = sapicid;
  492. cpu++;
  493. }
  494. }
  495. /*
  496. * Cycle through the APs sending Wakeup IPIs to boot each.
  497. */
  498. void __init
  499. smp_prepare_cpus (unsigned int max_cpus)
  500. {
  501. int boot_cpu_id = hard_smp_processor_id();
  502. /*
  503. * Initialize the per-CPU profiling counter/multiplier
  504. */
  505. smp_setup_percpu_timer();
  506. cpu_set(0, cpu_callin_map);
  507. local_cpu_data->loops_per_jiffy = loops_per_jiffy;
  508. ia64_cpu_to_sapicid[0] = boot_cpu_id;
  509. printk(KERN_INFO "Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
  510. current_thread_info()->cpu = 0;
  511. /*
  512. * If SMP should be disabled, then really disable it!
  513. */
  514. if (!max_cpus) {
  515. printk(KERN_INFO "SMP mode deactivated.\n");
  516. init_cpu_online(cpumask_of(0));
  517. init_cpu_present(cpumask_of(0));
  518. init_cpu_possible(cpumask_of(0));
  519. return;
  520. }
  521. }
  522. void __devinit smp_prepare_boot_cpu(void)
  523. {
  524. set_cpu_online(smp_processor_id(), true);
  525. cpu_set(smp_processor_id(), cpu_callin_map);
  526. set_numa_node(cpu_to_node_map[smp_processor_id()]);
  527. per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
  528. paravirt_post_smp_prepare_boot_cpu();
  529. }
  530. #ifdef CONFIG_HOTPLUG_CPU
  531. static inline void
  532. clear_cpu_sibling_map(int cpu)
  533. {
  534. int i;
  535. for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
  536. cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
  537. for_each_cpu_mask(i, cpu_core_map[cpu])
  538. cpu_clear(cpu, cpu_core_map[i]);
  539. per_cpu(cpu_sibling_map, cpu) = cpu_core_map[cpu] = CPU_MASK_NONE;
  540. }
  541. static void
  542. remove_siblinginfo(int cpu)
  543. {
  544. int last = 0;
  545. if (cpu_data(cpu)->threads_per_core == 1 &&
  546. cpu_data(cpu)->cores_per_socket == 1) {
  547. cpu_clear(cpu, cpu_core_map[cpu]);
  548. cpu_clear(cpu, per_cpu(cpu_sibling_map, cpu));
  549. return;
  550. }
  551. last = (cpus_weight(cpu_core_map[cpu]) == 1 ? 1 : 0);
  552. /* remove it from all sibling map's */
  553. clear_cpu_sibling_map(cpu);
  554. }
  555. extern void fixup_irqs(void);
  556. int migrate_platform_irqs(unsigned int cpu)
  557. {
  558. int new_cpei_cpu;
  559. struct irq_data *data = NULL;
  560. const struct cpumask *mask;
  561. int retval = 0;
  562. /*
  563. * dont permit CPEI target to removed.
  564. */
  565. if (cpe_vector > 0 && is_cpu_cpei_target(cpu)) {
  566. printk ("CPU (%d) is CPEI Target\n", cpu);
  567. if (can_cpei_retarget()) {
  568. /*
  569. * Now re-target the CPEI to a different processor
  570. */
  571. new_cpei_cpu = cpumask_any(cpu_online_mask);
  572. mask = cpumask_of(new_cpei_cpu);
  573. set_cpei_target_cpu(new_cpei_cpu);
  574. data = irq_get_irq_data(ia64_cpe_irq);
  575. /*
  576. * Switch for now, immediately, we need to do fake intr
  577. * as other interrupts, but need to study CPEI behaviour with
  578. * polling before making changes.
  579. */
  580. if (data && data->chip) {
  581. data->chip->irq_disable(data);
  582. data->chip->irq_set_affinity(data, mask, false);
  583. data->chip->irq_enable(data);
  584. printk ("Re-targeting CPEI to cpu %d\n", new_cpei_cpu);
  585. }
  586. }
  587. if (!data) {
  588. printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
  589. retval = -EBUSY;
  590. }
  591. }
  592. return retval;
  593. }
  594. /* must be called with cpucontrol mutex held */
  595. int __cpu_disable(void)
  596. {
  597. int cpu = smp_processor_id();
  598. /*
  599. * dont permit boot processor for now
  600. */
  601. if (cpu == 0 && !bsp_remove_ok) {
  602. printk ("Your platform does not support removal of BSP\n");
  603. return (-EBUSY);
  604. }
  605. if (ia64_platform_is("sn2")) {
  606. if (!sn_cpu_disable_allowed(cpu))
  607. return -EBUSY;
  608. }
  609. set_cpu_online(cpu, false);
  610. if (migrate_platform_irqs(cpu)) {
  611. set_cpu_online(cpu, true);
  612. return -EBUSY;
  613. }
  614. remove_siblinginfo(cpu);
  615. fixup_irqs();
  616. local_flush_tlb_all();
  617. cpu_clear(cpu, cpu_callin_map);
  618. return 0;
  619. }
  620. void __cpu_die(unsigned int cpu)
  621. {
  622. unsigned int i;
  623. for (i = 0; i < 100; i++) {
  624. /* They ack this in play_dead by setting CPU_DEAD */
  625. if (per_cpu(cpu_state, cpu) == CPU_DEAD)
  626. {
  627. printk ("CPU %d is now offline\n", cpu);
  628. return;
  629. }
  630. msleep(100);
  631. }
  632. printk(KERN_ERR "CPU %u didn't die...\n", cpu);
  633. }
  634. #endif /* CONFIG_HOTPLUG_CPU */
  635. void
  636. smp_cpus_done (unsigned int dummy)
  637. {
  638. int cpu;
  639. unsigned long bogosum = 0;
  640. /*
  641. * Allow the user to impress friends.
  642. */
  643. for_each_online_cpu(cpu) {
  644. bogosum += cpu_data(cpu)->loops_per_jiffy;
  645. }
  646. printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
  647. (int)num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
  648. }
  649. static inline void __devinit
  650. set_cpu_sibling_map(int cpu)
  651. {
  652. int i;
  653. for_each_online_cpu(i) {
  654. if ((cpu_data(cpu)->socket_id == cpu_data(i)->socket_id)) {
  655. cpu_set(i, cpu_core_map[cpu]);
  656. cpu_set(cpu, cpu_core_map[i]);
  657. if (cpu_data(cpu)->core_id == cpu_data(i)->core_id) {
  658. cpu_set(i, per_cpu(cpu_sibling_map, cpu));
  659. cpu_set(cpu, per_cpu(cpu_sibling_map, i));
  660. }
  661. }
  662. }
  663. }
  664. int __cpuinit
  665. __cpu_up (unsigned int cpu)
  666. {
  667. int ret;
  668. int sapicid;
  669. sapicid = ia64_cpu_to_sapicid[cpu];
  670. if (sapicid == -1)
  671. return -EINVAL;
  672. /*
  673. * Already booted cpu? not valid anymore since we dont
  674. * do idle loop tightspin anymore.
  675. */
  676. if (cpu_isset(cpu, cpu_callin_map))
  677. return -EINVAL;
  678. per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
  679. /* Processor goes to start_secondary(), sets online flag */
  680. ret = do_boot_cpu(sapicid, cpu);
  681. if (ret < 0)
  682. return ret;
  683. if (cpu_data(cpu)->threads_per_core == 1 &&
  684. cpu_data(cpu)->cores_per_socket == 1) {
  685. cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
  686. cpu_set(cpu, cpu_core_map[cpu]);
  687. return 0;
  688. }
  689. set_cpu_sibling_map(cpu);
  690. return 0;
  691. }
  692. /*
  693. * Assume that CPUs have been discovered by some platform-dependent interface. For
  694. * SoftSDV/Lion, that would be ACPI.
  695. *
  696. * Setup of the IPI irq handler is done in irq.c:init_IRQ_SMP().
  697. */
  698. void __init
  699. init_smp_config(void)
  700. {
  701. struct fptr {
  702. unsigned long fp;
  703. unsigned long gp;
  704. } *ap_startup;
  705. long sal_ret;
  706. /* Tell SAL where to drop the APs. */
  707. ap_startup = (struct fptr *) start_ap;
  708. sal_ret = ia64_sal_set_vectors(SAL_VECTOR_OS_BOOT_RENDEZ,
  709. ia64_tpa(ap_startup->fp), ia64_tpa(ap_startup->gp), 0, 0, 0, 0);
  710. if (sal_ret < 0)
  711. printk(KERN_ERR "SMP: Can't set SAL AP Boot Rendezvous: %s\n",
  712. ia64_sal_strerror(sal_ret));
  713. }
  714. /*
  715. * identify_siblings(cpu) gets called from identify_cpu. This populates the
  716. * information related to logical execution units in per_cpu_data structure.
  717. */
  718. void __devinit
  719. identify_siblings(struct cpuinfo_ia64 *c)
  720. {
  721. long status;
  722. u16 pltid;
  723. pal_logical_to_physical_t info;
  724. status = ia64_pal_logical_to_phys(-1, &info);
  725. if (status != PAL_STATUS_SUCCESS) {
  726. if (status != PAL_STATUS_UNIMPLEMENTED) {
  727. printk(KERN_ERR
  728. "ia64_pal_logical_to_phys failed with %ld\n",
  729. status);
  730. return;
  731. }
  732. info.overview_ppid = 0;
  733. info.overview_cpp = 1;
  734. info.overview_tpc = 1;
  735. }
  736. status = ia64_sal_physical_id_info(&pltid);
  737. if (status != PAL_STATUS_SUCCESS) {
  738. if (status != PAL_STATUS_UNIMPLEMENTED)
  739. printk(KERN_ERR
  740. "ia64_sal_pltid failed with %ld\n",
  741. status);
  742. return;
  743. }
  744. c->socket_id = (pltid << 8) | info.overview_ppid;
  745. if (info.overview_cpp == 1 && info.overview_tpc == 1)
  746. return;
  747. c->cores_per_socket = info.overview_cpp;
  748. c->threads_per_core = info.overview_tpc;
  749. c->num_log = info.overview_num_log;
  750. c->core_id = info.log1_cid;
  751. c->thread_id = info.log1_tid;
  752. }
  753. /*
  754. * returns non zero, if multi-threading is enabled
  755. * on at least one physical package. Due to hotplug cpu
  756. * and (maxcpus=), all threads may not necessarily be enabled
  757. * even though the processor supports multi-threading.
  758. */
  759. int is_multithreading_enabled(void)
  760. {
  761. int i, j;
  762. for_each_present_cpu(i) {
  763. for_each_present_cpu(j) {
  764. if (j == i)
  765. continue;
  766. if ((cpu_data(j)->socket_id == cpu_data(i)->socket_id)) {
  767. if (cpu_data(j)->core_id == cpu_data(i)->core_id)
  768. return 1;
  769. }
  770. }
  771. }
  772. return 0;
  773. }
  774. EXPORT_SYMBOL_GPL(is_multithreading_enabled);