uncompress.h 3.9 KB

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  1. /* arch/arm/plat-samsung/include/plat/uncompress.h
  2. *
  3. * Copyright 2003, 2007 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * S3C - uncompress code
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #ifndef __ASM_PLAT_UNCOMPRESS_H
  14. #define __ASM_PLAT_UNCOMPRESS_H
  15. typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
  16. /* uart setup */
  17. unsigned int fifo_mask;
  18. unsigned int fifo_max;
  19. /* forward declerations */
  20. static void arch_detect_cpu(void);
  21. /* defines for UART registers */
  22. #include <plat/regs-serial.h>
  23. #include <plat/regs-watchdog.h>
  24. /* working in physical space... */
  25. #undef S3C2410_WDOGREG
  26. #define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
  27. /* how many bytes we allow into the FIFO at a time in FIFO mode */
  28. #define FIFO_MAX (14)
  29. #ifdef S3C_PA_UART
  30. #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
  31. #endif
  32. static __inline__ void
  33. uart_wr(unsigned int reg, unsigned int val)
  34. {
  35. volatile unsigned int *ptr;
  36. ptr = (volatile unsigned int *)(reg + uart_base);
  37. *ptr = val;
  38. }
  39. static __inline__ unsigned int
  40. uart_rd(unsigned int reg)
  41. {
  42. volatile unsigned int *ptr;
  43. ptr = (volatile unsigned int *)(reg + uart_base);
  44. return *ptr;
  45. }
  46. /* we can deal with the case the UARTs are being run
  47. * in FIFO mode, so that we don't hold up our execution
  48. * waiting for tx to happen...
  49. */
  50. static void putc(int ch)
  51. {
  52. if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
  53. int level;
  54. while (1) {
  55. level = uart_rd(S3C2410_UFSTAT);
  56. level &= fifo_mask;
  57. if (level < fifo_max)
  58. break;
  59. }
  60. } else {
  61. /* not using fifos */
  62. while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
  63. barrier();
  64. }
  65. /* write byte to transmission register */
  66. uart_wr(S3C2410_UTXH, ch);
  67. }
  68. static inline void flush(void)
  69. {
  70. }
  71. #define __raw_writel(d, ad) \
  72. do { \
  73. *((volatile unsigned int __force *)(ad)) = (d); \
  74. } while (0)
  75. /* CONFIG_S3C_BOOT_WATCHDOG
  76. *
  77. * Simple boot-time watchdog setup, to reboot the system if there is
  78. * any problem with the boot process
  79. */
  80. #ifdef CONFIG_S3C_BOOT_WATCHDOG
  81. #define WDOG_COUNT (0xff00)
  82. static inline void arch_decomp_wdog(void)
  83. {
  84. __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
  85. }
  86. static void arch_decomp_wdog_start(void)
  87. {
  88. __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
  89. __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
  90. __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
  91. }
  92. #else
  93. #define arch_decomp_wdog_start()
  94. #define arch_decomp_wdog()
  95. #endif
  96. #ifdef CONFIG_S3C_BOOT_ERROR_RESET
  97. static void arch_decomp_error(const char *x)
  98. {
  99. putstr("\n\n");
  100. putstr(x);
  101. putstr("\n\n -- System resetting\n");
  102. __raw_writel(0x4000, S3C2410_WTDAT);
  103. __raw_writel(0x4000, S3C2410_WTCNT);
  104. __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
  105. while(1);
  106. }
  107. #define arch_error arch_decomp_error
  108. #endif
  109. #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
  110. static inline void arch_enable_uart_fifo(void)
  111. {
  112. u32 fifocon = uart_rd(S3C2410_UFCON);
  113. if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
  114. fifocon |= S3C2410_UFCON_RESETBOTH;
  115. uart_wr(S3C2410_UFCON, fifocon);
  116. /* wait for fifo reset to complete */
  117. while (1) {
  118. fifocon = uart_rd(S3C2410_UFCON);
  119. if (!(fifocon & S3C2410_UFCON_RESETBOTH))
  120. break;
  121. }
  122. }
  123. }
  124. #else
  125. #define arch_enable_uart_fifo() do { } while(0)
  126. #endif
  127. static void
  128. arch_decomp_setup(void)
  129. {
  130. /* we may need to setup the uart(s) here if we are not running
  131. * on an BAST... the BAST will have left the uarts configured
  132. * after calling linux.
  133. */
  134. arch_detect_cpu();
  135. arch_decomp_wdog_start();
  136. /* Enable the UART FIFOs if they where not enabled and our
  137. * configuration says we should turn them on.
  138. */
  139. arch_enable_uart_fifo();
  140. }
  141. #endif /* __ASM_PLAT_UNCOMPRESS_H */