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regs-onenand.h

regs-onenand.h 1.7 KB
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  1. /*
    2. 

  2.  * linux/arch/arm/plat-s3c/include/plat/regs-onenand.h
    3. 

  3.  *
    4. 

  4.  *  Copyright (C) 2008-2010 Samsung Electronics
    5. 

  5.  *  Kyungmin Park <kyungmin.park@samsung.com>
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or modify
    8. 

  8.  * it under the terms of the GNU General Public License version 2 as
    9. 

  9.  * published by the Free Software Foundation.
    10. 

  10.  */
    11. 

  11. #ifndef __SAMSUNG_ONENAND_H__
    12. 

  12. #define __SAMSUNG_ONENAND_H__
    13. 

  13. 

  14. #include <mach/hardware.h>
    15. 

  15. 

  16. /*
    17. 

  17.  * OneNAND Controller
    18. 

  18.  */
    19. 

  19. #define MEM_CFG_OFFSET		0x0000
    20. 

  20. #define BURST_LEN_OFFSET	0x0010
    21. 

  21. #define MEM_RESET_OFFSET	0x0020
    22. 

  22. #define INT_ERR_STAT_OFFSET	0x0030
    23. 

  23. #define INT_ERR_MASK_OFFSET	0x0040
    24. 

  24. #define INT_ERR_ACK_OFFSET	0x0050
    25. 

  25. #define ECC_ERR_STAT_OFFSET	0x0060
    26. 

  26. #define MANUFACT_ID_OFFSET	0x0070
    27. 

  27. #define DEVICE_ID_OFFSET	0x0080
    28. 

  28. #define DATA_BUF_SIZE_OFFSET	0x0090
    29. 

  29. #define BOOT_BUF_SIZE_OFFSET	0x00A0
    30. 

  30. #define BUF_AMOUNT_OFFSET	0x00B0
    31. 

  31. #define TECH_OFFSET		0x00C0
    32. 

  32. #define FBA_WIDTH_OFFSET	0x00D0
    33. 

  33. #define FPA_WIDTH_OFFSET	0x00E0
    34. 

  34. #define FSA_WIDTH_OFFSET	0x00F0
    35. 

  35. #define TRANS_SPARE_OFFSET	0x0140
    36. 

  36. #define DBS_DFS_WIDTH_OFFSET	0x0160
    37. 

  37. #define INT_PIN_ENABLE_OFFSET	0x01A0
    38. 

  38. #define ACC_CLOCK_OFFSET	0x01C0
    39. 

  39. #define FLASH_VER_ID_OFFSET	0x01F0
    40. 

  40. #define FLASH_AUX_CNTRL_OFFSET	0x0300		/* s3c64xx only */
    41. 

  41. 

  42. #define ONENAND_MEM_RESET_HOT	0x3
    43. 

  43. #define ONENAND_MEM_RESET_COLD	0x2
    44. 

  44. #define ONENAND_MEM_RESET_WARM	0x1
    45. 

  45. 

  46. #define CACHE_OP_ERR		(1 << 13)
    47. 

  47. #define RST_CMP			(1 << 12)
    48. 

  48. #define RDY_ACT			(1 << 11)
    49. 

  49. #define INT_ACT			(1 << 10)
    50. 

  50. #define UNSUP_CMD		(1 << 9)
    51. 

  51. #define LOCKED_BLK		(1 << 8)
    52. 

  52. #define BLK_RW_CMP		(1 << 7)
    53. 

  53. #define ERS_CMP			(1 << 6)
    54. 

  54. #define PGM_CMP			(1 << 5)
    55. 

  55. #define LOAD_CMP		(1 << 4)
    56. 

  56. #define ERS_FAIL		(1 << 3)
    57. 

  57. #define PGM_FAIL		(1 << 2)
    58. 

  58. #define INT_TO			(1 << 1)
    59. 

  59. #define LD_FAIL_ECC_ERR		(1 << 0)
    60. 

  60. 

  61. #define TSRF			(1 << 0)
    62. 

  62. 

  63. #endif
    64. 

  64.