cache-pl310-erp.c 7.3 KB

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  1. /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. */
  12. #include <linux/interrupt.h>
  13. #include <linux/irq.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/module.h>
  16. #include <linux/errno.h>
  17. #include <linux/cpu.h>
  18. #include <linux/io.h>
  19. #include <asm/cputype.h>
  20. #include <asm/hardware/cache-l2x0.h>
  21. #define MODULE_NAME "pl310_erp"
  22. struct pl310_drv_data {
  23. unsigned int irq;
  24. unsigned int ecntr;
  25. unsigned int parrt;
  26. unsigned int parrd;
  27. unsigned int errwd;
  28. unsigned int errwt;
  29. unsigned int errrt;
  30. unsigned int errrd;
  31. unsigned int slverr;
  32. unsigned int decerr;
  33. void __iomem *base;
  34. unsigned int intr_mask_reg;
  35. };
  36. #define ECNTR BIT(0)
  37. #define PARRT BIT(1)
  38. #define PARRD BIT(2)
  39. #define ERRWT BIT(3)
  40. #define ERRWD BIT(4)
  41. #define ERRRT BIT(5)
  42. #define ERRRD BIT(6)
  43. #define SLVERR BIT(7)
  44. #define DECERR BIT(8)
  45. static irqreturn_t pl310_erp_irq(int irq, void *dev_id)
  46. {
  47. struct pl310_drv_data *p = platform_get_drvdata(dev_id);
  48. uint16_t mask_int_stat, int_clear = 0, error = 0;
  49. mask_int_stat = readl_relaxed(p->base + L2X0_MASKED_INTR_STAT);
  50. if (mask_int_stat & ECNTR) {
  51. pr_alert("Event Counter1/0 Overflow Increment error\n");
  52. p->ecntr++;
  53. int_clear = mask_int_stat & ECNTR;
  54. }
  55. if (mask_int_stat & PARRT) {
  56. pr_alert("Read parity error on L2 Tag RAM\n");
  57. p->parrt++;
  58. error = 1;
  59. int_clear = mask_int_stat & PARRT;
  60. }
  61. if (mask_int_stat & PARRD) {
  62. pr_alert("Read parity error on L2 Tag RAM\n");
  63. p->parrd++;
  64. error = 1;
  65. int_clear = mask_int_stat & PARRD;
  66. }
  67. if (mask_int_stat & ERRWT) {
  68. pr_alert("Write error on L2 Tag RAM\n");
  69. p->errwt++;
  70. int_clear = mask_int_stat & ERRWT;
  71. }
  72. if (mask_int_stat & ERRWD) {
  73. pr_alert("Write error on L2 Data RAM\n");
  74. p->errwd++;
  75. int_clear = mask_int_stat & ERRWD;
  76. }
  77. if (mask_int_stat & ERRRT) {
  78. pr_alert("Read error on L2 Tag RAM\n");
  79. p->errrt++;
  80. int_clear = mask_int_stat & ERRRT;
  81. }
  82. if (mask_int_stat & ERRRD) {
  83. pr_alert("Read error on L2 Data RAM\n");
  84. p->errrd++;
  85. int_clear = mask_int_stat & ERRRD;
  86. }
  87. if (mask_int_stat & DECERR) {
  88. pr_alert("L2 master port decode error\n");
  89. p->decerr++;
  90. int_clear = mask_int_stat & DECERR;
  91. }
  92. if (mask_int_stat & SLVERR) {
  93. pr_alert("L2 slave port error\n");
  94. p->slverr++;
  95. int_clear = mask_int_stat & SLVERR;
  96. }
  97. writel_relaxed(int_clear, p->base + L2X0_INTR_CLEAR);
  98. /* Make sure the interrupts are cleared */
  99. mb();
  100. /* WARNING will be thrown whenever we receive any L2 interrupt.
  101. * Other than parity on tag/data ram, irrespective of the bits
  102. * set we will throw a warning.
  103. */
  104. WARN_ON(!error);
  105. /* Panic in case we encounter parity error in TAG/DATA Ram */
  106. BUG_ON(error);
  107. return IRQ_HANDLED;
  108. }
  109. static void pl310_mask_int(struct pl310_drv_data *p, bool enable)
  110. {
  111. /* L2CC register contents needs to be saved
  112. * as it's power rail will be removed during suspend
  113. */
  114. if (enable)
  115. p->intr_mask_reg = 0x1FF;
  116. else
  117. p->intr_mask_reg = 0x0;
  118. writel_relaxed(p->intr_mask_reg, p->base + L2X0_INTR_MASK);
  119. /* Make sure Mask is updated */
  120. mb();
  121. pr_debug("Mask interrupt 0%x\n",
  122. readl_relaxed(p->base + L2X0_INTR_MASK));
  123. }
  124. static int pl310_erp_show(struct device *dev, struct device_attribute *attr,
  125. char *buf)
  126. {
  127. struct pl310_drv_data *p = dev_get_drvdata(dev);
  128. return snprintf(buf, PAGE_SIZE,
  129. "L2CC Interrupt Number:\t\t\t%d\n"\
  130. "Event Counter1/0 Overflow Increment:\t%u\n"\
  131. "Parity Error on L2 Tag RAM (Read):\t%u\n"\
  132. "Parity Error on L2 Data RAM (Read):\t%u\n"\
  133. "Error on L2 Tag RAM (Write):\t\t%u\n"\
  134. "Error on L2 Data RAM (Write):\t\t%u\n"\
  135. "Error on L2 Tag RAM (Read):\t\t%u\n"\
  136. "Error on L2 Data RAM (Read):\t\t%u\n"\
  137. "SLave Error from L3 Port:\t\t%u\n"\
  138. "Decode Error from L3 Port:\t\t%u\n",
  139. p->irq, p->ecntr, p->parrt, p->parrd, p->errwt, p->errwd,
  140. p->errrt, p->errrd, p->slverr, p->decerr);
  141. }
  142. static DEVICE_ATTR(cache_erp, 0664, pl310_erp_show, NULL);
  143. static int __init pl310_create_sysfs(struct device *dev)
  144. {
  145. /* create a sysfs entry at
  146. * /sys/devices/platform/pl310_erp/cache_erp
  147. */
  148. return device_create_file(dev, &dev_attr_cache_erp);
  149. }
  150. static int __devinit pl310_cache_erp_probe(struct platform_device *pdev)
  151. {
  152. struct resource *r;
  153. struct pl310_drv_data *drv_data;
  154. int ret;
  155. drv_data = devm_kzalloc(&pdev->dev, sizeof(struct pl310_drv_data),
  156. GFP_KERNEL);
  157. if (drv_data == NULL) {
  158. dev_err(&pdev->dev, "cannot allocate memory\n");
  159. ret = -ENOMEM;
  160. goto error;
  161. }
  162. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  163. if (!r) {
  164. dev_err(&pdev->dev, "No L2 base address\n");
  165. ret = -ENODEV;
  166. goto error;
  167. }
  168. if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
  169. "erp")) {
  170. ret = -EBUSY;
  171. goto error;
  172. }
  173. drv_data->base = devm_ioremap_nocache(&pdev->dev, r->start,
  174. resource_size(r));
  175. if (!drv_data->base) {
  176. dev_err(&pdev->dev, "errored to ioremap 0x%x\n", r->start);
  177. ret = -ENOMEM;
  178. goto error;
  179. }
  180. dev_dbg(&pdev->dev, "L2CC base 0x%p\n", drv_data->base);
  181. r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "l2_irq");
  182. if (!r) {
  183. dev_err(&pdev->dev, "No L2 IRQ resource\n");
  184. ret = -ENODEV;
  185. goto error;
  186. }
  187. drv_data->irq = r->start;
  188. ret = devm_request_irq(&pdev->dev, drv_data->irq, pl310_erp_irq,
  189. IRQF_TRIGGER_RISING, "l2cc_intr", pdev);
  190. if (ret) {
  191. dev_err(&pdev->dev, "request irq for L2 interrupt failed\n");
  192. goto error;
  193. }
  194. platform_set_drvdata(pdev, drv_data);
  195. pl310_mask_int(drv_data, true);
  196. ret = pl310_create_sysfs(&pdev->dev);
  197. if (ret) {
  198. dev_err(&pdev->dev, "Failed to create sysfs entry\n");
  199. goto sysfs_err;
  200. }
  201. return 0;
  202. sysfs_err:
  203. platform_set_drvdata(pdev, NULL);
  204. pl310_mask_int(drv_data, false);
  205. error:
  206. return ret;
  207. }
  208. static int __devexit pl310_cache_erp_remove(struct platform_device *pdev)
  209. {
  210. struct pl310_drv_data *p = platform_get_drvdata(pdev);
  211. pl310_mask_int(p, false);
  212. device_remove_file(&pdev->dev, &dev_attr_cache_erp);
  213. platform_set_drvdata(pdev, NULL);
  214. return 0;
  215. }
  216. #ifdef CONFIG_PM
  217. static int pl310_suspend(struct device *dev)
  218. {
  219. struct pl310_drv_data *p = dev_get_drvdata(dev);
  220. disable_irq(p->irq);
  221. return 0;
  222. }
  223. static int pl310_resume_early(struct device *dev)
  224. {
  225. struct pl310_drv_data *p = dev_get_drvdata(dev);
  226. pl310_mask_int(p, true);
  227. enable_irq(p->irq);
  228. return 0;
  229. }
  230. static const struct dev_pm_ops pl310_cache_pm_ops = {
  231. .suspend = pl310_suspend,
  232. .resume_early = pl310_resume_early,
  233. };
  234. #endif
  235. static struct platform_driver pl310_cache_erp_driver = {
  236. .probe = pl310_cache_erp_probe,
  237. .remove = __devexit_p(pl310_cache_erp_remove),
  238. .driver = {
  239. .name = MODULE_NAME,
  240. .owner = THIS_MODULE,
  241. #ifdef CONFIG_PM
  242. .pm = &pl310_cache_pm_ops,
  243. #endif
  244. },
  245. };
  246. static int __init pl310_cache_erp_init(void)
  247. {
  248. return platform_driver_register(&pl310_cache_erp_driver);
  249. }
  250. module_init(pl310_cache_erp_init);
  251. static void __exit pl310_cache_erp_exit(void)
  252. {
  253. platform_driver_unregister(&pl310_cache_erp_driver);
  254. }
  255. module_exit(pl310_cache_erp_exit);
  256. MODULE_LICENSE("GPL v2");
  257. MODULE_DESCRIPTION("PL310 cache error reporting driver");