neponset.c 10 KB

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  1. /*
  2. * linux/arch/arm/mach-sa1100/neponset.c
  3. */
  4. #include <linux/err.h>
  5. #include <linux/init.h>
  6. #include <linux/ioport.h>
  7. #include <linux/irq.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pm.h>
  12. #include <linux/serial_core.h>
  13. #include <linux/slab.h>
  14. #include <asm/mach-types.h>
  15. #include <asm/mach/map.h>
  16. #include <asm/mach/serial_sa1100.h>
  17. #include <asm/hardware/sa1111.h>
  18. #include <asm/sizes.h>
  19. #include <mach/hardware.h>
  20. #include <mach/assabet.h>
  21. #include <mach/neponset.h>
  22. #include <mach/irqs.h>
  23. #define NEP_IRQ_SMC91X 0
  24. #define NEP_IRQ_USAR 1
  25. #define NEP_IRQ_SA1111 2
  26. #define NEP_IRQ_NR 3
  27. #define WHOAMI 0x00
  28. #define LEDS 0x10
  29. #define SWPK 0x20
  30. #define IRR 0x24
  31. #define KP_Y_IN 0x80
  32. #define KP_X_OUT 0x90
  33. #define NCR_0 0xa0
  34. #define MDM_CTL_0 0xb0
  35. #define MDM_CTL_1 0xb4
  36. #define AUD_CTL 0xc0
  37. #define IRR_ETHERNET (1 << 0)
  38. #define IRR_USAR (1 << 1)
  39. #define IRR_SA1111 (1 << 2)
  40. #define MDM_CTL0_RTS1 (1 << 0)
  41. #define MDM_CTL0_DTR1 (1 << 1)
  42. #define MDM_CTL0_RTS2 (1 << 2)
  43. #define MDM_CTL0_DTR2 (1 << 3)
  44. #define MDM_CTL1_CTS1 (1 << 0)
  45. #define MDM_CTL1_DSR1 (1 << 1)
  46. #define MDM_CTL1_DCD1 (1 << 2)
  47. #define MDM_CTL1_CTS2 (1 << 3)
  48. #define MDM_CTL1_DSR2 (1 << 4)
  49. #define MDM_CTL1_DCD2 (1 << 5)
  50. #define AUD_SEL_1341 (1 << 0)
  51. #define AUD_MUTE_1341 (1 << 1)
  52. extern void sa1110_mb_disable(void);
  53. struct neponset_drvdata {
  54. void __iomem *base;
  55. struct platform_device *sa1111;
  56. struct platform_device *smc91x;
  57. unsigned irq_base;
  58. #ifdef CONFIG_PM_SLEEP
  59. u32 ncr0;
  60. u32 mdm_ctl_0;
  61. #endif
  62. };
  63. static void __iomem *nep_base;
  64. void neponset_ncr_frob(unsigned int mask, unsigned int val)
  65. {
  66. void __iomem *base = nep_base;
  67. if (base) {
  68. unsigned long flags;
  69. unsigned v;
  70. local_irq_save(flags);
  71. v = readb_relaxed(base + NCR_0);
  72. writeb_relaxed((v & ~mask) | val, base + NCR_0);
  73. local_irq_restore(flags);
  74. } else {
  75. WARN(1, "nep_base unset\n");
  76. }
  77. }
  78. static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
  79. {
  80. void __iomem *base = nep_base;
  81. u_int mdm_ctl0;
  82. if (!base)
  83. return;
  84. mdm_ctl0 = readb_relaxed(base + MDM_CTL_0);
  85. if (port->mapbase == _Ser1UTCR0) {
  86. if (mctrl & TIOCM_RTS)
  87. mdm_ctl0 &= ~MDM_CTL0_RTS2;
  88. else
  89. mdm_ctl0 |= MDM_CTL0_RTS2;
  90. if (mctrl & TIOCM_DTR)
  91. mdm_ctl0 &= ~MDM_CTL0_DTR2;
  92. else
  93. mdm_ctl0 |= MDM_CTL0_DTR2;
  94. } else if (port->mapbase == _Ser3UTCR0) {
  95. if (mctrl & TIOCM_RTS)
  96. mdm_ctl0 &= ~MDM_CTL0_RTS1;
  97. else
  98. mdm_ctl0 |= MDM_CTL0_RTS1;
  99. if (mctrl & TIOCM_DTR)
  100. mdm_ctl0 &= ~MDM_CTL0_DTR1;
  101. else
  102. mdm_ctl0 |= MDM_CTL0_DTR1;
  103. }
  104. writeb_relaxed(mdm_ctl0, base + MDM_CTL_0);
  105. }
  106. static u_int neponset_get_mctrl(struct uart_port *port)
  107. {
  108. void __iomem *base = nep_base;
  109. u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
  110. u_int mdm_ctl1;
  111. if (!base)
  112. return ret;
  113. mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
  114. if (port->mapbase == _Ser1UTCR0) {
  115. if (mdm_ctl1 & MDM_CTL1_DCD2)
  116. ret &= ~TIOCM_CD;
  117. if (mdm_ctl1 & MDM_CTL1_CTS2)
  118. ret &= ~TIOCM_CTS;
  119. if (mdm_ctl1 & MDM_CTL1_DSR2)
  120. ret &= ~TIOCM_DSR;
  121. } else if (port->mapbase == _Ser3UTCR0) {
  122. if (mdm_ctl1 & MDM_CTL1_DCD1)
  123. ret &= ~TIOCM_CD;
  124. if (mdm_ctl1 & MDM_CTL1_CTS1)
  125. ret &= ~TIOCM_CTS;
  126. if (mdm_ctl1 & MDM_CTL1_DSR1)
  127. ret &= ~TIOCM_DSR;
  128. }
  129. return ret;
  130. }
  131. static struct sa1100_port_fns neponset_port_fns __devinitdata = {
  132. .set_mctrl = neponset_set_mctrl,
  133. .get_mctrl = neponset_get_mctrl,
  134. };
  135. /*
  136. * Install handler for Neponset IRQ. Note that we have to loop here
  137. * since the ETHERNET and USAR IRQs are level based, and we need to
  138. * ensure that the IRQ signal is deasserted before returning. This
  139. * is rather unfortunate.
  140. */
  141. static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
  142. {
  143. struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
  144. unsigned int irr;
  145. while (1) {
  146. /*
  147. * Acknowledge the parent IRQ.
  148. */
  149. desc->irq_data.chip->irq_ack(&desc->irq_data);
  150. /*
  151. * Read the interrupt reason register. Let's have all
  152. * active IRQ bits high. Note: there is a typo in the
  153. * Neponset user's guide for the SA1111 IRR level.
  154. */
  155. irr = readb_relaxed(d->base + IRR);
  156. irr ^= IRR_ETHERNET | IRR_USAR;
  157. if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
  158. break;
  159. /*
  160. * Since there is no individual mask, we have to
  161. * mask the parent IRQ. This is safe, since we'll
  162. * recheck the register for any pending IRQs.
  163. */
  164. if (irr & (IRR_ETHERNET | IRR_USAR)) {
  165. desc->irq_data.chip->irq_mask(&desc->irq_data);
  166. /*
  167. * Ack the interrupt now to prevent re-entering
  168. * this neponset handler. Again, this is safe
  169. * since we'll check the IRR register prior to
  170. * leaving.
  171. */
  172. desc->irq_data.chip->irq_ack(&desc->irq_data);
  173. if (irr & IRR_ETHERNET)
  174. generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
  175. if (irr & IRR_USAR)
  176. generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
  177. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  178. }
  179. if (irr & IRR_SA1111)
  180. generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
  181. }
  182. }
  183. /* Yes, we really do not have any kind of masking or unmasking */
  184. static void nochip_noop(struct irq_data *irq)
  185. {
  186. }
  187. static struct irq_chip nochip = {
  188. .name = "neponset",
  189. .irq_ack = nochip_noop,
  190. .irq_mask = nochip_noop,
  191. .irq_unmask = nochip_noop,
  192. };
  193. static struct sa1111_platform_data sa1111_info = {
  194. .disable_devs = SA1111_DEVID_PS2_MSE,
  195. };
  196. static int __devinit neponset_probe(struct platform_device *dev)
  197. {
  198. struct neponset_drvdata *d;
  199. struct resource *nep_res, *sa1111_res, *smc91x_res;
  200. struct resource sa1111_resources[] = {
  201. DEFINE_RES_MEM(0x40000000, SZ_8K),
  202. { .flags = IORESOURCE_IRQ },
  203. };
  204. struct platform_device_info sa1111_devinfo = {
  205. .parent = &dev->dev,
  206. .name = "sa1111",
  207. .id = 0,
  208. .res = sa1111_resources,
  209. .num_res = ARRAY_SIZE(sa1111_resources),
  210. .data = &sa1111_info,
  211. .size_data = sizeof(sa1111_info),
  212. .dma_mask = 0xffffffffUL,
  213. };
  214. struct resource smc91x_resources[] = {
  215. DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
  216. 0x02000000, "smc91x-regs"),
  217. DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
  218. 0x02000000, "smc91x-attrib"),
  219. { .flags = IORESOURCE_IRQ },
  220. };
  221. struct platform_device_info smc91x_devinfo = {
  222. .parent = &dev->dev,
  223. .name = "smc91x",
  224. .id = 0,
  225. .res = smc91x_resources,
  226. .num_res = ARRAY_SIZE(smc91x_resources),
  227. };
  228. int ret, irq;
  229. if (nep_base)
  230. return -EBUSY;
  231. irq = ret = platform_get_irq(dev, 0);
  232. if (ret < 0)
  233. goto err_alloc;
  234. nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  235. smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
  236. sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
  237. if (!nep_res || !smc91x_res || !sa1111_res) {
  238. ret = -ENXIO;
  239. goto err_alloc;
  240. }
  241. d = kzalloc(sizeof(*d), GFP_KERNEL);
  242. if (!d) {
  243. ret = -ENOMEM;
  244. goto err_alloc;
  245. }
  246. d->base = ioremap(nep_res->start, SZ_4K);
  247. if (!d->base) {
  248. ret = -ENOMEM;
  249. goto err_ioremap;
  250. }
  251. if (readb_relaxed(d->base + WHOAMI) != 0x11) {
  252. dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
  253. readb_relaxed(d->base + WHOAMI));
  254. ret = -ENODEV;
  255. goto err_id;
  256. }
  257. ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
  258. if (ret <= 0) {
  259. dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
  260. NEP_IRQ_NR, ret);
  261. if (ret == 0)
  262. ret = -ENOMEM;
  263. goto err_irq_alloc;
  264. }
  265. d->irq_base = ret;
  266. irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
  267. handle_simple_irq);
  268. set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE);
  269. irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
  270. handle_simple_irq);
  271. set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE);
  272. irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
  273. irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
  274. irq_set_handler_data(irq, d);
  275. irq_set_chained_handler(irq, neponset_irq_handler);
  276. /*
  277. * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
  278. * something on the Neponset activates this IRQ on sleep (eth?)
  279. */
  280. #if 0
  281. enable_irq_wake(irq);
  282. #endif
  283. dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
  284. d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
  285. nep_base = d->base;
  286. sa1100_register_uart_fns(&neponset_port_fns);
  287. /* Ensure that the memory bus request/grant signals are setup */
  288. sa1110_mb_disable();
  289. /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
  290. writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
  291. sa1111_resources[0].parent = sa1111_res;
  292. sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
  293. sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
  294. d->sa1111 = platform_device_register_full(&sa1111_devinfo);
  295. smc91x_resources[0].parent = smc91x_res;
  296. smc91x_resources[1].parent = smc91x_res;
  297. smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
  298. smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
  299. d->smc91x = platform_device_register_full(&smc91x_devinfo);
  300. platform_set_drvdata(dev, d);
  301. return 0;
  302. err_irq_alloc:
  303. err_id:
  304. iounmap(d->base);
  305. err_ioremap:
  306. kfree(d);
  307. err_alloc:
  308. return ret;
  309. }
  310. static int __devexit neponset_remove(struct platform_device *dev)
  311. {
  312. struct neponset_drvdata *d = platform_get_drvdata(dev);
  313. int irq = platform_get_irq(dev, 0);
  314. if (!IS_ERR(d->sa1111))
  315. platform_device_unregister(d->sa1111);
  316. if (!IS_ERR(d->smc91x))
  317. platform_device_unregister(d->smc91x);
  318. irq_set_chained_handler(irq, NULL);
  319. irq_free_descs(d->irq_base, NEP_IRQ_NR);
  320. nep_base = NULL;
  321. iounmap(d->base);
  322. kfree(d);
  323. return 0;
  324. }
  325. #ifdef CONFIG_PM_SLEEP
  326. static int neponset_suspend(struct device *dev)
  327. {
  328. struct neponset_drvdata *d = dev_get_drvdata(dev);
  329. d->ncr0 = readb_relaxed(d->base + NCR_0);
  330. d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0);
  331. return 0;
  332. }
  333. static int neponset_resume(struct device *dev)
  334. {
  335. struct neponset_drvdata *d = dev_get_drvdata(dev);
  336. writeb_relaxed(d->ncr0, d->base + NCR_0);
  337. writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0);
  338. return 0;
  339. }
  340. static const struct dev_pm_ops neponset_pm_ops = {
  341. .suspend_noirq = neponset_suspend,
  342. .resume_noirq = neponset_resume,
  343. .freeze_noirq = neponset_suspend,
  344. .restore_noirq = neponset_resume,
  345. };
  346. #define PM_OPS &neponset_pm_ops
  347. #else
  348. #define PM_OPS NULL
  349. #endif
  350. static struct platform_driver neponset_device_driver = {
  351. .probe = neponset_probe,
  352. .remove = __devexit_p(neponset_remove),
  353. .driver = {
  354. .name = "neponset",
  355. .owner = THIS_MODULE,
  356. .pm = PM_OPS,
  357. },
  358. };
  359. static int __init neponset_init(void)
  360. {
  361. return platform_driver_register(&neponset_device_driver);
  362. }
  363. subsys_initcall(neponset_init);