time.h 2.3 KB

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  1. /*
  2. * arch/arm/mach-pnx4008/include/mach/timex.h
  3. *
  4. * PNX4008 timers header file
  5. *
  6. * Author: Dmitry Chigirev <source@mvista.com>
  7. *
  8. * 2005 (c) MontaVista Software, Inc. This file is licensed under
  9. * the terms of the GNU General Public License version 2. This program
  10. * is licensed "as is" without any warranty of any kind, whether express
  11. * or implied.
  12. */
  13. #ifndef PNX_TIME_H
  14. #define PNX_TIME_H
  15. #include <linux/io.h>
  16. #include <mach/hardware.h>
  17. #define TICKS2USECS(x) (x)
  18. /* MilliSecond Timer - Chapter 21 Page 202 */
  19. #define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
  20. #define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
  21. #define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
  22. #define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
  23. #define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
  24. #define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
  25. /* High Speed Timer - Chpater 22, Page 205 */
  26. #define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
  27. #define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
  28. #define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
  29. #define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
  30. #define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
  31. #define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
  32. #define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
  33. #define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
  34. #define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
  35. #define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
  36. #define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
  37. #define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
  38. /* IMPORTANT: both timers are UPCOUNTING */
  39. /* xSTIM_MCTRL bit definitions */
  40. #define MR0_INT 1
  41. #define RESET_COUNT0 (1<<1)
  42. #define STOP_COUNT0 (1<<2)
  43. #define MR1_INT (1<<3)
  44. #define RESET_COUNT1 (1<<4)
  45. #define STOP_COUNT1 (1<<5)
  46. #define MR2_INT (1<<6)
  47. #define RESET_COUNT2 (1<<7)
  48. #define STOP_COUNT2 (1<<8)
  49. /* xSTIM_CTRL bit definitions */
  50. #define COUNT_ENAB 1
  51. #define RESET_COUNT (1<<1)
  52. #define DEBUG_EN (1<<2)
  53. /* xSTIM_INT bit definitions */
  54. #define MATCH0_INT 1
  55. #define MATCH1_INT (1<<1)
  56. #define MATCH2_INT (1<<2)
  57. #define RTC_TICK0 (1<<4)
  58. #define RTC_TICK1 (1<<5)
  59. #endif