addr-map.c 2.2 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091
  1. /*
  2. * arch/arm/mach-kirkwood/addr-map.c
  3. *
  4. * Address map functions for Marvell Kirkwood SoCs
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/mbus.h>
  13. #include <linux/io.h>
  14. #include <mach/hardware.h>
  15. #include <plat/addr-map.h>
  16. #include "common.h"
  17. /*
  18. * Generic Address Decode Windows bit settings
  19. */
  20. #define TARGET_DEV_BUS 1
  21. #define TARGET_SRAM 3
  22. #define TARGET_PCIE 4
  23. #define ATTR_DEV_SPI_ROM 0x1e
  24. #define ATTR_DEV_BOOT 0x1d
  25. #define ATTR_DEV_NAND 0x2f
  26. #define ATTR_DEV_CS3 0x37
  27. #define ATTR_DEV_CS2 0x3b
  28. #define ATTR_DEV_CS1 0x3d
  29. #define ATTR_DEV_CS0 0x3e
  30. #define ATTR_PCIE_IO 0xe0
  31. #define ATTR_PCIE_MEM 0xe8
  32. #define ATTR_PCIE1_IO 0xd0
  33. #define ATTR_PCIE1_MEM 0xd8
  34. #define ATTR_SRAM 0x01
  35. /*
  36. * Description of the windows needed by the platform code
  37. */
  38. static struct __initdata orion_addr_map_cfg addr_map_cfg = {
  39. .num_wins = 8,
  40. .remappable_wins = 4,
  41. .bridge_virt_base = BRIDGE_VIRT_BASE,
  42. };
  43. static const struct __initdata orion_addr_map_info addr_map_info[] = {
  44. /*
  45. * Windows for PCIe IO+MEM space.
  46. */
  47. { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
  48. TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
  49. },
  50. { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
  51. TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
  52. },
  53. { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
  54. TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
  55. },
  56. { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
  57. TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
  58. },
  59. /*
  60. * Window for NAND controller.
  61. */
  62. { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
  63. TARGET_DEV_BUS, ATTR_DEV_NAND, -1
  64. },
  65. /*
  66. * Window for SRAM.
  67. */
  68. { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
  69. TARGET_SRAM, ATTR_SRAM, -1
  70. },
  71. /* End marker */
  72. { -1, 0, 0, 0, 0, 0 }
  73. };
  74. void __init kirkwood_setup_cpu_mbus(void)
  75. {
  76. /*
  77. * Disable, clear and configure windows.
  78. */
  79. orion_config_wins(&addr_map_cfg, addr_map_info);
  80. /*
  81. * Setup MBUS dram target info.
  82. */
  83. orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
  84. }