spi.h 3.1 KB

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  1. /*
  2. * Copyright 2009 Texas Instruments.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. #ifndef __ARCH_ARM_DAVINCI_SPI_H
  19. #define __ARCH_ARM_DAVINCI_SPI_H
  20. #include <mach/edma.h>
  21. #define SPI_INTERN_CS 0xFF
  22. enum {
  23. SPI_VERSION_1, /* For DM355/DM365/DM6467 */
  24. SPI_VERSION_2, /* For DA8xx */
  25. };
  26. /**
  27. * davinci_spi_platform_data - Platform data for SPI master device on DaVinci
  28. *
  29. * @version: version of the SPI IP. Different DaVinci devices have slightly
  30. * varying versions of the same IP.
  31. * @num_chipselect: number of chipselects supported by this SPI master
  32. * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt
  33. * controller withn the SoC. Possible values are 0 and 1.
  34. * @chip_sel: list of GPIOs which can act as chip-selects for the SPI.
  35. * SPI_INTERN_CS denotes internal SPI chip-select. Not necessary
  36. * to populate if all chip-selects are internal.
  37. * @cshold_bug: set this to true if the SPI controller on your chip requires
  38. * a write to CSHOLD bit in between transfers (like in DM355).
  39. * @dma_event_q: DMA event queue to use if SPI_IO_TYPE_DMA is used for any
  40. * device on the bus.
  41. */
  42. struct davinci_spi_platform_data {
  43. u8 version;
  44. u8 num_chipselect;
  45. u8 intr_line;
  46. u8 *chip_sel;
  47. bool cshold_bug;
  48. enum dma_event_q dma_event_q;
  49. };
  50. /**
  51. * davinci_spi_config - Per-chip-select configuration for SPI slave devices
  52. *
  53. * @wdelay: amount of delay between transmissions. Measured in number of
  54. * SPI module clocks.
  55. * @odd_parity: polarity of parity flag at the end of transmit data stream.
  56. * 0 - odd parity, 1 - even parity.
  57. * @parity_enable: enable transmission of parity at end of each transmit
  58. * data stream.
  59. * @io_type: type of IO transfer. Choose between polled, interrupt and DMA.
  60. * @timer_disable: disable chip-select timers (setup and hold)
  61. * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks.
  62. * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks.
  63. * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured
  64. * in number of SPI clocks.
  65. * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in
  66. * number of SPI clocks.
  67. */
  68. struct davinci_spi_config {
  69. u8 wdelay;
  70. u8 odd_parity;
  71. u8 parity_enable;
  72. #define SPI_IO_TYPE_INTR 0
  73. #define SPI_IO_TYPE_POLL 1
  74. #define SPI_IO_TYPE_DMA 2
  75. u8 io_type;
  76. u8 timer_disable;
  77. u8 c2tdelay;
  78. u8 t2cdelay;
  79. u8 t2edelay;
  80. u8 c2edelay;
  81. };
  82. #endif /* __ARCH_ARM_DAVINCI_SPI_H */