dsp_spos_scb_lib.c 48 KB

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  1. /*
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. *
  17. */
  18. /*
  19. * 2002-07 Benny Sjostrand benny@hostmobility.com
  20. */
  21. #include <asm/io.h>
  22. #include <linux/delay.h>
  23. #include <linux/pm.h>
  24. #include <linux/init.h>
  25. #include <linux/slab.h>
  26. #include <linux/mutex.h>
  27. #include <sound/core.h>
  28. #include <sound/control.h>
  29. #include <sound/info.h>
  30. #include <sound/cs46xx.h>
  31. #include "cs46xx_lib.h"
  32. #include "dsp_spos.h"
  33. struct proc_scb_info {
  34. struct dsp_scb_descriptor * scb_desc;
  35. struct snd_cs46xx *chip;
  36. };
  37. static void remove_symbol (struct snd_cs46xx * chip, struct dsp_symbol_entry * symbol)
  38. {
  39. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  40. int symbol_index = (int)(symbol - ins->symbol_table.symbols);
  41. if (snd_BUG_ON(ins->symbol_table.nsymbols <= 0))
  42. return;
  43. if (snd_BUG_ON(symbol_index < 0 ||
  44. symbol_index >= ins->symbol_table.nsymbols))
  45. return;
  46. ins->symbol_table.symbols[symbol_index].deleted = 1;
  47. if (symbol_index < ins->symbol_table.highest_frag_index) {
  48. ins->symbol_table.highest_frag_index = symbol_index;
  49. }
  50. if (symbol_index == ins->symbol_table.nsymbols - 1)
  51. ins->symbol_table.nsymbols --;
  52. if (ins->symbol_table.highest_frag_index > ins->symbol_table.nsymbols) {
  53. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  54. }
  55. }
  56. #ifdef CONFIG_PROC_FS
  57. static void cs46xx_dsp_proc_scb_info_read (struct snd_info_entry *entry,
  58. struct snd_info_buffer *buffer)
  59. {
  60. struct proc_scb_info * scb_info = entry->private_data;
  61. struct dsp_scb_descriptor * scb = scb_info->scb_desc;
  62. struct dsp_spos_instance * ins;
  63. struct snd_cs46xx *chip = scb_info->chip;
  64. int j,col;
  65. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  66. ins = chip->dsp_spos_instance;
  67. mutex_lock(&chip->spos_mutex);
  68. snd_iprintf(buffer,"%04x %s:\n",scb->address,scb->scb_name);
  69. for (col = 0,j = 0;j < 0x10; j++,col++) {
  70. if (col == 4) {
  71. snd_iprintf(buffer,"\n");
  72. col = 0;
  73. }
  74. snd_iprintf(buffer,"%08x ",readl(dst + (scb->address + j) * sizeof(u32)));
  75. }
  76. snd_iprintf(buffer,"\n");
  77. if (scb->parent_scb_ptr != NULL) {
  78. snd_iprintf(buffer,"parent [%s:%04x] ",
  79. scb->parent_scb_ptr->scb_name,
  80. scb->parent_scb_ptr->address);
  81. } else snd_iprintf(buffer,"parent [none] ");
  82. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  83. scb->sub_list_ptr->scb_name,
  84. scb->sub_list_ptr->address,
  85. scb->next_scb_ptr->scb_name,
  86. scb->next_scb_ptr->address,
  87. scb->task_entry->symbol_name,
  88. scb->task_entry->address);
  89. snd_iprintf(buffer,"index [%d] ref_count [%d]\n",scb->index,scb->ref_count);
  90. mutex_unlock(&chip->spos_mutex);
  91. }
  92. #endif
  93. static void _dsp_unlink_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  94. {
  95. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  96. if ( scb->parent_scb_ptr ) {
  97. /* unlink parent SCB */
  98. if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr != scb &&
  99. scb->parent_scb_ptr->next_scb_ptr != scb))
  100. return;
  101. if (scb->parent_scb_ptr->sub_list_ptr == scb) {
  102. if (scb->next_scb_ptr == ins->the_null_scb) {
  103. /* last and only node in parent sublist */
  104. scb->parent_scb_ptr->sub_list_ptr = scb->sub_list_ptr;
  105. if (scb->sub_list_ptr != ins->the_null_scb) {
  106. scb->sub_list_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  107. }
  108. scb->sub_list_ptr = ins->the_null_scb;
  109. } else {
  110. /* first node in parent sublist */
  111. scb->parent_scb_ptr->sub_list_ptr = scb->next_scb_ptr;
  112. if (scb->next_scb_ptr != ins->the_null_scb) {
  113. /* update next node parent ptr. */
  114. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  115. }
  116. scb->next_scb_ptr = ins->the_null_scb;
  117. }
  118. } else {
  119. scb->parent_scb_ptr->next_scb_ptr = scb->next_scb_ptr;
  120. if (scb->next_scb_ptr != ins->the_null_scb) {
  121. /* update next node parent ptr. */
  122. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  123. }
  124. scb->next_scb_ptr = ins->the_null_scb;
  125. }
  126. /* update parent first entry in DSP RAM */
  127. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  128. /* then update entry in DSP RAM */
  129. cs46xx_dsp_spos_update_scb(chip,scb);
  130. scb->parent_scb_ptr = NULL;
  131. }
  132. }
  133. static void _dsp_clear_sample_buffer (struct snd_cs46xx *chip, u32 sample_buffer_addr,
  134. int dword_count)
  135. {
  136. void __iomem *dst = chip->region.idx[2].remap_addr + sample_buffer_addr;
  137. int i;
  138. for (i = 0; i < dword_count ; ++i ) {
  139. writel(0, dst);
  140. dst += 4;
  141. }
  142. }
  143. void cs46xx_dsp_remove_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  144. {
  145. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  146. unsigned long flags;
  147. /* check integrety */
  148. if (snd_BUG_ON(scb->index < 0 ||
  149. scb->index >= ins->nscb ||
  150. (ins->scbs + scb->index) != scb))
  151. return;
  152. #if 0
  153. /* can't remove a SCB with childs before
  154. removing childs first */
  155. if (snd_BUG_ON(scb->sub_list_ptr != ins->the_null_scb ||
  156. scb->next_scb_ptr != ins->the_null_scb))
  157. goto _end;
  158. #endif
  159. spin_lock_irqsave(&chip->reg_lock, flags);
  160. _dsp_unlink_scb (chip,scb);
  161. spin_unlock_irqrestore(&chip->reg_lock, flags);
  162. cs46xx_dsp_proc_free_scb_desc(scb);
  163. if (snd_BUG_ON(!scb->scb_symbol))
  164. return;
  165. remove_symbol (chip,scb->scb_symbol);
  166. ins->scbs[scb->index].deleted = 1;
  167. #ifdef CONFIG_PM
  168. kfree(ins->scbs[scb->index].data);
  169. ins->scbs[scb->index].data = NULL;
  170. #endif
  171. if (scb->index < ins->scb_highest_frag_index)
  172. ins->scb_highest_frag_index = scb->index;
  173. if (scb->index == ins->nscb - 1) {
  174. ins->nscb --;
  175. }
  176. if (ins->scb_highest_frag_index > ins->nscb) {
  177. ins->scb_highest_frag_index = ins->nscb;
  178. }
  179. #if 0
  180. /* !!!! THIS IS A PIECE OF SHIT MADE BY ME !!! */
  181. for(i = scb->index + 1;i < ins->nscb; ++i) {
  182. ins->scbs[i - 1].index = i - 1;
  183. }
  184. #endif
  185. }
  186. #ifdef CONFIG_PROC_FS
  187. void cs46xx_dsp_proc_free_scb_desc (struct dsp_scb_descriptor * scb)
  188. {
  189. if (scb->proc_info) {
  190. struct proc_scb_info * scb_info = scb->proc_info->private_data;
  191. snd_printdd("cs46xx_dsp_proc_free_scb_desc: freeing %s\n",scb->scb_name);
  192. snd_info_free_entry(scb->proc_info);
  193. scb->proc_info = NULL;
  194. kfree (scb_info);
  195. }
  196. }
  197. void cs46xx_dsp_proc_register_scb_desc (struct snd_cs46xx *chip,
  198. struct dsp_scb_descriptor * scb)
  199. {
  200. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  201. struct snd_info_entry * entry;
  202. struct proc_scb_info * scb_info;
  203. /* register to proc */
  204. if (ins->snd_card != NULL && ins->proc_dsp_dir != NULL &&
  205. scb->proc_info == NULL) {
  206. if ((entry = snd_info_create_card_entry(ins->snd_card, scb->scb_name,
  207. ins->proc_dsp_dir)) != NULL) {
  208. scb_info = kmalloc(sizeof(struct proc_scb_info), GFP_KERNEL);
  209. if (!scb_info) {
  210. snd_info_free_entry(entry);
  211. entry = NULL;
  212. goto out;
  213. }
  214. scb_info->chip = chip;
  215. scb_info->scb_desc = scb;
  216. entry->content = SNDRV_INFO_CONTENT_TEXT;
  217. entry->private_data = scb_info;
  218. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  219. entry->c.text.read = cs46xx_dsp_proc_scb_info_read;
  220. if (snd_info_register(entry) < 0) {
  221. snd_info_free_entry(entry);
  222. kfree (scb_info);
  223. entry = NULL;
  224. }
  225. }
  226. out:
  227. scb->proc_info = entry;
  228. }
  229. }
  230. #endif /* CONFIG_PROC_FS */
  231. static struct dsp_scb_descriptor *
  232. _dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest,
  233. struct dsp_symbol_entry * task_entry,
  234. struct dsp_scb_descriptor * parent_scb,
  235. int scb_child_type)
  236. {
  237. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  238. struct dsp_scb_descriptor * scb;
  239. unsigned long flags;
  240. if (snd_BUG_ON(!ins->the_null_scb))
  241. return NULL;
  242. /* fill the data that will be wroten to DSP */
  243. scb_data[SCBsubListPtr] =
  244. (ins->the_null_scb->address << 0x10) | ins->the_null_scb->address;
  245. scb_data[SCBfuncEntryPtr] &= 0xFFFF0000;
  246. scb_data[SCBfuncEntryPtr] |= task_entry->address;
  247. snd_printdd("dsp_spos: creating SCB <%s>\n",name);
  248. scb = cs46xx_dsp_create_scb(chip,name,scb_data,dest);
  249. scb->sub_list_ptr = ins->the_null_scb;
  250. scb->next_scb_ptr = ins->the_null_scb;
  251. scb->parent_scb_ptr = parent_scb;
  252. scb->task_entry = task_entry;
  253. /* update parent SCB */
  254. if (scb->parent_scb_ptr) {
  255. #if 0
  256. printk ("scb->parent_scb_ptr = %s\n",scb->parent_scb_ptr->scb_name);
  257. printk ("scb->parent_scb_ptr->next_scb_ptr = %s\n",scb->parent_scb_ptr->next_scb_ptr->scb_name);
  258. printk ("scb->parent_scb_ptr->sub_list_ptr = %s\n",scb->parent_scb_ptr->sub_list_ptr->scb_name);
  259. #endif
  260. /* link to parent SCB */
  261. if (scb_child_type == SCB_ON_PARENT_NEXT_SCB) {
  262. if (snd_BUG_ON(scb->parent_scb_ptr->next_scb_ptr !=
  263. ins->the_null_scb))
  264. return NULL;
  265. scb->parent_scb_ptr->next_scb_ptr = scb;
  266. } else if (scb_child_type == SCB_ON_PARENT_SUBLIST_SCB) {
  267. if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr !=
  268. ins->the_null_scb))
  269. return NULL;
  270. scb->parent_scb_ptr->sub_list_ptr = scb;
  271. } else {
  272. snd_BUG();
  273. }
  274. spin_lock_irqsave(&chip->reg_lock, flags);
  275. /* update entry in DSP RAM */
  276. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  277. spin_unlock_irqrestore(&chip->reg_lock, flags);
  278. }
  279. cs46xx_dsp_proc_register_scb_desc (chip,scb);
  280. return scb;
  281. }
  282. static struct dsp_scb_descriptor *
  283. cs46xx_dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data,
  284. u32 dest, char * task_entry_name,
  285. struct dsp_scb_descriptor * parent_scb,
  286. int scb_child_type)
  287. {
  288. struct dsp_symbol_entry * task_entry;
  289. task_entry = cs46xx_dsp_lookup_symbol (chip,task_entry_name,
  290. SYMBOL_CODE);
  291. if (task_entry == NULL) {
  292. snd_printk (KERN_ERR "dsp_spos: symbol %s not found\n",task_entry_name);
  293. return NULL;
  294. }
  295. return _dsp_create_generic_scb (chip,name,scb_data,dest,task_entry,
  296. parent_scb,scb_child_type);
  297. }
  298. struct dsp_scb_descriptor *
  299. cs46xx_dsp_create_timing_master_scb (struct snd_cs46xx *chip)
  300. {
  301. struct dsp_scb_descriptor * scb;
  302. struct dsp_timing_master_scb timing_master_scb = {
  303. { 0,
  304. 0,
  305. 0,
  306. 0
  307. },
  308. { 0,
  309. 0,
  310. 0,
  311. 0,
  312. 0
  313. },
  314. 0,0,
  315. 0,NULL_SCB_ADDR,
  316. 0,0, /* extraSampleAccum:TMreserved */
  317. 0,0, /* codecFIFOptr:codecFIFOsyncd */
  318. 0x0001,0x8000, /* fracSampAccumQm1:TMfrmsLeftInGroup */
  319. 0x0001,0x0000, /* fracSampCorrectionQm1:TMfrmGroupLength */
  320. 0x00060000 /* nSampPerFrmQ15 */
  321. };
  322. scb = cs46xx_dsp_create_generic_scb(chip,"TimingMasterSCBInst",(u32 *)&timing_master_scb,
  323. TIMINGMASTER_SCB_ADDR,
  324. "TIMINGMASTER",NULL,SCB_NO_PARENT);
  325. return scb;
  326. }
  327. struct dsp_scb_descriptor *
  328. cs46xx_dsp_create_codec_out_scb(struct snd_cs46xx * chip, char * codec_name,
  329. u16 channel_disp, u16 fifo_addr, u16 child_scb_addr,
  330. u32 dest, struct dsp_scb_descriptor * parent_scb,
  331. int scb_child_type)
  332. {
  333. struct dsp_scb_descriptor * scb;
  334. struct dsp_codec_output_scb codec_out_scb = {
  335. { 0,
  336. 0,
  337. 0,
  338. 0
  339. },
  340. {
  341. 0,
  342. 0,
  343. 0,
  344. 0,
  345. 0
  346. },
  347. 0,0,
  348. 0,NULL_SCB_ADDR,
  349. 0, /* COstrmRsConfig */
  350. 0, /* COstrmBufPtr */
  351. channel_disp,fifo_addr, /* leftChanBaseIOaddr:rightChanIOdisp */
  352. 0x0000,0x0080, /* (!AC97!) COexpVolChangeRate:COscaleShiftCount */
  353. 0,child_scb_addr /* COreserved - need child scb to work with rom code */
  354. };
  355. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_out_scb,
  356. dest,"S16_CODECOUTPUTTASK",parent_scb,
  357. scb_child_type);
  358. return scb;
  359. }
  360. struct dsp_scb_descriptor *
  361. cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip, char * codec_name,
  362. u16 channel_disp, u16 fifo_addr, u16 sample_buffer_addr,
  363. u32 dest, struct dsp_scb_descriptor * parent_scb,
  364. int scb_child_type)
  365. {
  366. struct dsp_scb_descriptor * scb;
  367. struct dsp_codec_input_scb codec_input_scb = {
  368. { 0,
  369. 0,
  370. 0,
  371. 0
  372. },
  373. {
  374. 0,
  375. 0,
  376. 0,
  377. 0,
  378. 0
  379. },
  380. #if 0 /* cs4620 */
  381. SyncIOSCB,NULL_SCB_ADDR
  382. #else
  383. 0 , 0,
  384. #endif
  385. 0,0,
  386. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64, /* strmRsConfig */
  387. sample_buffer_addr << 0x10, /* strmBufPtr; defined as a dword ptr, used as a byte ptr */
  388. channel_disp,fifo_addr, /* (!AC97!) leftChanBaseINaddr=AC97primary
  389. link input slot 3 :rightChanINdisp=""slot 4 */
  390. 0x0000,0x0000, /* (!AC97!) ????:scaleShiftCount; no shift needed
  391. because AC97 is already 20 bits */
  392. 0x80008000 /* ??clw cwcgame.scb has 0 */
  393. };
  394. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_input_scb,
  395. dest,"S16_CODECINPUTTASK",parent_scb,
  396. scb_child_type);
  397. return scb;
  398. }
  399. static struct dsp_scb_descriptor *
  400. cs46xx_dsp_create_pcm_reader_scb(struct snd_cs46xx * chip, char * scb_name,
  401. u16 sample_buffer_addr, u32 dest,
  402. int virtual_channel, u32 playback_hw_addr,
  403. struct dsp_scb_descriptor * parent_scb,
  404. int scb_child_type)
  405. {
  406. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  407. struct dsp_scb_descriptor * scb;
  408. struct dsp_generic_scb pcm_reader_scb = {
  409. /*
  410. Play DMA Task xfers data from host buffer to SP buffer
  411. init/runtime variables:
  412. PlayAC: Play Audio Data Conversion - SCB loc: 2nd dword, mask: 0x0000F000L
  413. DATA_FMT_16BIT_ST_LTLEND(0x00000000L) from 16-bit stereo, little-endian
  414. DATA_FMT_8_BIT_ST_SIGNED(0x00001000L) from 8-bit stereo, signed
  415. DATA_FMT_16BIT_MN_LTLEND(0x00002000L) from 16-bit mono, little-endian
  416. DATA_FMT_8_BIT_MN_SIGNED(0x00003000L) from 8-bit mono, signed
  417. DATA_FMT_16BIT_ST_BIGEND(0x00004000L) from 16-bit stereo, big-endian
  418. DATA_FMT_16BIT_MN_BIGEND(0x00006000L) from 16-bit mono, big-endian
  419. DATA_FMT_8_BIT_ST_UNSIGNED(0x00009000L) from 8-bit stereo, unsigned
  420. DATA_FMT_8_BIT_MN_UNSIGNED(0x0000b000L) from 8-bit mono, unsigned
  421. ? Other combinations possible from:
  422. DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L
  423. DMA_RQ_C2_AC_NONE 0x00000000L
  424. DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L
  425. DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L
  426. DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L
  427. DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L
  428. HostBuffAddr: Host Buffer Physical Byte Address - SCB loc:3rd dword, Mask: 0xFFFFFFFFL
  429. aligned to dword boundary
  430. */
  431. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  432. { DMA_RQ_C1_SOURCE_ON_HOST + /* source buffer is on the host */
  433. DMA_RQ_C1_SOURCE_MOD1024 + /* source buffer is 1024 dwords (4096 bytes) */
  434. DMA_RQ_C1_DEST_MOD32 + /* dest buffer(PCMreaderBuf) is 32 dwords*/
  435. DMA_RQ_C1_WRITEBACK_SRC_FLAG + /* ?? */
  436. DMA_RQ_C1_WRITEBACK_DEST_FLAG + /* ?? */
  437. 15, /* DwordCount-1: picked 16 for DwordCount because Jim */
  438. /* Barnette said that is what we should use since */
  439. /* we are not running in optimized mode? */
  440. DMA_RQ_C2_AC_NONE +
  441. DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG + /* set play interrupt (bit0) in HISR when source */
  442. /* buffer (on host) crosses half-way point */
  443. virtual_channel, /* Play DMA channel arbitrarily set to 0 */
  444. playback_hw_addr, /* HostBuffAddr (source) */
  445. DMA_RQ_SD_SP_SAMPLE_ADDR + /* destination buffer is in SP Sample Memory */
  446. sample_buffer_addr /* SP Buffer Address (destination) */
  447. },
  448. /* Scatter/gather DMA requestor extension (5 ints) */
  449. {
  450. 0,
  451. 0,
  452. 0,
  453. 0,
  454. 0
  455. },
  456. /* Sublist pointer & next stream control block (SCB) link. */
  457. NULL_SCB_ADDR,NULL_SCB_ADDR,
  458. /* Pointer to this tasks parameter block & stream function pointer */
  459. 0,NULL_SCB_ADDR,
  460. /* rsConfig register for stream buffer (rsDMA reg. is loaded from basicReq.daw */
  461. /* for incoming streams, or basicReq.saw, for outgoing streams) */
  462. RSCONFIG_DMA_ENABLE + /* enable DMA */
  463. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) + /* MAX_DMA_SIZE picked to be 19 since SPUD */
  464. /* uses it for some reason */
  465. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) + /* stream number = SCBaddr/16 */
  466. RSCONFIG_SAMPLE_16STEREO +
  467. RSCONFIG_MODULO_32, /* dest buffer(PCMreaderBuf) is 32 dwords (256 bytes) */
  468. /* Stream sample pointer & MAC-unit mode for this stream */
  469. (sample_buffer_addr << 0x10),
  470. /* Fractional increment per output sample in the input sample buffer */
  471. 0,
  472. {
  473. /* Standard stereo volume control
  474. default muted */
  475. 0xffff,0xffff,
  476. 0xffff,0xffff
  477. }
  478. };
  479. if (ins->null_algorithm == NULL) {
  480. ins->null_algorithm = cs46xx_dsp_lookup_symbol (chip,"NULLALGORITHM",
  481. SYMBOL_CODE);
  482. if (ins->null_algorithm == NULL) {
  483. snd_printk (KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  484. return NULL;
  485. }
  486. }
  487. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_reader_scb,
  488. dest,ins->null_algorithm,parent_scb,
  489. scb_child_type);
  490. return scb;
  491. }
  492. #define GOF_PER_SEC 200
  493. struct dsp_scb_descriptor *
  494. cs46xx_dsp_create_src_task_scb(struct snd_cs46xx * chip, char * scb_name,
  495. int rate,
  496. u16 src_buffer_addr,
  497. u16 src_delay_buffer_addr, u32 dest,
  498. struct dsp_scb_descriptor * parent_scb,
  499. int scb_child_type,
  500. int pass_through)
  501. {
  502. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  503. struct dsp_scb_descriptor * scb;
  504. unsigned int tmp1, tmp2;
  505. unsigned int phiIncr;
  506. unsigned int correctionPerGOF, correctionPerSec;
  507. snd_printdd( "dsp_spos: setting %s rate to %u\n",scb_name,rate);
  508. /*
  509. * Compute the values used to drive the actual sample rate conversion.
  510. * The following formulas are being computed, using inline assembly
  511. * since we need to use 64 bit arithmetic to compute the values:
  512. *
  513. * phiIncr = floor((Fs,in * 2^26) / Fs,out)
  514. * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
  515. * GOF_PER_SEC)
  516. * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
  517. * GOF_PER_SEC * correctionPerGOF
  518. *
  519. * i.e.
  520. *
  521. * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
  522. * correctionPerGOF:correctionPerSec =
  523. * dividend:remainder(ulOther / GOF_PER_SEC)
  524. */
  525. tmp1 = rate << 16;
  526. phiIncr = tmp1 / 48000;
  527. tmp1 -= phiIncr * 48000;
  528. tmp1 <<= 10;
  529. phiIncr <<= 10;
  530. tmp2 = tmp1 / 48000;
  531. phiIncr += tmp2;
  532. tmp1 -= tmp2 * 48000;
  533. correctionPerGOF = tmp1 / GOF_PER_SEC;
  534. tmp1 -= correctionPerGOF * GOF_PER_SEC;
  535. correctionPerSec = tmp1;
  536. {
  537. struct dsp_src_task_scb src_task_scb = {
  538. 0x0028,0x00c8,
  539. 0x5555,0x0000,
  540. 0x0000,0x0000,
  541. src_buffer_addr,1,
  542. correctionPerGOF,correctionPerSec,
  543. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  544. 0x0000,src_delay_buffer_addr,
  545. 0x0,
  546. 0x080,(src_delay_buffer_addr + (24 * 4)),
  547. 0,0, /* next_scb, sub_list_ptr */
  548. 0,0, /* entry, this_spb */
  549. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  550. src_buffer_addr << 0x10,
  551. phiIncr,
  552. {
  553. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left,
  554. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left
  555. }
  556. };
  557. if (ins->s16_up == NULL) {
  558. ins->s16_up = cs46xx_dsp_lookup_symbol (chip,"S16_UPSRC",
  559. SYMBOL_CODE);
  560. if (ins->s16_up == NULL) {
  561. snd_printk (KERN_ERR "dsp_spos: symbol S16_UPSRC not found\n");
  562. return NULL;
  563. }
  564. }
  565. /* clear buffers */
  566. _dsp_clear_sample_buffer (chip,src_buffer_addr,8);
  567. _dsp_clear_sample_buffer (chip,src_delay_buffer_addr,32);
  568. if (pass_through) {
  569. /* wont work with any other rate than
  570. the native DSP rate */
  571. snd_BUG_ON(rate != 48000);
  572. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  573. dest,"DMAREADER",parent_scb,
  574. scb_child_type);
  575. } else {
  576. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  577. dest,ins->s16_up,parent_scb,
  578. scb_child_type);
  579. }
  580. }
  581. return scb;
  582. }
  583. #if 0 /* not used */
  584. struct dsp_scb_descriptor *
  585. cs46xx_dsp_create_filter_scb(struct snd_cs46xx * chip, char * scb_name,
  586. u16 buffer_addr, u32 dest,
  587. struct dsp_scb_descriptor * parent_scb,
  588. int scb_child_type) {
  589. struct dsp_scb_descriptor * scb;
  590. struct dsp_filter_scb filter_scb = {
  591. .a0_right = 0x41a9,
  592. .a0_left = 0x41a9,
  593. .a1_right = 0xb8e4,
  594. .a1_left = 0xb8e4,
  595. .a2_right = 0x3e55,
  596. .a2_left = 0x3e55,
  597. .filter_unused3 = 0x0000,
  598. .filter_unused2 = 0x0000,
  599. .output_buf_ptr = buffer_addr,
  600. .init = 0x000,
  601. .prev_sample_output1 = 0x00000000,
  602. .prev_sample_output2 = 0x00000000,
  603. .prev_sample_input1 = 0x00000000,
  604. .prev_sample_input2 = 0x00000000,
  605. .next_scb_ptr = 0x0000,
  606. .sub_list_ptr = 0x0000,
  607. .entry_point = 0x0000,
  608. .spb_ptr = 0x0000,
  609. .b0_right = 0x0e38,
  610. .b0_left = 0x0e38,
  611. .b1_right = 0x1c71,
  612. .b1_left = 0x1c71,
  613. .b2_right = 0x0e38,
  614. .b2_left = 0x0e38,
  615. };
  616. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&filter_scb,
  617. dest,"FILTERTASK",parent_scb,
  618. scb_child_type);
  619. return scb;
  620. }
  621. #endif /* not used */
  622. struct dsp_scb_descriptor *
  623. cs46xx_dsp_create_mix_only_scb(struct snd_cs46xx * chip, char * scb_name,
  624. u16 mix_buffer_addr, u32 dest,
  625. struct dsp_scb_descriptor * parent_scb,
  626. int scb_child_type)
  627. {
  628. struct dsp_scb_descriptor * scb;
  629. struct dsp_mix_only_scb master_mix_scb = {
  630. /* 0 */ { 0,
  631. /* 1 */ 0,
  632. /* 2 */ mix_buffer_addr,
  633. /* 3 */ 0
  634. /* */ },
  635. {
  636. /* 4 */ 0,
  637. /* 5 */ 0,
  638. /* 6 */ 0,
  639. /* 7 */ 0,
  640. /* 8 */ 0x00000080
  641. },
  642. /* 9 */ 0,0,
  643. /* A */ 0,0,
  644. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  645. /* C */ (mix_buffer_addr + (16 * 4)) << 0x10,
  646. /* D */ 0,
  647. {
  648. /* E */ 0x8000,0x8000,
  649. /* F */ 0x8000,0x8000
  650. }
  651. };
  652. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&master_mix_scb,
  653. dest,"S16_MIX",parent_scb,
  654. scb_child_type);
  655. return scb;
  656. }
  657. struct dsp_scb_descriptor *
  658. cs46xx_dsp_create_mix_to_ostream_scb(struct snd_cs46xx * chip, char * scb_name,
  659. u16 mix_buffer_addr, u16 writeback_spb, u32 dest,
  660. struct dsp_scb_descriptor * parent_scb,
  661. int scb_child_type)
  662. {
  663. struct dsp_scb_descriptor * scb;
  664. struct dsp_mix2_ostream_scb mix2_ostream_scb = {
  665. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  666. {
  667. DMA_RQ_C1_SOURCE_MOD64 +
  668. DMA_RQ_C1_DEST_ON_HOST +
  669. DMA_RQ_C1_DEST_MOD1024 +
  670. DMA_RQ_C1_WRITEBACK_SRC_FLAG +
  671. DMA_RQ_C1_WRITEBACK_DEST_FLAG +
  672. 15,
  673. DMA_RQ_C2_AC_NONE +
  674. DMA_RQ_C2_SIGNAL_DEST_PINGPONG +
  675. CS46XX_DSP_CAPTURE_CHANNEL,
  676. DMA_RQ_SD_SP_SAMPLE_ADDR +
  677. mix_buffer_addr,
  678. 0x0
  679. },
  680. { 0, 0, 0, 0, 0, },
  681. 0,0,
  682. 0,writeback_spb,
  683. RSCONFIG_DMA_ENABLE +
  684. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) +
  685. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) +
  686. RSCONFIG_DMA_TO_HOST +
  687. RSCONFIG_SAMPLE_16STEREO +
  688. RSCONFIG_MODULO_64,
  689. (mix_buffer_addr + (32 * 4)) << 0x10,
  690. 1,0,
  691. 0x0001,0x0080,
  692. 0xFFFF,0
  693. };
  694. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&mix2_ostream_scb,
  695. dest,"S16_MIX_TO_OSTREAM",parent_scb,
  696. scb_child_type);
  697. return scb;
  698. }
  699. struct dsp_scb_descriptor *
  700. cs46xx_dsp_create_vari_decimate_scb(struct snd_cs46xx * chip,char * scb_name,
  701. u16 vari_buffer_addr0,
  702. u16 vari_buffer_addr1,
  703. u32 dest,
  704. struct dsp_scb_descriptor * parent_scb,
  705. int scb_child_type)
  706. {
  707. struct dsp_scb_descriptor * scb;
  708. struct dsp_vari_decimate_scb vari_decimate_scb = {
  709. 0x0028,0x00c8,
  710. 0x5555,0x0000,
  711. 0x0000,0x0000,
  712. vari_buffer_addr0,vari_buffer_addr1,
  713. 0x0028,0x00c8,
  714. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256,
  715. 0xFF800000,
  716. 0,
  717. 0x0080,vari_buffer_addr1 + (25 * 4),
  718. 0,0,
  719. 0,0,
  720. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  721. vari_buffer_addr0 << 0x10,
  722. 0x04000000,
  723. {
  724. 0x8000,0x8000,
  725. 0xFFFF,0xFFFF
  726. }
  727. };
  728. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&vari_decimate_scb,
  729. dest,"VARIDECIMATE",parent_scb,
  730. scb_child_type);
  731. return scb;
  732. }
  733. static struct dsp_scb_descriptor *
  734. cs46xx_dsp_create_pcm_serial_input_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  735. struct dsp_scb_descriptor * input_scb,
  736. struct dsp_scb_descriptor * parent_scb,
  737. int scb_child_type)
  738. {
  739. struct dsp_scb_descriptor * scb;
  740. struct dsp_pcm_serial_input_scb pcm_serial_input_scb = {
  741. { 0,
  742. 0,
  743. 0,
  744. 0
  745. },
  746. {
  747. 0,
  748. 0,
  749. 0,
  750. 0,
  751. 0
  752. },
  753. 0,0,
  754. 0,0,
  755. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_16,
  756. 0,
  757. /* 0xD */ 0,input_scb->address,
  758. {
  759. /* 0xE */ 0x8000,0x8000,
  760. /* 0xF */ 0x8000,0x8000
  761. }
  762. };
  763. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_serial_input_scb,
  764. dest,"PCMSERIALINPUTTASK",parent_scb,
  765. scb_child_type);
  766. return scb;
  767. }
  768. static struct dsp_scb_descriptor *
  769. cs46xx_dsp_create_asynch_fg_tx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  770. u16 hfg_scb_address,
  771. u16 asynch_buffer_address,
  772. struct dsp_scb_descriptor * parent_scb,
  773. int scb_child_type)
  774. {
  775. struct dsp_scb_descriptor * scb;
  776. struct dsp_asynch_fg_tx_scb asynch_fg_tx_scb = {
  777. 0xfc00,0x03ff, /* Prototype sample buffer size of 256 dwords */
  778. 0x0058,0x0028, /* Min Delta 7 dwords == 28 bytes */
  779. /* : Max delta 25 dwords == 100 bytes */
  780. 0,hfg_scb_address, /* Point to HFG task SCB */
  781. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  782. 0, /* Initialize accumulated Phi to 0 */
  783. 0,0x2aab, /* Const 1/3 */
  784. {
  785. 0, /* Define the unused elements */
  786. 0,
  787. 0
  788. },
  789. 0,0,
  790. 0,dest + AFGTxAccumPhi,
  791. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256, /* Stereo, 256 dword */
  792. (asynch_buffer_address) << 0x10, /* This should be automagically synchronized
  793. to the producer pointer */
  794. /* There is no correct initial value, it will depend upon the detected
  795. rate etc */
  796. 0x18000000, /* Phi increment for approx 32k operation */
  797. 0x8000,0x8000, /* Volume controls are unused at this time */
  798. 0x8000,0x8000
  799. };
  800. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_tx_scb,
  801. dest,"ASYNCHFGTXCODE",parent_scb,
  802. scb_child_type);
  803. return scb;
  804. }
  805. struct dsp_scb_descriptor *
  806. cs46xx_dsp_create_asynch_fg_rx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  807. u16 hfg_scb_address,
  808. u16 asynch_buffer_address,
  809. struct dsp_scb_descriptor * parent_scb,
  810. int scb_child_type)
  811. {
  812. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  813. struct dsp_scb_descriptor * scb;
  814. struct dsp_asynch_fg_rx_scb asynch_fg_rx_scb = {
  815. 0xfe00,0x01ff, /* Prototype sample buffer size of 128 dwords */
  816. 0x0064,0x001c, /* Min Delta 7 dwords == 28 bytes */
  817. /* : Max delta 25 dwords == 100 bytes */
  818. 0,hfg_scb_address, /* Point to HFG task SCB */
  819. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  820. {
  821. 0, /* Define the unused elements */
  822. 0,
  823. 0,
  824. 0,
  825. 0
  826. },
  827. 0,0,
  828. 0,dest,
  829. RSCONFIG_MODULO_128 |
  830. RSCONFIG_SAMPLE_16STEREO, /* Stereo, 128 dword */
  831. ( (asynch_buffer_address + (16 * 4)) << 0x10), /* This should be automagically
  832. synchrinized to the producer pointer */
  833. /* There is no correct initial value, it will depend upon the detected
  834. rate etc */
  835. 0x18000000,
  836. /* Set IEC958 input volume */
  837. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  838. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  839. };
  840. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_rx_scb,
  841. dest,"ASYNCHFGRXCODE",parent_scb,
  842. scb_child_type);
  843. return scb;
  844. }
  845. #if 0 /* not used */
  846. struct dsp_scb_descriptor *
  847. cs46xx_dsp_create_output_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  848. u16 snoop_buffer_address,
  849. struct dsp_scb_descriptor * snoop_scb,
  850. struct dsp_scb_descriptor * parent_scb,
  851. int scb_child_type)
  852. {
  853. struct dsp_scb_descriptor * scb;
  854. struct dsp_output_snoop_scb output_snoop_scb = {
  855. { 0, /* not used. Zero */
  856. 0,
  857. 0,
  858. 0,
  859. },
  860. {
  861. 0, /* not used. Zero */
  862. 0,
  863. 0,
  864. 0,
  865. 0
  866. },
  867. 0,0,
  868. 0,0,
  869. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  870. snoop_buffer_address << 0x10,
  871. 0,0,
  872. 0,
  873. 0,snoop_scb->address
  874. };
  875. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&output_snoop_scb,
  876. dest,"OUTPUTSNOOP",parent_scb,
  877. scb_child_type);
  878. return scb;
  879. }
  880. #endif /* not used */
  881. struct dsp_scb_descriptor *
  882. cs46xx_dsp_create_spio_write_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  883. struct dsp_scb_descriptor * parent_scb,
  884. int scb_child_type)
  885. {
  886. struct dsp_scb_descriptor * scb;
  887. struct dsp_spio_write_scb spio_write_scb = {
  888. 0,0, /* SPIOWAddress2:SPIOWAddress1; */
  889. 0, /* SPIOWData1; */
  890. 0, /* SPIOWData2; */
  891. 0,0, /* SPIOWAddress4:SPIOWAddress3; */
  892. 0, /* SPIOWData3; */
  893. 0, /* SPIOWData4; */
  894. 0,0, /* SPIOWDataPtr:Unused1; */
  895. { 0,0 }, /* Unused2[2]; */
  896. 0,0, /* SPIOWChildPtr:SPIOWSiblingPtr; */
  897. 0,0, /* SPIOWThisPtr:SPIOWEntryPoint; */
  898. {
  899. 0,
  900. 0,
  901. 0,
  902. 0,
  903. 0 /* Unused3[5]; */
  904. }
  905. };
  906. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&spio_write_scb,
  907. dest,"SPIOWRITE",parent_scb,
  908. scb_child_type);
  909. return scb;
  910. }
  911. struct dsp_scb_descriptor *
  912. cs46xx_dsp_create_magic_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  913. u16 snoop_buffer_address,
  914. struct dsp_scb_descriptor * snoop_scb,
  915. struct dsp_scb_descriptor * parent_scb,
  916. int scb_child_type)
  917. {
  918. struct dsp_scb_descriptor * scb;
  919. struct dsp_magic_snoop_task magic_snoop_scb = {
  920. /* 0 */ 0, /* i0 */
  921. /* 1 */ 0, /* i1 */
  922. /* 2 */ snoop_buffer_address << 0x10,
  923. /* 3 */ 0,snoop_scb->address,
  924. /* 4 */ 0, /* i3 */
  925. /* 5 */ 0, /* i4 */
  926. /* 6 */ 0, /* i5 */
  927. /* 7 */ 0, /* i6 */
  928. /* 8 */ 0, /* i7 */
  929. /* 9 */ 0,0, /* next_scb, sub_list_ptr */
  930. /* A */ 0,0, /* entry_point, this_ptr */
  931. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  932. /* C */ snoop_buffer_address << 0x10,
  933. /* D */ 0,
  934. /* E */ { 0x8000,0x8000,
  935. /* F */ 0xffff,0xffff
  936. }
  937. };
  938. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&magic_snoop_scb,
  939. dest,"MAGICSNOOPTASK",parent_scb,
  940. scb_child_type);
  941. return scb;
  942. }
  943. static struct dsp_scb_descriptor *
  944. find_next_free_scb (struct snd_cs46xx * chip, struct dsp_scb_descriptor * from)
  945. {
  946. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  947. struct dsp_scb_descriptor * scb = from;
  948. while (scb->next_scb_ptr != ins->the_null_scb) {
  949. if (snd_BUG_ON(!scb->next_scb_ptr))
  950. return NULL;
  951. scb = scb->next_scb_ptr;
  952. }
  953. return scb;
  954. }
  955. static u32 pcm_reader_buffer_addr[DSP_MAX_PCM_CHANNELS] = {
  956. 0x0600, /* 1 */
  957. 0x1500, /* 2 */
  958. 0x1580, /* 3 */
  959. 0x1600, /* 4 */
  960. 0x1680, /* 5 */
  961. 0x1700, /* 6 */
  962. 0x1780, /* 7 */
  963. 0x1800, /* 8 */
  964. 0x1880, /* 9 */
  965. 0x1900, /* 10 */
  966. 0x1980, /* 11 */
  967. 0x1A00, /* 12 */
  968. 0x1A80, /* 13 */
  969. 0x1B00, /* 14 */
  970. 0x1B80, /* 15 */
  971. 0x1C00, /* 16 */
  972. 0x1C80, /* 17 */
  973. 0x1D00, /* 18 */
  974. 0x1D80, /* 19 */
  975. 0x1E00, /* 20 */
  976. 0x1E80, /* 21 */
  977. 0x1F00, /* 22 */
  978. 0x1F80, /* 23 */
  979. 0x2000, /* 24 */
  980. 0x2080, /* 25 */
  981. 0x2100, /* 26 */
  982. 0x2180, /* 27 */
  983. 0x2200, /* 28 */
  984. 0x2280, /* 29 */
  985. 0x2300, /* 30 */
  986. 0x2380, /* 31 */
  987. 0x2400, /* 32 */
  988. };
  989. static u32 src_output_buffer_addr[DSP_MAX_SRC_NR] = {
  990. 0x2B80,
  991. 0x2BA0,
  992. 0x2BC0,
  993. 0x2BE0,
  994. 0x2D00,
  995. 0x2D20,
  996. 0x2D40,
  997. 0x2D60,
  998. 0x2D80,
  999. 0x2DA0,
  1000. 0x2DC0,
  1001. 0x2DE0,
  1002. 0x2E00,
  1003. 0x2E20
  1004. };
  1005. static u32 src_delay_buffer_addr[DSP_MAX_SRC_NR] = {
  1006. 0x2480,
  1007. 0x2500,
  1008. 0x2580,
  1009. 0x2600,
  1010. 0x2680,
  1011. 0x2700,
  1012. 0x2780,
  1013. 0x2800,
  1014. 0x2880,
  1015. 0x2900,
  1016. 0x2980,
  1017. 0x2A00,
  1018. 0x2A80,
  1019. 0x2B00
  1020. };
  1021. struct dsp_pcm_channel_descriptor *
  1022. cs46xx_dsp_create_pcm_channel (struct snd_cs46xx * chip,
  1023. u32 sample_rate, void * private_data,
  1024. u32 hw_dma_addr,
  1025. int pcm_channel_id)
  1026. {
  1027. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1028. struct dsp_scb_descriptor * src_scb = NULL, * pcm_scb, * mixer_scb = NULL;
  1029. struct dsp_scb_descriptor * src_parent_scb = NULL;
  1030. /* struct dsp_scb_descriptor * pcm_parent_scb; */
  1031. char scb_name[DSP_MAX_SCB_NAME];
  1032. int i, pcm_index = -1, insert_point, src_index = -1, pass_through = 0;
  1033. unsigned long flags;
  1034. switch (pcm_channel_id) {
  1035. case DSP_PCM_MAIN_CHANNEL:
  1036. mixer_scb = ins->master_mix_scb;
  1037. break;
  1038. case DSP_PCM_REAR_CHANNEL:
  1039. mixer_scb = ins->rear_mix_scb;
  1040. break;
  1041. case DSP_PCM_CENTER_LFE_CHANNEL:
  1042. mixer_scb = ins->center_lfe_mix_scb;
  1043. break;
  1044. case DSP_PCM_S71_CHANNEL:
  1045. /* TODO */
  1046. snd_BUG();
  1047. break;
  1048. case DSP_IEC958_CHANNEL:
  1049. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1050. return NULL;
  1051. mixer_scb = ins->asynch_tx_scb;
  1052. /* if sample rate is set to 48khz we pass
  1053. the Sample Rate Converted (which could
  1054. alter the raw data stream ...) */
  1055. if (sample_rate == 48000) {
  1056. snd_printdd ("IEC958 pass through\n");
  1057. /* Hack to bypass creating a new SRC */
  1058. pass_through = 1;
  1059. }
  1060. break;
  1061. default:
  1062. snd_BUG();
  1063. return NULL;
  1064. }
  1065. /* default sample rate is 44100 */
  1066. if (!sample_rate) sample_rate = 44100;
  1067. /* search for a already created SRC SCB with the same sample rate */
  1068. for (i = 0; i < DSP_MAX_PCM_CHANNELS &&
  1069. (pcm_index == -1 || src_scb == NULL); ++i) {
  1070. /* virtual channel reserved
  1071. for capture */
  1072. if (i == CS46XX_DSP_CAPTURE_CHANNEL) continue;
  1073. if (ins->pcm_channels[i].active) {
  1074. if (!src_scb &&
  1075. ins->pcm_channels[i].sample_rate == sample_rate &&
  1076. ins->pcm_channels[i].mixer_scb == mixer_scb) {
  1077. src_scb = ins->pcm_channels[i].src_scb;
  1078. ins->pcm_channels[i].src_scb->ref_count ++;
  1079. src_index = ins->pcm_channels[i].src_slot;
  1080. }
  1081. } else if (pcm_index == -1) {
  1082. pcm_index = i;
  1083. }
  1084. }
  1085. if (pcm_index == -1) {
  1086. snd_printk (KERN_ERR "dsp_spos: no free PCM channel\n");
  1087. return NULL;
  1088. }
  1089. if (src_scb == NULL) {
  1090. if (ins->nsrc_scb >= DSP_MAX_SRC_NR) {
  1091. snd_printk(KERN_ERR "dsp_spos: to many SRC instances\n!");
  1092. return NULL;
  1093. }
  1094. /* find a free slot */
  1095. for (i = 0; i < DSP_MAX_SRC_NR; ++i) {
  1096. if (ins->src_scb_slots[i] == 0) {
  1097. src_index = i;
  1098. ins->src_scb_slots[i] = 1;
  1099. break;
  1100. }
  1101. }
  1102. if (snd_BUG_ON(src_index == -1))
  1103. return NULL;
  1104. /* we need to create a new SRC SCB */
  1105. if (mixer_scb->sub_list_ptr == ins->the_null_scb) {
  1106. src_parent_scb = mixer_scb;
  1107. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1108. } else {
  1109. src_parent_scb = find_next_free_scb(chip,mixer_scb->sub_list_ptr);
  1110. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1111. }
  1112. snprintf (scb_name,DSP_MAX_SCB_NAME,"SrcTask_SCB%d",src_index);
  1113. snd_printdd( "dsp_spos: creating SRC \"%s\"\n",scb_name);
  1114. src_scb = cs46xx_dsp_create_src_task_scb(chip,scb_name,
  1115. sample_rate,
  1116. src_output_buffer_addr[src_index],
  1117. src_delay_buffer_addr[src_index],
  1118. /* 0x400 - 0x600 source SCBs */
  1119. 0x400 + (src_index * 0x10) ,
  1120. src_parent_scb,
  1121. insert_point,
  1122. pass_through);
  1123. if (!src_scb) {
  1124. snd_printk (KERN_ERR "dsp_spos: failed to create SRCtaskSCB\n");
  1125. return NULL;
  1126. }
  1127. /* cs46xx_dsp_set_src_sample_rate(chip,src_scb,sample_rate); */
  1128. ins->nsrc_scb ++;
  1129. }
  1130. snprintf (scb_name,DSP_MAX_SCB_NAME,"PCMReader_SCB%d",pcm_index);
  1131. snd_printdd( "dsp_spos: creating PCM \"%s\" (%d)\n",scb_name,
  1132. pcm_channel_id);
  1133. pcm_scb = cs46xx_dsp_create_pcm_reader_scb(chip,scb_name,
  1134. pcm_reader_buffer_addr[pcm_index],
  1135. /* 0x200 - 400 PCMreader SCBs */
  1136. (pcm_index * 0x10) + 0x200,
  1137. pcm_index, /* virtual channel 0-31 */
  1138. hw_dma_addr, /* pcm hw addr */
  1139. NULL, /* parent SCB ptr */
  1140. 0 /* insert point */
  1141. );
  1142. if (!pcm_scb) {
  1143. snd_printk (KERN_ERR "dsp_spos: failed to create PCMreaderSCB\n");
  1144. return NULL;
  1145. }
  1146. spin_lock_irqsave(&chip->reg_lock, flags);
  1147. ins->pcm_channels[pcm_index].sample_rate = sample_rate;
  1148. ins->pcm_channels[pcm_index].pcm_reader_scb = pcm_scb;
  1149. ins->pcm_channels[pcm_index].src_scb = src_scb;
  1150. ins->pcm_channels[pcm_index].unlinked = 1;
  1151. ins->pcm_channels[pcm_index].private_data = private_data;
  1152. ins->pcm_channels[pcm_index].src_slot = src_index;
  1153. ins->pcm_channels[pcm_index].active = 1;
  1154. ins->pcm_channels[pcm_index].pcm_slot = pcm_index;
  1155. ins->pcm_channels[pcm_index].mixer_scb = mixer_scb;
  1156. ins->npcm_channels ++;
  1157. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1158. return (ins->pcm_channels + pcm_index);
  1159. }
  1160. int cs46xx_dsp_pcm_channel_set_period (struct snd_cs46xx * chip,
  1161. struct dsp_pcm_channel_descriptor * pcm_channel,
  1162. int period_size)
  1163. {
  1164. u32 temp = snd_cs46xx_peek (chip,pcm_channel->pcm_reader_scb->address << 2);
  1165. temp &= ~DMA_RQ_C1_SOURCE_SIZE_MASK;
  1166. switch (period_size) {
  1167. case 2048:
  1168. temp |= DMA_RQ_C1_SOURCE_MOD1024;
  1169. break;
  1170. case 1024:
  1171. temp |= DMA_RQ_C1_SOURCE_MOD512;
  1172. break;
  1173. case 512:
  1174. temp |= DMA_RQ_C1_SOURCE_MOD256;
  1175. break;
  1176. case 256:
  1177. temp |= DMA_RQ_C1_SOURCE_MOD128;
  1178. break;
  1179. case 128:
  1180. temp |= DMA_RQ_C1_SOURCE_MOD64;
  1181. break;
  1182. case 64:
  1183. temp |= DMA_RQ_C1_SOURCE_MOD32;
  1184. break;
  1185. case 32:
  1186. temp |= DMA_RQ_C1_SOURCE_MOD16;
  1187. break;
  1188. default:
  1189. snd_printdd ("period size (%d) not supported by HW\n", period_size);
  1190. return -EINVAL;
  1191. }
  1192. snd_cs46xx_poke (chip,pcm_channel->pcm_reader_scb->address << 2,temp);
  1193. return 0;
  1194. }
  1195. int cs46xx_dsp_pcm_ostream_set_period (struct snd_cs46xx * chip,
  1196. int period_size)
  1197. {
  1198. u32 temp = snd_cs46xx_peek (chip,WRITEBACK_SCB_ADDR << 2);
  1199. temp &= ~DMA_RQ_C1_DEST_SIZE_MASK;
  1200. switch (period_size) {
  1201. case 2048:
  1202. temp |= DMA_RQ_C1_DEST_MOD1024;
  1203. break;
  1204. case 1024:
  1205. temp |= DMA_RQ_C1_DEST_MOD512;
  1206. break;
  1207. case 512:
  1208. temp |= DMA_RQ_C1_DEST_MOD256;
  1209. break;
  1210. case 256:
  1211. temp |= DMA_RQ_C1_DEST_MOD128;
  1212. break;
  1213. case 128:
  1214. temp |= DMA_RQ_C1_DEST_MOD64;
  1215. break;
  1216. case 64:
  1217. temp |= DMA_RQ_C1_DEST_MOD32;
  1218. break;
  1219. case 32:
  1220. temp |= DMA_RQ_C1_DEST_MOD16;
  1221. break;
  1222. default:
  1223. snd_printdd ("period size (%d) not supported by HW\n", period_size);
  1224. return -EINVAL;
  1225. }
  1226. snd_cs46xx_poke (chip,WRITEBACK_SCB_ADDR << 2,temp);
  1227. return 0;
  1228. }
  1229. void cs46xx_dsp_destroy_pcm_channel (struct snd_cs46xx * chip,
  1230. struct dsp_pcm_channel_descriptor * pcm_channel)
  1231. {
  1232. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1233. unsigned long flags;
  1234. if (snd_BUG_ON(!pcm_channel->active ||
  1235. ins->npcm_channels <= 0 ||
  1236. pcm_channel->src_scb->ref_count <= 0))
  1237. return;
  1238. spin_lock_irqsave(&chip->reg_lock, flags);
  1239. pcm_channel->unlinked = 1;
  1240. pcm_channel->active = 0;
  1241. pcm_channel->private_data = NULL;
  1242. pcm_channel->src_scb->ref_count --;
  1243. ins->npcm_channels --;
  1244. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1245. cs46xx_dsp_remove_scb(chip,pcm_channel->pcm_reader_scb);
  1246. if (!pcm_channel->src_scb->ref_count) {
  1247. cs46xx_dsp_remove_scb(chip,pcm_channel->src_scb);
  1248. if (snd_BUG_ON(pcm_channel->src_slot < 0 ||
  1249. pcm_channel->src_slot >= DSP_MAX_SRC_NR))
  1250. return;
  1251. ins->src_scb_slots[pcm_channel->src_slot] = 0;
  1252. ins->nsrc_scb --;
  1253. }
  1254. }
  1255. int cs46xx_dsp_pcm_unlink (struct snd_cs46xx * chip,
  1256. struct dsp_pcm_channel_descriptor * pcm_channel)
  1257. {
  1258. unsigned long flags;
  1259. if (snd_BUG_ON(!pcm_channel->active ||
  1260. chip->dsp_spos_instance->npcm_channels <= 0))
  1261. return -EIO;
  1262. spin_lock_irqsave(&chip->reg_lock, flags);
  1263. if (pcm_channel->unlinked) {
  1264. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1265. return -EIO;
  1266. }
  1267. pcm_channel->unlinked = 1;
  1268. _dsp_unlink_scb (chip,pcm_channel->pcm_reader_scb);
  1269. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1270. return 0;
  1271. }
  1272. int cs46xx_dsp_pcm_link (struct snd_cs46xx * chip,
  1273. struct dsp_pcm_channel_descriptor * pcm_channel)
  1274. {
  1275. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1276. struct dsp_scb_descriptor * parent_scb;
  1277. struct dsp_scb_descriptor * src_scb = pcm_channel->src_scb;
  1278. unsigned long flags;
  1279. spin_lock_irqsave(&chip->reg_lock, flags);
  1280. if (pcm_channel->unlinked == 0) {
  1281. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1282. return -EIO;
  1283. }
  1284. parent_scb = src_scb;
  1285. if (src_scb->sub_list_ptr != ins->the_null_scb) {
  1286. src_scb->sub_list_ptr->parent_scb_ptr = pcm_channel->pcm_reader_scb;
  1287. pcm_channel->pcm_reader_scb->next_scb_ptr = src_scb->sub_list_ptr;
  1288. }
  1289. src_scb->sub_list_ptr = pcm_channel->pcm_reader_scb;
  1290. snd_BUG_ON(pcm_channel->pcm_reader_scb->parent_scb_ptr);
  1291. pcm_channel->pcm_reader_scb->parent_scb_ptr = parent_scb;
  1292. /* update SCB entry in DSP RAM */
  1293. cs46xx_dsp_spos_update_scb(chip,pcm_channel->pcm_reader_scb);
  1294. /* update parent SCB entry */
  1295. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1296. pcm_channel->unlinked = 0;
  1297. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1298. return 0;
  1299. }
  1300. struct dsp_scb_descriptor *
  1301. cs46xx_add_record_source (struct snd_cs46xx *chip, struct dsp_scb_descriptor * source,
  1302. u16 addr, char * scb_name)
  1303. {
  1304. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1305. struct dsp_scb_descriptor * parent;
  1306. struct dsp_scb_descriptor * pcm_input;
  1307. int insert_point;
  1308. if (snd_BUG_ON(!ins->record_mixer_scb))
  1309. return NULL;
  1310. if (ins->record_mixer_scb->sub_list_ptr != ins->the_null_scb) {
  1311. parent = find_next_free_scb (chip,ins->record_mixer_scb->sub_list_ptr);
  1312. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1313. } else {
  1314. parent = ins->record_mixer_scb;
  1315. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1316. }
  1317. pcm_input = cs46xx_dsp_create_pcm_serial_input_scb(chip,scb_name,addr,
  1318. source, parent,
  1319. insert_point);
  1320. return pcm_input;
  1321. }
  1322. int cs46xx_src_unlink(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1323. {
  1324. unsigned long flags;
  1325. if (snd_BUG_ON(!src->parent_scb_ptr))
  1326. return -EINVAL;
  1327. /* mute SCB */
  1328. cs46xx_dsp_scb_set_volume (chip,src,0,0);
  1329. spin_lock_irqsave(&chip->reg_lock, flags);
  1330. _dsp_unlink_scb (chip,src);
  1331. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1332. return 0;
  1333. }
  1334. int cs46xx_src_link(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1335. {
  1336. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1337. struct dsp_scb_descriptor * parent_scb;
  1338. if (snd_BUG_ON(src->parent_scb_ptr))
  1339. return -EINVAL;
  1340. if (snd_BUG_ON(!ins->master_mix_scb))
  1341. return -EINVAL;
  1342. if (ins->master_mix_scb->sub_list_ptr != ins->the_null_scb) {
  1343. parent_scb = find_next_free_scb (chip,ins->master_mix_scb->sub_list_ptr);
  1344. parent_scb->next_scb_ptr = src;
  1345. } else {
  1346. parent_scb = ins->master_mix_scb;
  1347. parent_scb->sub_list_ptr = src;
  1348. }
  1349. src->parent_scb_ptr = parent_scb;
  1350. /* update entry in DSP RAM */
  1351. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1352. return 0;
  1353. }
  1354. int cs46xx_dsp_enable_spdif_out (struct snd_cs46xx *chip)
  1355. {
  1356. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1357. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1358. cs46xx_dsp_enable_spdif_hw (chip);
  1359. }
  1360. /* dont touch anything if SPDIF is open */
  1361. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1362. /* when cs46xx_iec958_post_close(...) is called it
  1363. will call this function if necessary depending on
  1364. this bit */
  1365. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1366. return -EBUSY;
  1367. }
  1368. if (snd_BUG_ON(ins->asynch_tx_scb))
  1369. return -EINVAL;
  1370. if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr !=
  1371. ins->the_null_scb))
  1372. return -EINVAL;
  1373. /* reset output snooper sample buffer pointer */
  1374. snd_cs46xx_poke (chip, (ins->ref_snoop_scb->address + 2) << 2,
  1375. (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10 );
  1376. /* The asynch. transfer task */
  1377. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1378. SPDIFO_SCB_INST,
  1379. SPDIFO_IP_OUTPUT_BUFFER1,
  1380. ins->master_mix_scb,
  1381. SCB_ON_PARENT_NEXT_SCB);
  1382. if (!ins->asynch_tx_scb) return -ENOMEM;
  1383. ins->spdif_pcm_input_scb = cs46xx_dsp_create_pcm_serial_input_scb(chip,"PCMSerialInput_II",
  1384. PCMSERIALINII_SCB_ADDR,
  1385. ins->ref_snoop_scb,
  1386. ins->asynch_tx_scb,
  1387. SCB_ON_PARENT_SUBLIST_SCB);
  1388. if (!ins->spdif_pcm_input_scb) return -ENOMEM;
  1389. /* monitor state */
  1390. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1391. return 0;
  1392. }
  1393. int cs46xx_dsp_disable_spdif_out (struct snd_cs46xx *chip)
  1394. {
  1395. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1396. /* dont touch anything if SPDIF is open */
  1397. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1398. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1399. return -EBUSY;
  1400. }
  1401. /* check integrety */
  1402. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1403. return -EINVAL;
  1404. if (snd_BUG_ON(!ins->spdif_pcm_input_scb))
  1405. return -EINVAL;
  1406. if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr != ins->asynch_tx_scb))
  1407. return -EINVAL;
  1408. if (snd_BUG_ON(ins->asynch_tx_scb->parent_scb_ptr !=
  1409. ins->master_mix_scb))
  1410. return -EINVAL;
  1411. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1412. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1413. ins->spdif_pcm_input_scb = NULL;
  1414. ins->asynch_tx_scb = NULL;
  1415. /* clear buffer to prevent any undesired noise */
  1416. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1417. /* monitor state */
  1418. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1419. return 0;
  1420. }
  1421. int cs46xx_iec958_pre_open (struct snd_cs46xx *chip)
  1422. {
  1423. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1424. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1425. /* remove AsynchFGTxSCB and and PCMSerialInput_II */
  1426. cs46xx_dsp_disable_spdif_out (chip);
  1427. /* save state */
  1428. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1429. }
  1430. /* if not enabled already */
  1431. if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1432. cs46xx_dsp_enable_spdif_hw (chip);
  1433. }
  1434. /* Create the asynch. transfer task for playback */
  1435. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1436. SPDIFO_SCB_INST,
  1437. SPDIFO_IP_OUTPUT_BUFFER1,
  1438. ins->master_mix_scb,
  1439. SCB_ON_PARENT_NEXT_SCB);
  1440. /* set spdif channel status value for streaming */
  1441. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_stream);
  1442. ins->spdif_status_out |= DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1443. return 0;
  1444. }
  1445. int cs46xx_iec958_post_close (struct snd_cs46xx *chip)
  1446. {
  1447. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1448. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1449. return -EINVAL;
  1450. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1451. /* restore settings */
  1452. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1453. /* deallocate stuff */
  1454. if (ins->spdif_pcm_input_scb != NULL) {
  1455. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1456. ins->spdif_pcm_input_scb = NULL;
  1457. }
  1458. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1459. ins->asynch_tx_scb = NULL;
  1460. /* clear buffer to prevent any undesired noise */
  1461. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1462. /* restore state */
  1463. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1464. cs46xx_dsp_enable_spdif_out (chip);
  1465. }
  1466. return 0;
  1467. }