mdss_panel.h 16 KB

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  1. /* Copyright (c) 2008-2014, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. */
  13. #ifndef MDSS_PANEL_H
  14. #define MDSS_PANEL_H
  15. #include <linux/platform_device.h>
  16. #include <linux/types.h>
  17. #include "dlog.h"
  18. #if defined(CONFIG_FB_MSM_MDSS_S6E8AA0A_HD_PANEL)
  19. #include "smart_mtp_s6e8aa0x01.h"
  20. #include "smart_dimming.h"
  21. typedef unsigned int boolean;
  22. #endif
  23. /* panel id type */
  24. struct panel_id {
  25. u16 id;
  26. u16 type;
  27. };
  28. #define DEFAULT_FRAME_RATE 60
  29. #define MDSS_DSI_RST_SEQ_LEN 10
  30. /* panel type list */
  31. #define NO_PANEL 0xffff /* No Panel */
  32. #define MDDI_PANEL 1 /* MDDI */
  33. #define EBI2_PANEL 2 /* EBI2 */
  34. #define LCDC_PANEL 3 /* internal LCDC type */
  35. #define EXT_MDDI_PANEL 4 /* Ext.MDDI */
  36. #define TV_PANEL 5 /* TV */
  37. #define HDMI_PANEL 6 /* HDMI TV */
  38. #define DTV_PANEL 7 /* DTV */
  39. #define MIPI_VIDEO_PANEL 8 /* MIPI */
  40. #define MIPI_CMD_PANEL 9 /* MIPI */
  41. #define WRITEBACK_PANEL 10 /* Wifi display */
  42. #define LVDS_PANEL 11 /* LVDS */
  43. #define EDP_PANEL 12 /* LVDS */
  44. /* panel class */
  45. enum {
  46. DISPLAY_LCD = 0, /* lcd = ebi2/mddi */
  47. DISPLAY_LCDC, /* lcdc */
  48. DISPLAY_TV, /* TV Out */
  49. DISPLAY_EXT_MDDI, /* External MDDI */
  50. DISPLAY_WRITEBACK,
  51. };
  52. /* panel device locaiton */
  53. enum {
  54. DISPLAY_1 = 0, /* attached as first device */
  55. DISPLAY_2, /* attached on second device */
  56. DISPLAY_3, /* attached on third writeback device */
  57. MAX_PHYS_TARGET_NUM,
  58. };
  59. enum {
  60. MDSS_PANEL_INTF_INVALID = -1,
  61. MDSS_PANEL_INTF_DSI,
  62. MDSS_PANEL_INTF_EDP,
  63. MDSS_PANEL_INTF_HDMI,
  64. };
  65. enum {
  66. MODE_GPIO_NOT_VALID = 0,
  67. MODE_GPIO_HIGH,
  68. MODE_GPIO_LOW,
  69. };
  70. #define MDSS_MAX_PANEL_LEN 256
  71. #define MDSS_INTF_MAX_NAME_LEN 5
  72. struct mdss_panel_intf {
  73. char name[MDSS_INTF_MAX_NAME_LEN];
  74. int type;
  75. };
  76. struct mdss_panel_cfg {
  77. char arg_cfg[MDSS_MAX_PANEL_LEN + 1];
  78. int pan_intf;
  79. bool lk_cfg;
  80. bool init_done;
  81. };
  82. struct mdss_panel_recovery {
  83. void (*fxn)(void *ctx);
  84. void *data;
  85. };
  86. #define MDSS_PANEL_INTF_MAX 2
  87. struct mdss_panel_intf_desc {
  88. char valid;
  89. char intf_type;
  90. char *panel_name;
  91. };
  92. struct mdss_panel_desc {
  93. char cont_splash;
  94. char pref_prim_intf;
  95. char intf_tot;
  96. char *cmd_args;
  97. struct mdss_panel_intf_desc intf[MDSS_PANEL_INTF_MAX];
  98. };
  99. /**
  100. * enum mdss_intf_events - Different events generated by MDP core
  101. *
  102. * @MDSS_EVENT_RESET: MDP control path is being (re)initialized.
  103. * @MDSS_EVENT_UNBLANK: Sent before first frame update from MDP is
  104. * sent to panel.
  105. * @MDSS_EVENT_PANEL_ON: After first frame update from MDP.
  106. * @MDSS_EVENT_BLANK: MDP has no contents to display only blank screen
  107. * is shown in panel. Sent before panel off.
  108. * @MDSS_EVENT_PANEL_OFF: MDP has suspended frame updates, panel should be
  109. * completely shutdown after this call.
  110. * @MDSS_EVENT_CLOSE: MDP has tore down entire session.
  111. * @MDSS_EVENT_SUSPEND: Propagation of power suspend event.
  112. * @MDSS_EVENT_RESUME: Propagation of power resume event.
  113. * @MDSS_EVENT_CHECK_PARAMS: Event generated when a panel reconfiguration is
  114. * requested including when resolution changes.
  115. * The event handler receives pointer to
  116. * struct mdss_panel_info and should return one of:
  117. * - negative if the configuration is invalid
  118. * - 0 if there is no panel reconfig needed
  119. * - 1 if reconfig is needed to take effect
  120. * @MDSS_EVENT_CONT_SPLASH_BEGIN: Special event used to handle transition of
  121. * display state from boot loader to panel driver.
  122. * The event handler will disable the panel.
  123. * @MDSS_EVENT_CONT_SPLASH_FINISH: Special event used to handle transition of
  124. * display state from boot loader to panel driver.
  125. * The event handler will enable the panel and
  126. * vote for the display clocks.
  127. * @MDSS_EVENT_PANEL_UPDATE_FPS: Event to update the frame rate of the panel.
  128. * @MDSS_EVENT_FB_REGISTERED: Called after fb dev driver has been registered,
  129. * panel driver gets ptr to struct fb_info which
  130. * holds fb dev information.
  131. * @MDSS_EVENT_PANEL_CLK_CTRL: panel clock control
  132. - 0 clock disable
  133. - 1 clock enable
  134. * @MDSS_EVENT_DSI_CMDLIST_KOFF: kickoff sending dcs command from command list
  135. * @MDSS_EVENT_ENABLE_PARTIAL_UPDATE: Event to update ROI of the panel.
  136. * @MDSS_EVENT_DSI_CMDLIST_KOFF: acquire dsi_mdp_busy lock before kickoff.
  137. * @MDSS_EVENT_DSI_ULPS_CTRL: Event to configure Ultra Lower Power Saving
  138. * mode for the DSI data and clock lanes. The
  139. * event arguments can have one of these values:
  140. * - 0: Disable ULPS mode
  141. * - 1: Enable ULPS mode
  142. * @MDSS_EVENT_DSI_DYNAMIC_SWITCH: Event to update the dsi driver structures
  143. * based on the dsi mode passed as argument.
  144. * - 0: update to video mode
  145. * - 1: update to command mode
  146. */
  147. enum mdss_intf_events {
  148. MDSS_EVENT_RESET = 1,
  149. MDSS_EVENT_UNBLANK,
  150. MDSS_EVENT_PANEL_ON,
  151. MDSS_EVENT_BLANK,
  152. MDSS_EVENT_PANEL_OFF,
  153. #if defined(CONFIG_FB_MSM_MDSS_S6E8AA0A_HD_PANEL)
  154. MTP_READ,
  155. #endif
  156. MDSS_EVENT_CLOSE,
  157. MDSS_EVENT_SUSPEND,
  158. MDSS_EVENT_RESUME,
  159. MDSS_EVENT_CHECK_PARAMS,
  160. MDSS_EVENT_CONT_SPLASH_BEGIN,
  161. MDSS_EVENT_CONT_SPLASH_FINISH,
  162. MDSS_EVENT_FIRST_FRAME_UPDATE,
  163. MDSS_EVENT_PANEL_UPDATE_FPS,
  164. MDSS_EVENT_FB_REGISTERED,
  165. MDSS_EVENT_FRAME_UPDATE,
  166. MDSS_EVENT_PANEL_CLK_CTRL,
  167. MDSS_EVENT_DSI_CMDLIST_KOFF,
  168. MDSS_EVENT_MDNIE_DEFAULT_UPDATE,
  169. MDSS_EVENT_ENABLE_PARTIAL_UPDATE,
  170. MDSS_EVENT_DSI_ULPS_CTRL,
  171. MDSS_EVENT_REGISTER_RECOVERY_HANDLER,
  172. MDSS_EVENT_DSI_DYNAMIC_SWITCH,
  173. MDSS_EVENT_BACKLIGHT_LATE_ON,
  174. #if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OCTA_CMD_WQHD_PT_PANEL)
  175. MDSS_EVENT_TE_UPDATE,
  176. MDSS_EVENT_TE_UPDATE2,
  177. MDSS_EVENT_TE_SET,
  178. MDSS_EVENT_TE_RESTORE,
  179. #endif
  180. };
  181. struct lcd_panel_info {
  182. u32 h_back_porch;
  183. u32 h_front_porch;
  184. u32 h_pulse_width;
  185. u32 v_back_porch;
  186. u32 v_front_porch;
  187. u32 v_pulse_width;
  188. u32 border_clr;
  189. u32 underflow_clr;
  190. u32 hsync_skew;
  191. /* Pad width */
  192. u32 xres_pad;
  193. /* Pad height */
  194. u32 yres_pad;
  195. };
  196. /* DSI PHY configuration */
  197. struct mdss_dsi_phy_ctrl {
  198. uint32_t regulator[7];
  199. uint32_t timing[12];
  200. uint32_t ctrl[4];
  201. uint32_t strength[2];
  202. char bistctrl[6];
  203. uint32_t pll[21];
  204. char lanecfg[45];
  205. };
  206. struct mipi_panel_info {
  207. char mode; /* video/cmd */
  208. char interleave_mode;
  209. char crc_check;
  210. char ecc_check;
  211. char dst_format; /* shared by video and command */
  212. char data_lane0;
  213. char data_lane1;
  214. char data_lane2;
  215. char data_lane3;
  216. char dlane_swap; /* data lane swap */
  217. char rgb_swap;
  218. char b_sel;
  219. char g_sel;
  220. char r_sel;
  221. char rx_eot_ignore;
  222. char tx_eot_append;
  223. char t_clk_post; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */
  224. char t_clk_pre; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */
  225. char vc; /* virtual channel */
  226. struct mdss_dsi_phy_ctrl dsi_phy_db;
  227. /* video mode */
  228. char pulse_mode_hsa_he;
  229. char hfp_power_stop;
  230. char hbp_power_stop;
  231. char hsa_power_stop;
  232. char eof_bllp_power_stop;
  233. char last_line_interleave_en;
  234. char bllp_power_stop;
  235. char traffic_mode;
  236. char frame_rate;
  237. /* command mode */
  238. char interleave_max;
  239. char insert_dcs_cmd;
  240. char wr_mem_continue;
  241. char wr_mem_start;
  242. char te_sel;
  243. char stream; /* 0 or 1 */
  244. char mdp_trigger;
  245. char dma_trigger;
  246. /*Dynamic Switch Support*/
  247. bool dynamic_switch_enabled;
  248. u32 pixel_packing;
  249. u32 dsi_pclk_rate;
  250. /* The packet-size should not bet changed */
  251. char no_max_pkt_size;
  252. /* Clock required during LP commands */
  253. char force_clk_lane_hs;
  254. char vsync_enable;
  255. char hw_vsync_mode;
  256. char lp11_init;
  257. u32 init_delay;
  258. };
  259. struct edp_panel_info {
  260. char frame_rate; /* fps */
  261. };
  262. enum dynamic_fps_update {
  263. DFPS_SUSPEND_RESUME_MODE,
  264. DFPS_IMMEDIATE_CLK_UPDATE_MODE,
  265. DFPS_IMMEDIATE_PORCH_UPDATE_MODE,
  266. };
  267. enum lvds_mode {
  268. LVDS_SINGLE_CHANNEL_MODE,
  269. LVDS_DUAL_CHANNEL_MODE,
  270. };
  271. struct lvds_panel_info {
  272. enum lvds_mode channel_mode;
  273. /* Channel swap in dual mode */
  274. char channel_swap;
  275. };
  276. struct fbc_panel_info {
  277. u32 enabled;
  278. u32 target_bpp;
  279. u32 comp_mode;
  280. u32 qerr_enable;
  281. u32 cd_bias;
  282. u32 pat_enable;
  283. u32 vlc_enable;
  284. u32 bflc_enable;
  285. u32 line_x_budget;
  286. u32 block_x_budget;
  287. u32 block_budget;
  288. u32 lossless_mode_thd;
  289. u32 lossy_mode_thd;
  290. u32 lossy_rgb_thd;
  291. u32 lossy_mode_idx;
  292. };
  293. struct mdss_mdp_pp_tear_check {
  294. u32 tear_check_en;
  295. u32 sync_cfg_height;
  296. u32 vsync_init_val;
  297. u32 sync_threshold_start;
  298. u32 sync_threshold_continue;
  299. u32 start_pos;
  300. u32 rd_ptr_irq;
  301. u32 refx100;
  302. };
  303. struct mdss_panel_info {
  304. u32 xres;
  305. u32 yres;
  306. u32 physical_width;
  307. u32 physical_height;
  308. u32 width;
  309. u32 height;
  310. u32 bpp;
  311. u32 type;
  312. u32 wait_cycle;
  313. u32 pdest;
  314. u32 brightness_max;
  315. u32 bl_max;
  316. u32 bl_min;
  317. u32 fb_num;
  318. u32 clk_rate;
  319. u32 clk_min;
  320. u32 clk_max;
  321. u32 frame_count;
  322. u32 is_3d_panel;
  323. u32 out_format;
  324. u32 rst_seq[MDSS_DSI_RST_SEQ_LEN];
  325. u32 rst_seq_len;
  326. u32 early_lcd_on;
  327. u32 vic; /* video identification code */
  328. u32 roi_x;
  329. u32 roi_y;
  330. u32 roi_w;
  331. u32 roi_h;
  332. int bklt_ctrl; /* backlight ctrl */
  333. int pwm_pmic_gpio;
  334. int pwm_lpg_chan;
  335. int pwm_period;
  336. u32 mode_gpio_state;
  337. bool dynamic_fps;
  338. bool ulps_feature_enabled;
  339. bool esd_check_enabled;
  340. char dfps_update;
  341. int new_fps;
  342. int panel_max_fps;
  343. int panel_max_vtotal;
  344. u32 xstart_pix_align;
  345. u32 width_pix_align;
  346. u32 ystart_pix_align;
  347. u32 height_pix_align;
  348. u32 min_width;
  349. u32 min_height;
  350. u32 min_fps;
  351. u32 max_fps;
  352. u32 cont_splash_enabled;
  353. u32 partial_update_enabled;
  354. struct ion_handle *splash_ihdl;
  355. u32 panel_power_on;
  356. int force_screen_state;
  357. uint32_t panel_dead;
  358. bool dynamic_switch_pending;
  359. bool is_lpm_mode;
  360. struct mdss_mdp_pp_tear_check te;
  361. struct lcd_panel_info lcdc;
  362. struct fbc_panel_info fbc;
  363. struct mipi_panel_info mipi;
  364. struct lvds_panel_info lvds;
  365. struct edp_panel_info edp;
  366. u8 (*alpm_event) (u8 flag);
  367. void (*alpm_gamma_read) (void);
  368. };
  369. #if defined(CONFIG_FB_MSM_MDSS_S6E8AA0A_HD_PANEL)
  370. #define MTP_DATA_SIZE (24)
  371. #define ELVSS_DATA_SIZE (24)
  372. struct cmd_set {
  373. struct dsi_cmd_desc *cmd;
  374. int size;
  375. };
  376. #endif
  377. /* ALPM Flags */
  378. enum {
  379. /* Status Flags */
  380. MODE_OFF = 0, /* Off ALPM or Normal Mode Status */
  381. ALPM_MODE_ON, /* ALPM Mode Status */
  382. NORMAL_MODE_ON, /* Normal Mode Status */
  383. /* Event Flags */
  384. CHECK_CURRENT_STATUS, /* Check Current Mode */
  385. CHECK_PREVIOUS_STATUS, /* Check Previous Mode */
  386. STORE_CURRENT_STATUS, /* Store Current Mode to Previous Mode */
  387. CLEAR_MODE_STATUS, /* Clear Status Flag as 0 */
  388. /* Brightness Flags */
  389. CHECK_BL_VALUE,
  390. STORE_BL_10CD = 10, /* Store Brightness level */
  391. STORE_BL_60CD = 60, /* Store Brightness Level */
  392. };
  393. struct mdss_panel_data {
  394. struct mdss_panel_info panel_info;
  395. void (*set_backlight) (struct mdss_panel_data *pdata, u32 bl_level);
  396. unsigned char *mmss_cc_base;
  397. //void (*panel_reset_fn)(struct mdss_panel_data *pdata, int enable);
  398. //int (*panel_extra_power)(struct mdss_panel_data *pdata, int enable);
  399. /**
  400. * event_handler() - callback handler for MDP core events
  401. * @pdata: Pointer refering to the panel struct associated to this
  402. * event. Can be used to retrieve panel info.
  403. * @e: Event being generated, see enum mdss_intf_events
  404. * @arg: Optional argument to pass some info from some events.
  405. *
  406. * Used to register handler to be used to propagate different events
  407. * happening in MDP core driver. Panel driver can listen for any of
  408. * these events to perform appropriate actions for panel initialization
  409. * and teardown.
  410. */
  411. int (*event_handler) (struct mdss_panel_data *pdata, int e, void *arg);
  412. struct mdss_panel_data *next;
  413. #if defined(CONFIG_FB_MSM_MDSS_S6E8AA0A_HD_PANEL)
  414. unsigned char *gamma_smartdim_4_8;
  415. int *lux_table;
  416. int lux_table_max_cnt;
  417. struct SMART_DIM smart_s6e8aa0x01;
  418. struct SMART_DIM smart_ea8868;
  419. struct str_smart_dim smart;
  420. signed char lcd_current_cd_idx;
  421. unsigned char lcd_mtp_data[MTP_DATA_SIZE+16] ;
  422. unsigned char lcd_elvss_data[ELVSS_DATA_SIZE+16];
  423. unsigned char *gamma_smartdim;
  424. unsigned char *gamma_initial;
  425. struct cmd_set gamma_update;
  426. struct cmd_set elvss_update;
  427. struct cmd_set elvss_update_4_8;
  428. struct cmd_set acl_on;
  429. struct cmd_set acl_off;
  430. struct cmd_set acl_update;
  431. int (*set_gamma)(int bl_level, int gamma_mode);
  432. int (*set_acl)(int bl_level);
  433. int (*set_elvss)(int bl_level);
  434. int (*set_elvss_4_8)(int bl_level);
  435. int (*prepare_brightness_control_cmd_array)(int lcd_type, int bl_level);
  436. struct cmd_set combined_ctrl;
  437. boolean ldi_acl_stat;
  438. #endif
  439. };
  440. /**
  441. * mdss_get_panel_framerate() - get panel frame rate based on panel information
  442. * @panel_info: Pointer to panel info containing all panel information
  443. */
  444. static inline u32 mdss_panel_get_framerate(struct mdss_panel_info *panel_info)
  445. {
  446. u32 frame_rate, pixel_total;
  447. if (panel_info == NULL)
  448. return DEFAULT_FRAME_RATE;
  449. switch (panel_info->type) {
  450. case MIPI_VIDEO_PANEL:
  451. case MIPI_CMD_PANEL:
  452. frame_rate = panel_info->mipi.frame_rate;
  453. break;
  454. case EDP_PANEL:
  455. frame_rate = panel_info->edp.frame_rate;
  456. break;
  457. case WRITEBACK_PANEL:
  458. frame_rate = DEFAULT_FRAME_RATE;
  459. break;
  460. default:
  461. pixel_total = (panel_info->lcdc.h_back_porch +
  462. panel_info->lcdc.h_front_porch +
  463. panel_info->lcdc.h_pulse_width +
  464. panel_info->xres) *
  465. (panel_info->lcdc.v_back_porch +
  466. panel_info->lcdc.v_front_porch +
  467. panel_info->lcdc.v_pulse_width +
  468. panel_info->yres);
  469. if (pixel_total)
  470. frame_rate = panel_info->clk_rate / pixel_total;
  471. else
  472. frame_rate = DEFAULT_FRAME_RATE;
  473. break;
  474. }
  475. return frame_rate;
  476. }
  477. /**
  478. * mdss_panel_get_min_bw() - get panel min bw based on resolution
  479. * @panel_info: Pointer to panel info containing all panel information
  480. * the min BW should be = panel_info->xres * panel_info->yres * 4 bpp * frame_rate
  481. */
  482. static inline u32 mdss_panel_get_min_bw(struct mdss_panel_info *panel_info)
  483. {
  484. u32 min_bw, frame_rate;
  485. if (panel_info == NULL)
  486. return -EINVAL;
  487. frame_rate = mdss_panel_get_framerate(panel_info);
  488. switch (panel_info->type) {
  489. case WRITEBACK_PANEL:
  490. case MIPI_VIDEO_PANEL:
  491. case MIPI_CMD_PANEL:
  492. default:
  493. min_bw = panel_info->xres * panel_info->yres * 4 * frame_rate;
  494. break;
  495. }
  496. return min_bw;
  497. }
  498. /*
  499. * mdss_panel_get_vtotal() - return panel vertical height
  500. * @pinfo: Pointer to panel info containing all panel information
  501. *
  502. * Returns the total height of the panel including any blanking regions
  503. * which are not visible to user but used to calculate panel pixel clock.
  504. */
  505. static inline int mdss_panel_get_vtotal(struct mdss_panel_info *pinfo)
  506. {
  507. return pinfo->yres + pinfo->lcdc.v_back_porch +
  508. pinfo->lcdc.v_front_porch +
  509. pinfo->lcdc.v_pulse_width;
  510. }
  511. /*
  512. * mdss_panel_get_htotal() - return panel horizontal width
  513. * @pinfo: Pointer to panel info containing all panel information
  514. *
  515. * Returns the total width of the panel including any blanking regions
  516. * which are not visible to user but used for calculations.
  517. */
  518. static inline int mdss_panel_get_htotal(struct mdss_panel_info *pinfo)
  519. {
  520. return pinfo->xres + pinfo->lcdc.h_back_porch +
  521. pinfo->lcdc.h_front_porch +
  522. pinfo->lcdc.h_pulse_width;
  523. }
  524. int mdss_register_panel(struct platform_device *pdev,
  525. struct mdss_panel_data *pdata);
  526. /**
  527. * mdss_panel_intf_type: - checks if a given intf type is primary
  528. * @intf_val: panel interface type of the individual controller
  529. *
  530. * Individual controller queries with MDP to check if it is
  531. * configured as the primary interface.
  532. *
  533. * returns a pointer to the configured structure mdss_panel_cfg
  534. * to the controller that's configured as the primary panel interface.
  535. * returns NULL on error or if @intf_val is not the configured
  536. * controller.
  537. */
  538. struct mdss_panel_cfg *mdss_panel_intf_type(int intf_val);
  539. /**
  540. * mdss_panel_get_boot_cfg() - checks if bootloader config present
  541. *
  542. * Function returns true if bootloader has configured the parameters
  543. * for primary controller and panel config data.
  544. *
  545. * returns true if bootloader configured, else false
  546. */
  547. int mdss_panel_get_boot_cfg(void);
  548. /**
  549. * mdss_is_ready() - checks if mdss is probed and ready
  550. *
  551. * Checks if mdss resources have been initialized
  552. *
  553. * returns true if mdss is ready, else returns false.
  554. */
  555. bool mdss_is_ready(void);
  556. int mdss_panel_force_update(struct mdss_panel_data *pdata);
  557. int load_565rle_image(char *filename);
  558. int load_samsung_boot_logo(void);
  559. #if defined(CONFIG_LCD_CONNECTION_CHECK)
  560. int is_lcd_attached(void);
  561. #endif
  562. #if defined(CONFIG_CLK_TUNING)
  563. void load_clk_tuning_file(void);
  564. #endif /* CONFIG_CLK_TUNING */
  565. #endif /* MDSS_PANEL_H */