mdss_mdp_intf_cmd.c 29 KB

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  1. /* Copyright (c) 2013, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/bootmem.h>
  15. #include <linux/memblock.h>
  16. #include "mdss_mdp.h"
  17. #include "mdss_panel.h"
  18. #include "mdss_debug.h"
  19. #include "mdss_fb.h"
  20. #include "mdss_mdp_trace.h"
  21. #define VSYNC_EXPIRE_TICK 6
  22. #define MAX_SESSIONS 2
  23. /* wait for at most 2 vsync for lowest refresh rate (24hz) */
  24. #define KOFF_TIMEOUT msecs_to_jiffies(84)
  25. #define STOP_TIMEOUT(hz) msecs_to_jiffies((1000 / hz) * (VSYNC_EXPIRE_TICK + 2))
  26. #define ULPS_ENTER_TIME msecs_to_jiffies(100)
  27. /*
  28. * STOP_TIMEOUT need to wait for cmd stop depends on fps
  29. * if the command panel support 60fps the timeout value
  30. * generated using 16ms(1frame). If that support 15fps the timeout value
  31. * generated by 40ms(1frame)
  32. */
  33. #define STOP_TIMEOUT_FOR_ALPM msecs_to_jiffies(40 * (VSYNC_EXPIRE_TICK + 2))
  34. struct mdss_mdp_cmd_ctx {
  35. struct mdss_mdp_ctl *ctl;
  36. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  37. u32 panel_ndx;
  38. #endif
  39. u32 pp_num;
  40. u8 ref_cnt;
  41. struct completion stop_comp;
  42. wait_queue_head_t pp_waitq;
  43. struct list_head vsync_handlers;
  44. int panel_on;
  45. atomic_t koff_cnt;
  46. int clk_enabled;
  47. int vsync_enabled;
  48. int rdptr_enabled;
  49. struct mutex clk_mtx;
  50. spinlock_t clk_lock;
  51. #if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OCTA_CMD_WQHD_PT_PANEL)
  52. spinlock_t te_lock;
  53. #endif
  54. struct work_struct clk_work;
  55. struct delayed_work ulps_work;
  56. struct work_struct pp_done_work;
  57. atomic_t pp_done_cnt;
  58. /* te config */
  59. u8 tear_check;
  60. u16 height; /* panel height */
  61. u16 vporch; /* vertical porches */
  62. u16 start_threshold;
  63. u32 vclk_line; /* vsync clock per line */
  64. struct mdss_panel_recovery recovery;
  65. bool ulps;
  66. struct mdss_mdp_cmd_ctx *sync_ctx; /* for partial update */
  67. u32 pp_timeout_report_cnt;
  68. };
  69. struct mdss_mdp_cmd_ctx mdss_mdp_cmd_ctx_list[MAX_SESSIONS];
  70. extern char board_rev;
  71. int get_lcd_attached(void);
  72. static int mdss_mdp_cmd_do_notifier(struct mdss_mdp_cmd_ctx *ctx);
  73. static inline u32 mdss_mdp_cmd_line_count(struct mdss_mdp_ctl *ctl)
  74. {
  75. struct mdss_mdp_mixer *mixer;
  76. u32 cnt = 0xffff; /* init it to an invalid value */
  77. u32 init;
  78. u32 height;
  79. mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
  80. mixer = mdss_mdp_mixer_get(ctl, MDSS_MDP_MIXER_MUX_LEFT);
  81. if (!mixer) {
  82. mixer = mdss_mdp_mixer_get(ctl, MDSS_MDP_MIXER_MUX_RIGHT);
  83. if (!mixer) {
  84. mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
  85. goto exit;
  86. }
  87. }
  88. init = mdss_mdp_pingpong_read
  89. (mixer, MDSS_MDP_REG_PP_VSYNC_INIT_VAL) & 0xffff;
  90. height = mdss_mdp_pingpong_read
  91. (mixer, MDSS_MDP_REG_PP_SYNC_CONFIG_HEIGHT) & 0xffff;
  92. if (height < init) {
  93. mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
  94. goto exit;
  95. }
  96. cnt = mdss_mdp_pingpong_read
  97. (mixer, MDSS_MDP_REG_PP_INT_COUNT_VAL) & 0xffff;
  98. if (cnt < init) /* wrap around happened at height */
  99. cnt += (height - init);
  100. else
  101. cnt -= init;
  102. mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
  103. pr_debug("cnt=%d init=%d height=%d\n", cnt, init, height);
  104. exit:
  105. return cnt;
  106. }
  107. static int mdss_mdp_cmd_tearcheck_cfg(struct mdss_mdp_ctl *ctl,
  108. struct mdss_mdp_mixer *mixer)
  109. {
  110. struct mdss_mdp_pp_tear_check *te;
  111. struct mdss_panel_info *pinfo;
  112. u32 vsync_clk_speed_hz, total_lines, vclks_line, cfg;
  113. if (IS_ERR_OR_NULL(ctl->panel_data)) {
  114. pr_err("no panel data\n");
  115. return -ENODEV;
  116. }
  117. pinfo = &ctl->panel_data->panel_info;
  118. te = &ctl->panel_data->panel_info.te;
  119. mdss_mdp_vsync_clk_enable(1);
  120. vsync_clk_speed_hz =
  121. mdss_mdp_get_clk_rate(MDSS_CLK_MDP_VSYNC);
  122. total_lines = mdss_panel_get_vtotal(pinfo);
  123. total_lines *= pinfo->mipi.frame_rate;
  124. vclks_line = (total_lines) ? vsync_clk_speed_hz / total_lines : 0;
  125. cfg = BIT(19);
  126. if (pinfo->mipi.hw_vsync_mode)
  127. cfg |= BIT(20);
  128. if (te->refx100)
  129. vclks_line = vclks_line * pinfo->mipi.frame_rate *
  130. 100 / te->refx100;
  131. else {
  132. pr_warn("refx100 cannot be zero! Use 6000 as default\n");
  133. vclks_line = vclks_line * pinfo->mipi.frame_rate *
  134. 100 / 6000;
  135. }
  136. cfg |= vclks_line;
  137. pr_info("%s: te->tear_check_en = %d, res=%d vclks=%x height=%d init=%d rd=%d start=%d ",
  138. __func__, te->tear_check_en, pinfo->yres, vclks_line, te->sync_cfg_height,
  139. te->vsync_init_val, te->rd_ptr_irq, te->start_pos);
  140. pr_info("thrd_start =%d thrd_cont=%d\n",
  141. te->sync_threshold_start, te->sync_threshold_continue);
  142. mdss_mdp_pingpong_write(mixer, MDSS_MDP_REG_PP_SYNC_CONFIG_VSYNC, cfg);
  143. mdss_mdp_pingpong_write(mixer, MDSS_MDP_REG_PP_SYNC_CONFIG_HEIGHT,
  144. te->sync_cfg_height);
  145. mdss_mdp_pingpong_write(mixer, MDSS_MDP_REG_PP_VSYNC_INIT_VAL,
  146. te->vsync_init_val);
  147. mdss_mdp_pingpong_write(mixer, MDSS_MDP_REG_PP_RD_PTR_IRQ,
  148. te->rd_ptr_irq);
  149. mdss_mdp_pingpong_write(mixer, MDSS_MDP_REG_PP_START_POS,
  150. te->start_pos);
  151. mdss_mdp_pingpong_write(mixer, MDSS_MDP_REG_PP_SYNC_THRESH,
  152. ((te->sync_threshold_continue << 16) |
  153. te->sync_threshold_start));
  154. mdss_mdp_pingpong_write(mixer, MDSS_MDP_REG_PP_TEAR_CHECK_EN,
  155. te->tear_check_en);
  156. return 0;
  157. }
  158. static int mdss_mdp_cmd_tearcheck_setup(struct mdss_mdp_ctl *ctl)
  159. {
  160. struct mdss_mdp_mixer *mixer;
  161. int rc = 0;
  162. mixer = mdss_mdp_mixer_get(ctl, MDSS_MDP_MIXER_MUX_LEFT);
  163. if (mixer) {
  164. rc = mdss_mdp_cmd_tearcheck_cfg(ctl, mixer);
  165. if (rc)
  166. goto err;
  167. }
  168. mixer = mdss_mdp_mixer_get(ctl, MDSS_MDP_MIXER_MUX_RIGHT);
  169. if (mixer)
  170. rc = mdss_mdp_cmd_tearcheck_cfg(ctl, mixer);
  171. err:
  172. return rc;
  173. }
  174. static inline void mdss_mdp_cmd_clk_on(struct mdss_mdp_cmd_ctx *ctx)
  175. {
  176. unsigned long flags;
  177. struct mdss_data_type *mdata = mdss_mdp_get_mdata();
  178. int irq_en, rc;
  179. if (!ctx->panel_on) {
  180. pr_info("%s: Ignore clock on because the unblank does not finished\n", __func__);
  181. return;
  182. }
  183. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  184. xlog(__func__, ctx->panel_ndx, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, 0, 0);
  185. #endif
  186. mutex_lock(&ctx->clk_mtx);
  187. MDSS_XLOG(ctx->pp_num, ctx->koff_cnt, ctx->clk_enabled,
  188. ctx->rdptr_enabled);
  189. if (!ctx->clk_enabled) {
  190. mdss_bus_bandwidth_ctrl(true);
  191. ctx->clk_enabled = 1;
  192. if (cancel_delayed_work_sync(&ctx->ulps_work))
  193. pr_debug("deleted pending ulps work\n");
  194. rc = mdss_iommu_ctrl(1);
  195. if (IS_ERR_VALUE(rc))
  196. pr_err("IOMMU attach failed\n");
  197. mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
  198. if (ctx->ulps) {
  199. if (mdss_mdp_cmd_tearcheck_setup(ctx->ctl))
  200. pr_warn("tearcheck setup failed\n");
  201. mdss_mdp_ctl_intf_event(ctx->ctl,
  202. MDSS_EVENT_DSI_ULPS_CTRL, (void *)0);
  203. ctx->ulps = false;
  204. }
  205. mdss_mdp_ctl_intf_event
  206. (ctx->ctl, MDSS_EVENT_PANEL_CLK_CTRL, (void *)1);
  207. mdss_mdp_hist_intr_setup(&mdata->hist_intr, MDSS_IRQ_RESUME);
  208. }
  209. spin_lock_irqsave(&ctx->clk_lock, flags);
  210. irq_en = !ctx->rdptr_enabled;
  211. ctx->rdptr_enabled = VSYNC_EXPIRE_TICK;
  212. spin_unlock_irqrestore(&ctx->clk_lock, flags);
  213. if (irq_en)
  214. mdss_mdp_irq_enable(MDSS_MDP_IRQ_PING_PONG_RD_PTR, ctx->pp_num);
  215. mutex_unlock(&ctx->clk_mtx);
  216. }
  217. static inline void mdss_mdp_cmd_clk_off(struct mdss_mdp_cmd_ctx *ctx)
  218. {
  219. unsigned long flags;
  220. struct mdss_data_type *mdata = mdss_mdp_get_mdata();
  221. int set_clk_off = 0;
  222. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  223. xlog(__func__,ctx->panel_ndx, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, 0, 0);
  224. #endif
  225. mutex_lock(&ctx->clk_mtx);
  226. MDSS_XLOG(ctx->pp_num, ctx->koff_cnt, ctx->clk_enabled,
  227. ctx->rdptr_enabled);
  228. spin_lock_irqsave(&ctx->clk_lock, flags);
  229. if (!ctx->rdptr_enabled)
  230. set_clk_off = 1;
  231. spin_unlock_irqrestore(&ctx->clk_lock, flags);
  232. if ((ctx->clk_enabled && set_clk_off) || (get_lcd_attached() == 0)) {
  233. ctx->clk_enabled = 0;
  234. mdss_mdp_hist_intr_setup(&mdata->hist_intr, MDSS_IRQ_SUSPEND);
  235. mdss_mdp_ctl_intf_event
  236. (ctx->ctl, MDSS_EVENT_PANEL_CLK_CTRL, (void *)0);
  237. mdss_iommu_ctrl(0);
  238. mdss_bus_bandwidth_ctrl(false);
  239. mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
  240. if (ctx->panel_on)
  241. schedule_delayed_work(&ctx->ulps_work, ULPS_ENTER_TIME);
  242. }
  243. mutex_unlock(&ctx->clk_mtx);
  244. }
  245. #if defined(DYNAMIC_FPS_USE_TE_CTRL)
  246. int dynamic_fps_use_te_ctrl_value;
  247. #endif
  248. #if defined(CONFIG_LCD_HMT)
  249. int skip_te_enable = 0;
  250. static unsigned int skip_te = 0;
  251. #endif
  252. #if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OCTA_CMD_WQHD_PT_PANEL)
  253. int te;
  254. int te_cnt;
  255. int te_set_done;
  256. struct completion te_check_comp;
  257. int get_lcd_ldi_info(void);
  258. #endif
  259. static void mdss_mdp_cmd_readptr_done(void *arg)
  260. {
  261. struct mdss_mdp_ctl *ctl = arg;
  262. struct mdss_mdp_cmd_ctx *ctx = ctl->priv_data;
  263. struct mdss_mdp_vsync_handler *tmp;
  264. ktime_t vsync_time;
  265. #if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OCTA_CMD_WQHD_PT_PANEL)
  266. static ktime_t vsync_time1;
  267. static ktime_t vsync_time2;
  268. static int i = 0;
  269. static int time1 = 0, time2 = 0;
  270. #endif
  271. static long long vsync[2];
  272. long long duration = 16000;
  273. static int index;
  274. static int add_value = 1;
  275. // pr_err("mdss_mdp_cmd_readptr_done\n");
  276. #if defined(DYNAMIC_FPS_USE_TE_CTRL)
  277. if(dynamic_fps_use_te_ctrl)
  278. {
  279. if(dynamic_fps_use_te_ctrl_value)
  280. {
  281. dynamic_fps_use_te_ctrl_value = 0;
  282. return;
  283. }
  284. dynamic_fps_use_te_ctrl_value = 1;
  285. }
  286. #endif
  287. if (!ctx) {
  288. pr_err("invalid ctx\n");
  289. return;
  290. }
  291. #if defined(CONFIG_LCD_HMT)
  292. if (skip_te_enable) {
  293. if (skip_te) {
  294. pr_debug("%s : Skip TE Signal \n",__func__);
  295. skip_te = 0;
  296. return;
  297. }
  298. skip_te = 1;
  299. }
  300. #endif
  301. ATRACE_BEGIN(__func__);
  302. vsync_time = ktime_get();
  303. vsync[index] = ktime_to_us(vsync_time);
  304. index += add_value;
  305. add_value *= -1;
  306. if (vsync[0] && vsync[1])
  307. duration = vsync[index + add_value] - vsync[index];
  308. ctl->vsync_cnt++;
  309. MDSS_XLOG(0xFFFF, ctl->num, ctx->koff_cnt, ctx->clk_enabled,
  310. ctx->rdptr_enabled, duration);
  311. if (duration <= 8000 || duration >= 22000)
  312. pr_err("[DEBUG]%s:time : %lld, duration : %lld\n",
  313. __func__, vsync[index + add_value], duration);
  314. #if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OCTA_CMD_WQHD_PT_PANEL)
  315. if (get_lcd_ldi_info()) {
  316. if (te_set_done == TE_SET_START) {
  317. pr_debug("%s : TE_SET_START...",__func__);
  318. if (i % 2 == 0) {
  319. vsync_time1 = ktime_get();
  320. time1 = (int)ktime_to_us(vsync_time1);
  321. te = time1 && time2 ? time1 - time2 : 0;
  322. pr_debug("[%s] : ktime = %d\n",__func__, te);
  323. } else {
  324. vsync_time2 = ktime_get();
  325. time2 = (int)ktime_to_us(vsync_time2);
  326. te = time1 && time2 ? time2 - time1 : 0;
  327. pr_debug("[%s] : ktime = %d\n",__func__, te);
  328. }
  329. i++;
  330. pr_debug("[%s] TE = %d\n",__func__, te);
  331. spin_lock(&ctx->te_lock);
  332. te_cnt++;
  333. if (te_cnt >= 2) { // check TE using only two signal..
  334. pr_debug(">>>> te_check_comp COMPLETE (%d) <<<< \n", te_cnt);
  335. complete(&te_check_comp);
  336. }
  337. spin_unlock(&ctx->te_lock);
  338. } else {
  339. pr_debug("%s : not TE_SET_START...",__func__);
  340. }
  341. }
  342. #endif
  343. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  344. xlog(__func__,ctl->num, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, 0, 0x88888);
  345. #endif
  346. spin_lock(&ctx->clk_lock);
  347. list_for_each_entry(tmp, &ctx->vsync_handlers, list) {
  348. if (tmp->enabled && !tmp->cmd_post_flush)
  349. tmp->vsync_handler(ctl, vsync_time);
  350. }
  351. if (!ctx->vsync_enabled) {
  352. if (ctx->rdptr_enabled)
  353. ctx->rdptr_enabled--;
  354. #if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OCTA_CMD_WQHD_PT_PANEL)
  355. if (get_lcd_ldi_info())
  356. if (!(te_set_done == TE_SET_DONE || te_set_done == TE_SET_FAIL))
  357. {
  358. pr_info("now restoring TE/ rdptr_enabled++\n");
  359. if (ctx->rdptr_enabled == 0)
  360. ctx->rdptr_enabled++;
  361. }
  362. #endif
  363. /* keep clk on during kickoff */
  364. if (ctx->rdptr_enabled == 0 && atomic_read(&ctx->koff_cnt))
  365. ctx->rdptr_enabled++;
  366. }
  367. if (ctx->rdptr_enabled == 0) {
  368. mdss_mdp_irq_disable_nosync
  369. (MDSS_MDP_IRQ_PING_PONG_RD_PTR, ctx->pp_num);
  370. complete(&ctx->stop_comp);
  371. schedule_work(&ctx->clk_work);
  372. index = 0;
  373. add_value = 1;
  374. vsync[0] = vsync[1] = 0;
  375. }
  376. ATRACE_END(__func__);
  377. spin_unlock(&ctx->clk_lock);
  378. }
  379. static void mdss_mdp_cmd_underflow_recovery(void *data)
  380. {
  381. struct mdss_mdp_cmd_ctx *ctx = data;
  382. unsigned long flags;
  383. if (!data) {
  384. pr_err("%s: invalid ctx\n", __func__);
  385. return;
  386. }
  387. if (!ctx->ctl)
  388. return;
  389. spin_lock_irqsave(&ctx->clk_lock, flags);
  390. if (atomic_read(&ctx->koff_cnt)) {
  391. mdss_mdp_ctl_reset(ctx->ctl);
  392. pr_debug("%s: intf_num=%d\n", __func__,
  393. ctx->ctl->intf_num);
  394. atomic_dec(&ctx->koff_cnt);
  395. mdss_mdp_irq_disable_nosync(MDSS_MDP_IRQ_PING_PONG_COMP,
  396. ctx->pp_num);
  397. }
  398. spin_unlock_irqrestore(&ctx->clk_lock, flags);
  399. }
  400. #if 0
  401. static void mdss_mdp_cmd_pingpong_recovery(struct mdss_mdp_cmd_ctx *ctx)
  402. {
  403. unsigned long flags;
  404. if (!ctx) {
  405. pr_err("%s: invalid ctx\n", __func__);
  406. return;
  407. }
  408. if (!ctx->ctl)
  409. return;
  410. spin_lock_irqsave(&ctx->clk_lock, flags);
  411. if (ctx->koff_cnt) {
  412. mdss_mdp_ctl_reset(ctx->ctl);
  413. pr_debug("%s: intf_num=%d\n", __func__,
  414. ctx->ctl->intf_num);
  415. ctx->koff_cnt--;
  416. mdss_mdp_irq_disable_nosync(MDSS_MDP_IRQ_PING_PONG_COMP,
  417. ctx->pp_num);
  418. complete_all(&ctx->pp_comp);
  419. }
  420. spin_unlock_irqrestore(&ctx->clk_lock, flags);
  421. }
  422. #endif
  423. static void mdss_mdp_cmd_pingpong_done(void *arg)
  424. {
  425. struct mdss_mdp_ctl *ctl = arg;
  426. struct mdss_mdp_cmd_ctx *ctx = ctl->priv_data;
  427. struct mdss_mdp_vsync_handler *tmp;
  428. ktime_t vsync_time;
  429. #if defined (CONFIG_FB_MSM_MDSS_DBG_SEQ_TICK)
  430. mdss_dbg_tick_save(PP_DONE);
  431. #endif
  432. if (!ctx) {
  433. pr_err("%s: invalid ctx\n", __func__);
  434. return;
  435. }
  436. mdss_mdp_ctl_perf_set_transaction_status(ctl,
  437. PERF_HW_MDP_STATE, PERF_STATUS_DONE);
  438. spin_lock(&ctx->clk_lock);
  439. list_for_each_entry(tmp, &ctx->vsync_handlers, list) {
  440. if (tmp->enabled && tmp->cmd_post_flush)
  441. tmp->vsync_handler(ctl, vsync_time);
  442. }
  443. mdss_mdp_irq_disable_nosync(MDSS_MDP_IRQ_PING_PONG_COMP, ctx->pp_num);
  444. MDSS_XLOG(ctl->num, ctx->koff_cnt, ctx->clk_enabled,
  445. ctx->rdptr_enabled);
  446. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  447. xlog(__func__, ctl->num, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, ctl->roi_bkup.w, ctl->roi_bkup.h);
  448. #endif
  449. if (atomic_add_unless(&ctx->koff_cnt, -1, 0)) {
  450. if (atomic_read(&ctx->koff_cnt))
  451. pr_err("%s: too many kickoffs=%d!\n", __func__,
  452. atomic_read(&ctx->koff_cnt));
  453. if (mdss_mdp_cmd_do_notifier(ctx)) {
  454. atomic_inc(&ctx->pp_done_cnt);
  455. schedule_work(&ctx->pp_done_work);
  456. }
  457. wake_up_all(&ctx->pp_waitq);
  458. } else {
  459. pr_err("%s: should not have pingpong interrupt!\n", __func__);
  460. }
  461. trace_mdp_cmd_pingpong_done(ctl, ctx->pp_num,
  462. atomic_read(&ctx->koff_cnt));
  463. pr_debug("%s: ctl_num=%d intf_num=%d ctx=%d kcnt=%d\n", __func__,
  464. ctl->num, ctl->intf_num, ctx->pp_num,
  465. atomic_read(&ctx->koff_cnt));
  466. spin_unlock(&ctx->clk_lock);
  467. }
  468. static void pingpong_done_work(struct work_struct *work)
  469. {
  470. struct mdss_mdp_cmd_ctx *ctx =
  471. container_of(work, typeof(*ctx), pp_done_work);
  472. if (ctx->ctl) {
  473. while (atomic_add_unless(&ctx->pp_done_cnt, -1, 0))
  474. mdss_mdp_ctl_notify(ctx->ctl, MDP_NOTIFY_FRAME_DONE);
  475. #if !defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OCTA_CMD_FHD_FA2_PT_PANEL)
  476. mdss_mdp_ctl_perf_release_bw(ctx->ctl);
  477. #endif
  478. }
  479. }
  480. static void clk_ctrl_work(struct work_struct *work)
  481. {
  482. struct mdss_mdp_cmd_ctx *ctx =
  483. container_of(work, typeof(*ctx), clk_work);
  484. if (!ctx) {
  485. pr_err("%s: invalid ctx\n", __func__);
  486. return;
  487. }
  488. mdss_mdp_cmd_clk_off(ctx);
  489. }
  490. static void __mdss_mdp_cmd_ulps_work(struct work_struct *work)
  491. {
  492. struct delayed_work *dw = to_delayed_work(work);
  493. struct mdss_data_type *mdata = mdss_mdp_get_mdata();
  494. struct mdss_mdp_cmd_ctx *ctx =
  495. container_of(dw, struct mdss_mdp_cmd_ctx, ulps_work);
  496. if (!ctx) {
  497. pr_err("%s: invalid ctx\n", __func__);
  498. return;
  499. }
  500. if (!ctx->panel_on) {
  501. pr_err("Panel is off. skipping ULPS configuration\n");
  502. return;
  503. }
  504. if (!mdss_mdp_ctl_intf_event(ctx->ctl, MDSS_EVENT_DSI_ULPS_CTRL,
  505. (void *)1)) {
  506. ctx->ulps = true;
  507. if (mdata->idle_pc_enabled) {
  508. ctx->ctl->play_cnt = 0;
  509. mdss_mdp_footswitch_ctrl_idle_pc(0,
  510. &ctx->ctl->mfd->pdev->dev);
  511. }
  512. }
  513. }
  514. static int mdss_mdp_cmd_add_vsync_handler(struct mdss_mdp_ctl *ctl,
  515. struct mdss_mdp_vsync_handler *handle)
  516. {
  517. struct mdss_mdp_cmd_ctx *ctx;
  518. unsigned long flags;
  519. bool enable_rdptr = false;
  520. ctx = (struct mdss_mdp_cmd_ctx *) ctl->priv_data;
  521. if (!ctx) {
  522. pr_err("%s: invalid ctx\n", __func__);
  523. return -ENODEV;
  524. }
  525. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  526. xlog(__func__, ctl->num, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, 0, 0);
  527. #endif
  528. MDSS_XLOG(ctl->num, ctx->koff_cnt, ctx->clk_enabled,
  529. ctx->rdptr_enabled);
  530. spin_lock_irqsave(&ctx->clk_lock, flags);
  531. if (!handle->enabled) {
  532. handle->enabled = true;
  533. list_add(&handle->list, &ctx->vsync_handlers);
  534. enable_rdptr = !handle->cmd_post_flush;
  535. if (enable_rdptr)
  536. ctx->vsync_enabled++;
  537. }
  538. spin_unlock_irqrestore(&ctx->clk_lock, flags);
  539. if (enable_rdptr)
  540. mdss_mdp_cmd_clk_on(ctx);
  541. return 0;
  542. }
  543. static int mdss_mdp_cmd_remove_vsync_handler(struct mdss_mdp_ctl *ctl,
  544. struct mdss_mdp_vsync_handler *handle)
  545. {
  546. struct mdss_mdp_cmd_ctx *ctx;
  547. unsigned long flags;
  548. ctx = (struct mdss_mdp_cmd_ctx *) ctl->priv_data;
  549. if (!ctx) {
  550. pr_err("%s: invalid ctx\n", __func__);
  551. return -ENODEV;
  552. }
  553. MDSS_XLOG(ctl->num, ctx->koff_cnt, ctx->clk_enabled,
  554. ctx->rdptr_enabled, 0x88888);
  555. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  556. xlog(__func__, ctl->num, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, 0, 0x88888);
  557. #endif
  558. spin_lock_irqsave(&ctx->clk_lock, flags);
  559. if (handle->enabled) {
  560. handle->enabled = false;
  561. list_del_init(&handle->list);
  562. if (!handle->cmd_post_flush) {
  563. if (ctx->vsync_enabled)
  564. ctx->vsync_enabled--;
  565. else
  566. WARN(1, "unbalanced vsync disable");
  567. }
  568. }
  569. spin_unlock_irqrestore(&ctx->clk_lock, flags);
  570. return 0;
  571. }
  572. int mdss_mdp_cmd_reconfigure_splash_done(struct mdss_mdp_ctl *ctl, bool handoff)
  573. {
  574. struct mdss_panel_data *pdata;
  575. int ret = 0;
  576. pdata = ctl->panel_data;
  577. pdata->panel_info.cont_splash_enabled = 0;
  578. #if !defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OCTA_CMD_WQXGA_S6TNMR7_PT_PANEL)
  579. mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_PANEL_CLK_CTRL, (void *)0);
  580. #endif
  581. return ret;
  582. }
  583. void mdp5_dump_regs(void)
  584. {
  585. int i, z, start, len;
  586. int offsets[] = {0x0};
  587. int length[] = {19776};
  588. printk("%s: =============MDSS Reg DUMP==============\n", __func__);
  589. for (i = 0; i < sizeof(offsets) / sizeof(int); i++) {
  590. start = offsets[i];
  591. len = length[i];
  592. printk("-------- Address %05x: -------\n", start);
  593. for (z = 0; z < len; z++) {
  594. if ((z & 3) == 0)
  595. printk("%05x:", start + (z * 4));
  596. printk(" %08x", MDSS_MDP_REG_READ(start + (z * 4)));
  597. if ((z & 3) == 3)
  598. printk("\n");
  599. }
  600. if ((z & 3) != 0)
  601. printk("\n");
  602. }
  603. printk("%s: ============= END ==============\n", __func__);
  604. }
  605. static int mdss_mdp_cmd_wait4pingpong(struct mdss_mdp_ctl *ctl, void *arg)
  606. {
  607. struct mdss_mdp_cmd_ctx *ctx;
  608. struct mdss_panel_data *pdata;
  609. unsigned long flags;
  610. int rc = 0;
  611. ctx = (struct mdss_mdp_cmd_ctx *) ctl->priv_data;
  612. if (!ctx) {
  613. pr_err("invalid ctx\n");
  614. return -ENODEV;
  615. }
  616. pdata = ctl->panel_data;
  617. ctl->roi_bkup.w = ctl->width;
  618. ctl->roi_bkup.h = ctl->height;
  619. MDSS_XLOG(ctl->num, ctx->koff_cnt, ctx->clk_enabled,
  620. ctx->rdptr_enabled, ctl->roi_bkup.w,
  621. ctl->roi_bkup.h);
  622. pr_debug("%s: intf_num=%d ctx=%pK koff_cnt=%d\n", __func__,
  623. ctl->intf_num, ctx, atomic_read(&ctx->koff_cnt));
  624. rc = wait_event_timeout(ctx->pp_waitq,
  625. atomic_read(&ctx->koff_cnt) == 0,
  626. KOFF_TIMEOUT);
  627. if (rc <= 0) {
  628. u32 status, mask;
  629. mask = BIT(MDSS_MDP_IRQ_PING_PONG_COMP + ctx->pp_num);
  630. status = mask & readl_relaxed(ctl->mdata->mdp_base +
  631. MDSS_MDP_REG_INTR_STATUS);
  632. if (status) {
  633. WARN(1, "pp done but irq not triggered\n");
  634. mdss_mdp_irq_clear(ctl->mdata,
  635. MDSS_MDP_IRQ_PING_PONG_COMP,
  636. ctx->pp_num);
  637. local_irq_save(flags);
  638. mdss_mdp_cmd_pingpong_done(ctl);
  639. local_irq_restore(flags);
  640. rc = 1;
  641. }
  642. rc = atomic_read(&ctx->koff_cnt) == 0;
  643. }
  644. if (rc <= 0) {
  645. if (!ctx->pp_timeout_report_cnt) {
  646. WARN(1, "cmd kickoff timed out (%d) ctl=%d\n",
  647. rc, ctl->num);
  648. mdss_dsi_debug_check_te(pdata);
  649. MDSS_XLOG_TOUT_HANDLER("mdp", "dsi0", "dsi1",
  650. "edp", "hdmi", "panic");
  651. }
  652. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  653. dumpreg();
  654. mdp5_dump_regs();
  655. mdss_mdp_debug_bus();
  656. xlog_dump();
  657. #if 0
  658. mdss_mdp_cmd_pingpong_recovery(ctx);
  659. #else
  660. panic("Pingpong Timeout");
  661. #endif
  662. #endif
  663. ctx->pp_timeout_report_cnt++;
  664. rc = -EPERM;
  665. mdss_mdp_ctl_notify(ctl, MDP_NOTIFY_FRAME_TIMEOUT);
  666. atomic_add_unless(&ctx->koff_cnt, -1, 0);
  667. } else {
  668. rc = 0;
  669. ctx->pp_timeout_report_cnt = 0;
  670. }
  671. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  672. xlog(__func__,ctl->num, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, 0, rc);
  673. #endif
  674. /* signal any pending ping pong done events */
  675. while (atomic_add_unless(&ctx->pp_done_cnt, -1, 0))
  676. mdss_mdp_ctl_notify(ctx->ctl, MDP_NOTIFY_FRAME_DONE);
  677. MDSS_XLOG(ctl->num, atomic_read(&ctx->koff_cnt), ctx->clk_enabled,
  678. ctx->rdptr_enabled, rc);
  679. return rc;
  680. }
  681. static int mdss_mdp_cmd_do_notifier(struct mdss_mdp_cmd_ctx *ctx)
  682. {
  683. struct mdss_mdp_cmd_ctx *sctx;
  684. sctx = ctx->sync_ctx;
  685. if (!sctx || atomic_read(&sctx->koff_cnt) == 0)
  686. return 1;
  687. return 0;
  688. }
  689. static void mdss_mdp_cmd_set_sync_ctx(
  690. struct mdss_mdp_ctl *ctl, struct mdss_mdp_ctl *sctl)
  691. {
  692. struct mdss_mdp_cmd_ctx *ctx, *sctx;
  693. ctx = (struct mdss_mdp_cmd_ctx *)ctl->priv_data;
  694. if (!sctl) {
  695. ctx->sync_ctx = NULL;
  696. return;
  697. }
  698. sctx = (struct mdss_mdp_cmd_ctx *)sctl->priv_data;
  699. if (!sctl->roi.w && !sctl->roi.h) {
  700. /* left only */
  701. ctx->sync_ctx = NULL;
  702. sctx->sync_ctx = NULL;
  703. } else {
  704. /* left + right */
  705. ctx->sync_ctx = sctx;
  706. sctx->sync_ctx = ctx;
  707. }
  708. }
  709. static int mdss_mdp_cmd_set_partial_roi(struct mdss_mdp_ctl *ctl)
  710. {
  711. int rc = 0;
  712. if (ctl->roi.w && ctl->roi.h && ctl->roi_changed &&
  713. ctl->panel_data->panel_info.partial_update_enabled) {
  714. ctl->panel_data->panel_info.roi_x = ctl->roi.x;
  715. ctl->panel_data->panel_info.roi_y = ctl->roi.y;
  716. ctl->panel_data->panel_info.roi_w = ctl->roi.w;
  717. ctl->panel_data->panel_info.roi_h = ctl->roi.h;
  718. rc = mdss_mdp_ctl_intf_event(ctl,
  719. MDSS_EVENT_ENABLE_PARTIAL_UPDATE, NULL);
  720. }
  721. return rc;
  722. }
  723. int mdss_mdp_cmd_kickoff(struct mdss_mdp_ctl *ctl, void *arg)
  724. {
  725. struct mdss_mdp_cmd_ctx *ctx, *sctx = NULL;
  726. int rc;
  727. ATRACE_BEGIN(__func__);
  728. ctx = (struct mdss_mdp_cmd_ctx *) ctl->priv_data;
  729. if (!ctx) {
  730. pr_err("invalid ctx\n");
  731. return -ENODEV;
  732. }
  733. if (get_lcd_attached() == 0) {
  734. pr_err("%s : lcd is not attached..\n",__func__);
  735. return -ENODEV;
  736. }
  737. mdss_mdp_ctl_perf_set_transaction_status(ctl,
  738. PERF_HW_MDP_STATE, PERF_STATUS_BUSY);
  739. pr_debug("%s:+\n", __func__);
  740. if (ctx->panel_on == 0) {
  741. rc = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_UNBLANK, NULL);
  742. WARN(rc, "intf %d unblank error (%d)\n", ctl->intf_num, rc);
  743. ctx->panel_on++;
  744. rc = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_PANEL_ON, NULL);
  745. WARN(rc, "intf %d panel on error (%d)\n", ctl->intf_num, rc);
  746. mdss_mdp_ctl_intf_event(ctl,
  747. MDSS_EVENT_REGISTER_RECOVERY_HANDLER,
  748. (void *)&ctx->recovery);
  749. }
  750. MDSS_XLOG(ctl->num, ctl->roi.x, ctl->roi.y, ctl->roi.w,
  751. ctl->roi.h);
  752. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  753. xlog(__func__, ctl->num, ctl->roi.x, ctl->roi.y, ctl->roi.w, ctl->roi.h, 0x1234);
  754. #endif
  755. atomic_inc(&ctx->koff_cnt);
  756. if (sctx)
  757. atomic_inc(&sctx->koff_cnt);
  758. trace_mdp_cmd_kickoff(ctl->num, atomic_read(&ctx->koff_cnt));
  759. mdss_mdp_cmd_clk_on(ctx);
  760. mdss_mdp_cmd_set_partial_roi(ctl);
  761. /*
  762. * tx dcs command if had any
  763. */
  764. mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_DSI_CMDLIST_KOFF, NULL);
  765. mdss_mdp_cmd_set_sync_ctx(ctl, NULL);
  766. mdss_mdp_irq_enable(MDSS_MDP_IRQ_PING_PONG_COMP, ctx->pp_num);
  767. mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_START, 1);
  768. mdss_mdp_ctl_perf_set_transaction_status(ctl,
  769. PERF_SW_COMMIT_STATE, PERF_STATUS_DONE);
  770. mb();
  771. MDSS_XLOG(ctl->num, ctx->koff_cnt, ctx->clk_enabled,
  772. ctx->rdptr_enabled);
  773. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  774. {
  775. void mdss_mdp_mixer_read(void);
  776. mdss_mdp_mixer_read();
  777. }
  778. #endif
  779. ATRACE_END(__func__);
  780. pr_debug("%s : -- \n", __func__);
  781. return 0;
  782. }
  783. int mdss_mdp_cmd_stop(struct mdss_mdp_ctl *ctl)
  784. {
  785. struct mdss_mdp_cmd_ctx *ctx;
  786. struct mdss_panel_info *pinfo = &ctl->panel_data->panel_info;
  787. unsigned long flags;
  788. struct mdss_mdp_vsync_handler *tmp, *handle;
  789. int need_wait = 0;
  790. int ret = 0;
  791. u8 timeout_status = 0;
  792. int hz;
  793. pr_debug("%s:+\n", __func__);
  794. if (get_lcd_attached() == 0) {
  795. pr_err("%s : lcd is not attached..\n",__func__);
  796. return 0;
  797. }
  798. ctx = (struct mdss_mdp_cmd_ctx *) ctl->priv_data;
  799. if (!ctx) {
  800. pr_err("invalid ctx\n");
  801. return -ENODEV;
  802. }
  803. list_for_each_entry_safe(handle, tmp, &ctx->vsync_handlers, list)
  804. mdss_mdp_cmd_remove_vsync_handler(ctl, handle);
  805. MDSS_XLOG(ctl->num, ctx->koff_cnt, ctx->clk_enabled,
  806. ctx->rdptr_enabled, XLOG_FUNC_ENTRY);
  807. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  808. xlog(__func__, ctl->num, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, 0, 0x11111);
  809. #endif
  810. spin_lock_irqsave(&ctx->clk_lock, flags);
  811. if (ctx->rdptr_enabled) {
  812. INIT_COMPLETION(ctx->stop_comp);
  813. need_wait = 1;
  814. }
  815. spin_unlock_irqrestore(&ctx->clk_lock, flags);
  816. hz = mdss_panel_get_framerate(&ctl->panel_data->panel_info);
  817. if (need_wait) {
  818. if (pinfo->alpm_event && pinfo->alpm_event(CHECK_CURRENT_STATUS))
  819. timeout_status = wait_for_completion_timeout(&ctx->stop_comp,\
  820. STOP_TIMEOUT_FOR_ALPM);
  821. else
  822. timeout_status = wait_for_completion_timeout(&ctx->stop_comp,\
  823. STOP_TIMEOUT(hz)); /*msecs_to_jiffies(1000));*/ //STOP_TIMEOUT(16 * 4 frames) -> 1000
  824. if (timeout_status <= 0) {
  825. WARN(1, "stop cmd time out\n");
  826. if (IS_ERR_OR_NULL(ctl->panel_data)) {
  827. pr_err("no panel data\n");
  828. } else {
  829. pinfo = &ctl->panel_data->panel_info;
  830. mdss_mdp_irq_disable
  831. (MDSS_MDP_IRQ_PING_PONG_RD_PTR,
  832. ctx->pp_num);
  833. ctx->rdptr_enabled = 0;
  834. }
  835. }
  836. }
  837. if (cancel_work_sync(&ctx->clk_work))
  838. pr_debug("no pending clk work\n");
  839. if (cancel_delayed_work_sync(&ctx->ulps_work))
  840. pr_debug("deleted pending ulps work\n");
  841. mdss_mdp_ctl_intf_event(ctl,
  842. MDSS_EVENT_REGISTER_RECOVERY_HANDLER,
  843. NULL);
  844. ctx->panel_on = 0;
  845. mdss_mdp_cmd_clk_off(ctx);
  846. flush_work(&ctx->pp_done_work);
  847. mdss_mdp_set_intr_callback(MDSS_MDP_IRQ_PING_PONG_RD_PTR, ctx->pp_num,
  848. NULL, NULL);
  849. mdss_mdp_set_intr_callback(MDSS_MDP_IRQ_PING_PONG_COMP, ctx->pp_num,
  850. NULL, NULL);
  851. memset(ctx, 0, sizeof(*ctx));
  852. ctl->priv_data = NULL;
  853. if (ctl->num == 0) {
  854. ret = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_BLANK, NULL);
  855. WARN(ret, "intf %d unblank error (%d)\n", ctl->intf_num, ret);
  856. ret = mdss_mdp_ctl_intf_event(ctl, MDSS_EVENT_PANEL_OFF, NULL);
  857. WARN(ret, "intf %d unblank error (%d)\n", ctl->intf_num, ret);
  858. }
  859. ctl->stop_fnc = NULL;
  860. ctl->display_fnc = NULL;
  861. ctl->wait_pingpong = NULL;
  862. ctl->add_vsync_handler = NULL;
  863. ctl->remove_vsync_handler = NULL;
  864. MDSS_XLOG(ctl->num, ctx->koff_cnt, ctx->clk_enabled,
  865. ctx->rdptr_enabled, XLOG_FUNC_EXIT);
  866. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  867. xlog(__func__, ctl->num, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, 0, 0x222222);
  868. #endif
  869. pr_debug("%s:-\n", __func__);
  870. return 0;
  871. }
  872. int mdss_mdp_cmd_start(struct mdss_mdp_ctl *ctl)
  873. {
  874. struct mdss_mdp_cmd_ctx *ctx;
  875. struct mdss_mdp_mixer *mixer;
  876. int i, ret;
  877. pr_debug("%s:+\n", __func__);
  878. mixer = mdss_mdp_mixer_get(ctl, MDSS_MDP_MIXER_MUX_LEFT);
  879. if (!mixer) {
  880. pr_err("mixer not setup correctly\n");
  881. return -ENODEV;
  882. }
  883. for (i = 0; i < MAX_SESSIONS; i++) {
  884. ctx = &mdss_mdp_cmd_ctx_list[i];
  885. if (ctx->ref_cnt == 0) {
  886. ctx->ref_cnt++;
  887. break;
  888. }
  889. }
  890. if (i == MAX_SESSIONS) {
  891. pr_err("too many sessions\n");
  892. return -ENOMEM;
  893. }
  894. ctl->priv_data = ctx;
  895. if (!ctx) {
  896. pr_err("invalid ctx\n");
  897. return -ENODEV;
  898. }
  899. ctx->ctl = ctl;
  900. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  901. ctx->panel_ndx = ctl->panel_ndx;
  902. #endif
  903. ctx->pp_num = mixer->num;
  904. ctx->pp_timeout_report_cnt = 0;
  905. init_waitqueue_head(&ctx->pp_waitq);
  906. init_completion(&ctx->stop_comp);
  907. spin_lock_init(&ctx->clk_lock);
  908. #if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OCTA_CMD_WQHD_PT_PANEL)
  909. spin_lock_init(&ctx->te_lock);
  910. #endif
  911. mutex_init(&ctx->clk_mtx);
  912. INIT_WORK(&ctx->clk_work, clk_ctrl_work);
  913. INIT_DELAYED_WORK(&ctx->ulps_work, __mdss_mdp_cmd_ulps_work);
  914. INIT_WORK(&ctx->pp_done_work, pingpong_done_work);
  915. atomic_set(&ctx->pp_done_cnt, 0);
  916. INIT_LIST_HEAD(&ctx->vsync_handlers);
  917. ctx->recovery.fxn = mdss_mdp_cmd_underflow_recovery;
  918. ctx->recovery.data = ctx;
  919. pr_debug("%s: ctx=%pK num=%d mixer=%d\n", __func__,
  920. ctx, ctx->pp_num, mixer->num);
  921. MDSS_XLOG(ctl->num, ctx->koff_cnt, ctx->clk_enabled,
  922. ctx->rdptr_enabled);
  923. mdss_mdp_set_intr_callback(MDSS_MDP_IRQ_PING_PONG_RD_PTR, ctx->pp_num,
  924. mdss_mdp_cmd_readptr_done, ctl);
  925. #if defined (CONFIG_FB_MSM_MDSS_DSI_DBG)
  926. xlog(__func__, ctl->num, atomic_read(&ctx->koff_cnt), ctx->clk_enabled, ctx->rdptr_enabled, 0, 0);
  927. #endif
  928. mdss_mdp_set_intr_callback(MDSS_MDP_IRQ_PING_PONG_COMP, ctx->pp_num,
  929. mdss_mdp_cmd_pingpong_done, ctl);
  930. ret = mdss_mdp_cmd_tearcheck_setup(ctl);
  931. if (ret) {
  932. pr_err("tearcheck setup failed\n");
  933. return ret;
  934. }
  935. ctl->stop_fnc = mdss_mdp_cmd_stop;
  936. ctl->display_fnc = mdss_mdp_cmd_kickoff;
  937. ctl->wait_pingpong = mdss_mdp_cmd_wait4pingpong;
  938. ctl->add_vsync_handler = mdss_mdp_cmd_add_vsync_handler;
  939. ctl->remove_vsync_handler = mdss_mdp_cmd_remove_vsync_handler;
  940. ctl->read_line_cnt_fnc = mdss_mdp_cmd_line_count;
  941. pr_debug("%s:-\n", __func__);
  942. return 0;
  943. }