dsi_host_v2.c 46 KB

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  1. /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. */
  13. #include <linux/module.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/delay.h>
  17. #include <linux/io.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/slab.h>
  20. #include <linux/iopoll.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/of_device.h>
  23. #include "dsi_v2.h"
  24. #include "dsi_io_v2.h"
  25. #include "dsi_host_v2.h"
  26. #include "mdss_debug.h"
  27. #include "mdp3.h"
  28. #define DSI_POLL_SLEEP_US 1000
  29. #define DSI_POLL_TIMEOUT_US 16000
  30. #define DSI_ESC_CLK_RATE 19200000
  31. #define DSI_DMA_CMD_TIMEOUT_MS 200
  32. #define VSYNC_PERIOD 17
  33. #define DSI_MAX_PKT_SIZE 10
  34. #define DSI_SHORT_PKT_DATA_SIZE 2
  35. #define DSI_MAX_BYTES_TO_READ 16
  36. struct dsi_host_v2_private {
  37. int irq_no;
  38. unsigned char *dsi_base;
  39. size_t dsi_reg_size;
  40. struct device dis_dev;
  41. int clk_count;
  42. int dsi_on;
  43. void (*debug_enable_clk)(int on);
  44. };
  45. static struct dsi_host_v2_private *dsi_host_private;
  46. static int msm_dsi_clk_ctrl(struct mdss_panel_data *pdata, int enable);
  47. #if defined(CONFIG_FB_MSM_MDSS_DSI_DBG)
  48. extern int dsi_ctrl_on;
  49. extern unsigned char *dsi_ctrl_base;
  50. extern void dumpreg(void);
  51. extern void mdp3_dump_clk(void);
  52. #endif
  53. int msm_dsi_init(void)
  54. {
  55. if (!dsi_host_private) {
  56. dsi_host_private = kzalloc(sizeof(struct dsi_host_v2_private),
  57. GFP_KERNEL);
  58. if (!dsi_host_private) {
  59. pr_err("fail to alloc dsi host private data\n");
  60. return -ENOMEM;
  61. }
  62. }
  63. return 0;
  64. }
  65. void msm_dsi_deinit(void)
  66. {
  67. kfree(dsi_host_private);
  68. dsi_host_private = NULL;
  69. }
  70. void msm_dsi_ack_err_status(unsigned char *ctrl_base)
  71. {
  72. u32 status;
  73. status = MIPI_INP(ctrl_base + DSI_ACK_ERR_STATUS);
  74. if (status) {
  75. MIPI_OUTP(ctrl_base + DSI_ACK_ERR_STATUS, status);
  76. /* Writing of an extra 0 needed to clear error bits */
  77. MIPI_OUTP(ctrl_base + DSI_ACK_ERR_STATUS, 0);
  78. pr_err("%s: status=%x\n", __func__, status);
  79. }
  80. }
  81. void msm_dsi_timeout_status(unsigned char *ctrl_base)
  82. {
  83. u32 status;
  84. status = MIPI_INP(ctrl_base + DSI_TIMEOUT_STATUS);
  85. if (status & 0x0111) {
  86. MIPI_OUTP(ctrl_base + DSI_TIMEOUT_STATUS, status);
  87. pr_err("%s: status=%x\n", __func__, status);
  88. }
  89. }
  90. void msm_dsi_dln0_phy_err(unsigned char *ctrl_base)
  91. {
  92. u32 status;
  93. status = MIPI_INP(ctrl_base + DSI_DLN0_PHY_ERR);
  94. if (status & 0x011111) {
  95. MIPI_OUTP(ctrl_base + DSI_DLN0_PHY_ERR, status);
  96. pr_err("%s: status=%x\n", __func__, status);
  97. }
  98. }
  99. void msm_dsi_fifo_status(unsigned char *ctrl_base)
  100. {
  101. u32 status;
  102. status = MIPI_INP(ctrl_base + DSI_FIFO_STATUS);
  103. if (status & 0x44444489) {
  104. MIPI_OUTP(ctrl_base + DSI_FIFO_STATUS, status);
  105. pr_err("%s: status=%x\n", __func__, status);
  106. }
  107. }
  108. void msm_dsi_status(unsigned char *ctrl_base)
  109. {
  110. u32 status;
  111. status = MIPI_INP(ctrl_base + DSI_STATUS);
  112. if (status & 0x80000000) {
  113. MIPI_OUTP(ctrl_base + DSI_STATUS, status);
  114. pr_err("%s: status=%x\n", __func__, status);
  115. }
  116. }
  117. void msm_dsi_error(unsigned char *ctrl_base)
  118. {
  119. msm_dsi_ack_err_status(ctrl_base);
  120. msm_dsi_timeout_status(ctrl_base);
  121. msm_dsi_fifo_status(ctrl_base);
  122. msm_dsi_status(ctrl_base);
  123. msm_dsi_dln0_phy_err(ctrl_base);
  124. }
  125. static void msm_dsi_set_irq_mask(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask)
  126. {
  127. u32 intr_ctrl;
  128. intr_ctrl = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL);
  129. intr_ctrl |= mask;
  130. MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, intr_ctrl);
  131. }
  132. static void msm_dsi_clear_irq_mask(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask)
  133. {
  134. u32 intr_ctrl;
  135. intr_ctrl = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL);
  136. intr_ctrl &= ~mask;
  137. MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, intr_ctrl);
  138. }
  139. static void msm_dsi_set_irq(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask)
  140. {
  141. unsigned long flags;
  142. spin_lock_irqsave(&ctrl->irq_lock, flags);
  143. if (ctrl->dsi_irq_mask & mask) {
  144. spin_unlock_irqrestore(&ctrl->irq_lock, flags);
  145. return;
  146. }
  147. if (ctrl->dsi_irq_mask == 0) {
  148. enable_irq(dsi_host_private->irq_no);
  149. pr_debug("%s: IRQ Enable, mask=%x term=%x\n", __func__,
  150. (int)ctrl->dsi_irq_mask, (int)mask);
  151. }
  152. msm_dsi_set_irq_mask(ctrl, mask);
  153. ctrl->dsi_irq_mask |= mask;
  154. spin_unlock_irqrestore(&ctrl->irq_lock, flags);
  155. }
  156. static void msm_dsi_clear_irq(struct mdss_dsi_ctrl_pdata *ctrl, u32 mask)
  157. {
  158. unsigned long flags;
  159. spin_lock_irqsave(&ctrl->irq_lock, flags);
  160. if (!(ctrl->dsi_irq_mask & mask)) {
  161. spin_unlock_irqrestore(&ctrl->irq_lock, flags);
  162. return;
  163. }
  164. ctrl->dsi_irq_mask &= ~mask;
  165. if (ctrl->dsi_irq_mask == 0) {
  166. disable_irq(dsi_host_private->irq_no);
  167. pr_debug("%s: IRQ Disable, mask=%x term=%x\n", __func__,
  168. (int)ctrl->dsi_irq_mask, (int)mask);
  169. }
  170. msm_dsi_clear_irq_mask(ctrl, mask);
  171. spin_unlock_irqrestore(&ctrl->irq_lock, flags);
  172. }
  173. irqreturn_t msm_dsi_isr_handler(int irq, void *ptr)
  174. {
  175. u32 isr;
  176. struct mdss_dsi_ctrl_pdata *ctrl =
  177. (struct mdss_dsi_ctrl_pdata *)ptr;
  178. spin_lock(&ctrl->mdp_lock);
  179. if (ctrl->dsi_irq_mask == 0) {
  180. spin_unlock(&ctrl->mdp_lock);
  181. return IRQ_HANDLED;
  182. }
  183. isr = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL);
  184. MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, isr);
  185. pr_debug("%s: isr=%x", __func__, isr);
  186. if (isr & DSI_INTR_ERROR) {
  187. pr_err("%s: isr=%x %x", __func__, isr, (int)DSI_INTR_ERROR);
  188. msm_dsi_error(dsi_host_private->dsi_base);
  189. }
  190. if (isr & DSI_INTR_VIDEO_DONE)
  191. complete(&ctrl->video_comp);
  192. if (isr & DSI_INTR_CMD_DMA_DONE)
  193. complete(&ctrl->dma_comp);
  194. if (isr & DSI_INTR_BTA_DONE)
  195. complete(&ctrl->bta_comp);
  196. if (isr & DSI_INTR_CMD_MDP_DONE)
  197. complete(&ctrl->mdp_comp);
  198. spin_unlock(&ctrl->mdp_lock);
  199. return IRQ_HANDLED;
  200. }
  201. int msm_dsi_irq_init(struct device *dev, int irq_no,
  202. struct mdss_dsi_ctrl_pdata *ctrl)
  203. {
  204. int ret;
  205. u32 isr;
  206. msm_dsi_ahb_ctrl(1);
  207. isr = MIPI_INP(dsi_host_private->dsi_base + DSI_INT_CTRL);
  208. isr &= ~DSI_INTR_ALL_MASK;
  209. MIPI_OUTP(dsi_host_private->dsi_base + DSI_INT_CTRL, isr);
  210. msm_dsi_ahb_ctrl(0);
  211. ret = devm_request_irq(dev, irq_no, msm_dsi_isr_handler,
  212. IRQF_DISABLED, "DSI", ctrl);
  213. if (ret) {
  214. pr_err("msm_dsi_irq_init request_irq() failed!\n");
  215. return ret;
  216. }
  217. dsi_host_private->irq_no = irq_no;
  218. disable_irq(irq_no);
  219. return 0;
  220. }
  221. static void msm_dsi_get_cmd_engine(struct mdss_dsi_ctrl_pdata *ctrl)
  222. {
  223. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  224. u32 dsi_ctrl;
  225. if (ctrl->panel_mode == DSI_VIDEO_MODE) {
  226. dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL);
  227. MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl | 0x04);
  228. }
  229. }
  230. static void msm_dsi_release_cmd_engine(struct mdss_dsi_ctrl_pdata *ctrl)
  231. {
  232. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  233. u32 dsi_ctrl;
  234. if (ctrl->panel_mode == DSI_VIDEO_MODE) {
  235. dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL);
  236. dsi_ctrl &= ~0x04;
  237. MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl);
  238. }
  239. }
  240. static int msm_dsi_wait4mdp_done(struct mdss_dsi_ctrl_pdata *ctrl)
  241. {
  242. int rc;
  243. unsigned long flag;
  244. spin_lock_irqsave(&ctrl->mdp_lock, flag);
  245. INIT_COMPLETION(ctrl->mdp_comp);
  246. msm_dsi_set_irq(ctrl, DSI_INTR_CMD_MDP_DONE_MASK);
  247. spin_unlock_irqrestore(&ctrl->mdp_lock, flag);
  248. rc = wait_for_completion_timeout(&ctrl->mdp_comp,
  249. msecs_to_jiffies(VSYNC_PERIOD * 4));
  250. if (rc == 0) {
  251. pr_err("DSI wait 4 mdp done time out\n");
  252. #if defined(CONFIG_FB_MSM_MDSS_DSI_DBG)
  253. dumpreg();
  254. mdp3_dump_clk();
  255. panic("DSI wait 4 mdp done time out");
  256. #endif
  257. rc = -ETIME;
  258. } else if (!IS_ERR_VALUE(rc)) {
  259. rc = 0;
  260. }
  261. msm_dsi_clear_irq(ctrl, DSI_INTR_CMD_MDP_DONE_MASK);
  262. return rc;
  263. }
  264. void msm_dsi_cmd_mdp_busy(struct mdss_dsi_ctrl_pdata *ctrl)
  265. {
  266. int rc;
  267. u32 dsi_status;
  268. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  269. if (ctrl->panel_mode == DSI_VIDEO_MODE)
  270. return;
  271. dsi_status = MIPI_INP(ctrl_base + DSI_STATUS);
  272. if (dsi_status & 0x04) {
  273. pr_debug("dsi command engine is busy\n");
  274. rc = msm_dsi_wait4mdp_done(ctrl);
  275. if (rc)
  276. pr_err("Timed out waiting for mdp done");
  277. }
  278. }
  279. static int msm_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl)
  280. {
  281. int rc;
  282. unsigned long flag;
  283. spin_lock_irqsave(&ctrl->mdp_lock, flag);
  284. INIT_COMPLETION(ctrl->video_comp);
  285. msm_dsi_set_irq(ctrl, DSI_INTR_VIDEO_DONE_MASK);
  286. spin_unlock_irqrestore(&ctrl->mdp_lock, flag);
  287. rc = wait_for_completion_timeout(&ctrl->video_comp,
  288. msecs_to_jiffies(VSYNC_PERIOD * 4));
  289. if (rc == 0) {
  290. pr_err("DSI wait 4 video done time out\n");
  291. rc = -ETIME;
  292. } else if (!IS_ERR_VALUE(rc)) {
  293. rc = 0;
  294. }
  295. msm_dsi_clear_irq(ctrl, DSI_INTR_VIDEO_DONE_MASK);
  296. return rc;
  297. }
  298. static int msm_dsi_wait4video_eng_busy(struct mdss_dsi_ctrl_pdata *ctrl)
  299. {
  300. int rc = 0;
  301. u32 dsi_status;
  302. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  303. if (ctrl->panel_mode == DSI_CMD_MODE)
  304. return rc;
  305. dsi_status = MIPI_INP(ctrl_base + DSI_STATUS);
  306. if (dsi_status & 0x08) {
  307. pr_debug("dsi command in video mode wait for active region\n");
  308. rc = msm_dsi_wait4video_done(ctrl);
  309. /* delay 4-5 ms to skip BLLP */
  310. if (!rc)
  311. usleep_range(4000, 5000);
  312. }
  313. return rc;
  314. }
  315. void msm_dsi_host_init(struct mipi_panel_info *pinfo)
  316. {
  317. u32 dsi_ctrl, data;
  318. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  319. pr_debug("msm_dsi_host_init\n");
  320. pinfo->rgb_swap = DSI_RGB_SWAP_RGB;
  321. if (pinfo->mode == DSI_VIDEO_MODE) {
  322. data = 0;
  323. if (pinfo->pulse_mode_hsa_he)
  324. data |= BIT(28);
  325. if (pinfo->hfp_power_stop)
  326. data |= BIT(24);
  327. if (pinfo->hbp_power_stop)
  328. data |= BIT(20);
  329. if (pinfo->hsa_power_stop)
  330. data |= BIT(16);
  331. if (pinfo->eof_bllp_power_stop)
  332. data |= BIT(15);
  333. if (pinfo->bllp_power_stop)
  334. data |= BIT(12);
  335. data |= ((pinfo->traffic_mode & 0x03) << 8);
  336. data |= ((pinfo->dst_format & 0x03) << 4); /* 2 bits */
  337. data |= (pinfo->vc & 0x03);
  338. MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_CTRL, data);
  339. data = 0;
  340. data |= ((pinfo->rgb_swap & 0x07) << 12);
  341. if (pinfo->b_sel)
  342. data |= BIT(8);
  343. if (pinfo->g_sel)
  344. data |= BIT(4);
  345. if (pinfo->r_sel)
  346. data |= BIT(0);
  347. MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_DATA_CTRL, data);
  348. } else if (pinfo->mode == DSI_CMD_MODE) {
  349. data = 0;
  350. data |= ((pinfo->interleave_max & 0x0f) << 20);
  351. data |= ((pinfo->rgb_swap & 0x07) << 16);
  352. if (pinfo->b_sel)
  353. data |= BIT(12);
  354. if (pinfo->g_sel)
  355. data |= BIT(8);
  356. if (pinfo->r_sel)
  357. data |= BIT(4);
  358. data |= (pinfo->dst_format & 0x0f); /* 4 bits */
  359. MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_CTRL, data);
  360. /* DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL */
  361. data = pinfo->wr_mem_continue & 0x0ff;
  362. data <<= 8;
  363. data |= (pinfo->wr_mem_start & 0x0ff);
  364. if (pinfo->insert_dcs_cmd)
  365. data |= BIT(16);
  366. MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL,
  367. data);
  368. } else
  369. pr_err("%s: Unknown DSI mode=%d\n", __func__, pinfo->mode);
  370. dsi_ctrl = BIT(8) | BIT(2); /* clock enable & cmd mode */
  371. if (pinfo->crc_check)
  372. dsi_ctrl |= BIT(24);
  373. if (pinfo->ecc_check)
  374. dsi_ctrl |= BIT(20);
  375. if (pinfo->data_lane3)
  376. dsi_ctrl |= BIT(7);
  377. if (pinfo->data_lane2)
  378. dsi_ctrl |= BIT(6);
  379. if (pinfo->data_lane1)
  380. dsi_ctrl |= BIT(5);
  381. if (pinfo->data_lane0)
  382. dsi_ctrl |= BIT(4);
  383. /* from frame buffer, low power mode */
  384. /* DSI_COMMAND_MODE_DMA_CTRL */
  385. MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_DMA_CTRL, 0x14000000);
  386. data = 0;
  387. if (pinfo->te_sel)
  388. data |= BIT(31);
  389. data |= pinfo->mdp_trigger << 4;/* cmd mdp trigger */
  390. data |= pinfo->dma_trigger; /* cmd dma trigger */
  391. data |= (pinfo->stream & 0x01) << 8;
  392. MIPI_OUTP(ctrl_base + DSI_TRIG_CTRL, data);
  393. /* DSI_LAN_SWAP_CTRL */
  394. MIPI_OUTP(ctrl_base + DSI_LANE_SWAP_CTRL, pinfo->dlane_swap);
  395. /* clock out ctrl */
  396. data = pinfo->t_clk_post & 0x3f; /* 6 bits */
  397. data <<= 8;
  398. data |= pinfo->t_clk_pre & 0x3f; /* 6 bits */
  399. /* DSI_CLKOUT_TIMING_CTRL */
  400. MIPI_OUTP(ctrl_base + DSI_CLKOUT_TIMING_CTRL, data);
  401. data = 0;
  402. if (pinfo->rx_eot_ignore)
  403. data |= BIT(4);
  404. if (pinfo->tx_eot_append)
  405. data |= BIT(0);
  406. MIPI_OUTP(ctrl_base + DSI_EOT_PACKET_CTRL, data);
  407. /* allow only ack-err-status to generate interrupt */
  408. /* DSI_ERR_INT_MASK0 */
  409. MIPI_OUTP(ctrl_base + DSI_ERR_INT_MASK0, 0x13ff3fe0);
  410. /* turn esc, byte, dsi, pclk, sclk, hclk on */
  411. MIPI_OUTP(ctrl_base + DSI_CLK_CTRL, 0x23f);
  412. dsi_ctrl |= BIT(0); /* enable dsi */
  413. MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl);
  414. wmb();
  415. }
  416. void dsi_set_tx_power_mode(int mode)
  417. {
  418. u32 data;
  419. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  420. data = MIPI_INP(ctrl_base + DSI_COMMAND_MODE_DMA_CTRL);
  421. if (mode == 0)
  422. data &= ~BIT(26);
  423. else
  424. data |= BIT(26);
  425. MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_DMA_CTRL, data);
  426. }
  427. void msm_dsi_sw_reset(void)
  428. {
  429. u32 dsi_ctrl;
  430. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  431. pr_debug("msm_dsi_sw_reset\n");
  432. dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL);
  433. dsi_ctrl &= ~0x01;
  434. MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl);
  435. wmb();
  436. /* turn esc, byte, dsi, pclk, sclk, hclk on */
  437. MIPI_OUTP(ctrl_base + DSI_CLK_CTRL, 0x23f);
  438. wmb();
  439. MIPI_OUTP(ctrl_base + DSI_SOFT_RESET, 0x01);
  440. wmb();
  441. MIPI_OUTP(ctrl_base + DSI_SOFT_RESET, 0x00);
  442. wmb();
  443. }
  444. void msm_dsi_controller_cfg(int enable)
  445. {
  446. u32 dsi_ctrl, status;
  447. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  448. pr_debug("msm_dsi_controller_cfg\n");
  449. /* Check for CMD_MODE_DMA_BUSY */
  450. if (readl_poll_timeout((ctrl_base + DSI_STATUS),
  451. status,
  452. ((status & 0x02) == 0),
  453. DSI_POLL_SLEEP_US, DSI_POLL_TIMEOUT_US)) {
  454. pr_err("%s: DSI status=%x failed\n", __func__, status);
  455. pr_err("%s: Doing sw reset\n", __func__);
  456. msm_dsi_sw_reset();
  457. }
  458. /* Check for x_HS_FIFO_EMPTY */
  459. if (readl_poll_timeout((ctrl_base + DSI_FIFO_STATUS),
  460. status,
  461. ((status & 0x11111000) == 0x11111000),
  462. DSI_POLL_SLEEP_US, DSI_POLL_TIMEOUT_US))
  463. pr_err("%s: FIFO status=%x failed\n", __func__, status);
  464. /* Check for VIDEO_MODE_ENGINE_BUSY */
  465. if (readl_poll_timeout((ctrl_base + DSI_STATUS),
  466. status,
  467. ((status & 0x08) == 0),
  468. DSI_POLL_SLEEP_US, DSI_POLL_TIMEOUT_US)) {
  469. pr_err("%s: DSI status=%x\n", __func__, status);
  470. pr_err("%s: Doing sw reset\n", __func__);
  471. msm_dsi_sw_reset();
  472. }
  473. dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL);
  474. if (enable)
  475. dsi_ctrl |= 0x01;
  476. else
  477. dsi_ctrl &= ~0x01;
  478. MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl);
  479. wmb();
  480. }
  481. void msm_dsi_op_mode_config(int mode, struct mdss_panel_data *pdata)
  482. {
  483. u32 dsi_ctrl;
  484. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  485. pr_debug("msm_dsi_op_mode_config\n");
  486. dsi_ctrl = MIPI_INP(ctrl_base + DSI_CTRL);
  487. if (dsi_ctrl & DSI_VIDEO_MODE_EN)
  488. dsi_ctrl &= ~(DSI_CMD_MODE_EN|DSI_EN);
  489. else
  490. dsi_ctrl &= ~(DSI_CMD_MODE_EN|DSI_VIDEO_MODE_EN|DSI_EN);
  491. if (mode == DSI_VIDEO_MODE) {
  492. dsi_ctrl |= (DSI_VIDEO_MODE_EN|DSI_EN);
  493. } else { /* command mode */
  494. dsi_ctrl |= (DSI_CMD_MODE_EN|DSI_EN);
  495. /*For Video mode panel, keep Video and Cmd mode ON */
  496. if (pdata->panel_info.type == MIPI_VIDEO_PANEL)
  497. dsi_ctrl |= DSI_VIDEO_MODE_EN;
  498. }
  499. pr_debug("%s: dsi_ctrl=%x\n", __func__, dsi_ctrl);
  500. MIPI_OUTP(ctrl_base + DSI_CTRL, dsi_ctrl);
  501. wmb();
  502. }
  503. int msm_dsi_cmd_dma_tx(struct mdss_dsi_ctrl_pdata *ctrl,
  504. struct dsi_buf *tp)
  505. {
  506. int len, rc;
  507. unsigned long size, addr;
  508. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  509. unsigned long flag;
  510. #if defined(CONFIG_DSI_HOST_DEBUG)
  511. int i = 0;
  512. char *bp;
  513. bp = tp->data;
  514. printk("%s: ", __func__);
  515. for (i = 0; i < tp->len; i++)
  516. printk("%02X ", *bp++);
  517. printk("\n");
  518. #endif
  519. len = ALIGN(tp->len, 4);
  520. size = ALIGN(tp->len, SZ_4K);
  521. tp->dmap = dma_map_single(&dsi_host_private->dis_dev, tp->data, size,
  522. DMA_TO_DEVICE);
  523. if (dma_mapping_error(&dsi_host_private->dis_dev, tp->dmap)) {
  524. pr_err("%s: dmap mapp failed\n", __func__);
  525. return -ENOMEM;
  526. }
  527. addr = tp->dmap;
  528. msm_dsi_get_cmd_engine(ctrl);
  529. spin_lock_irqsave(&ctrl->mdp_lock, flag);
  530. INIT_COMPLETION(ctrl->dma_comp);
  531. msm_dsi_set_irq(ctrl, DSI_INTR_CMD_DMA_DONE_MASK);
  532. spin_unlock_irqrestore(&ctrl->mdp_lock, flag);
  533. MIPI_OUTP(ctrl_base + DSI_DMA_CMD_OFFSET, addr);
  534. MIPI_OUTP(ctrl_base + DSI_DMA_CMD_LENGTH, len);
  535. wmb();
  536. MIPI_OUTP(ctrl_base + DSI_CMD_MODE_DMA_SW_TRIGGER, 0x01);
  537. wmb();
  538. rc = wait_for_completion_timeout(&ctrl->dma_comp,
  539. msecs_to_jiffies(DSI_DMA_CMD_TIMEOUT_MS));
  540. if (rc == 0) {
  541. #if defined(CONFIG_FB_MSM_MDSS_DSI_DBG)
  542. dumpreg();
  543. mdp3_dump_clk();
  544. #endif
  545. pr_err("DSI command transaction time out\n");
  546. rc = -ETIME;
  547. } else if (!IS_ERR_VALUE(rc)) {
  548. rc = 0;
  549. }
  550. dma_unmap_single(&dsi_host_private->dis_dev, tp->dmap, size,
  551. DMA_TO_DEVICE);
  552. tp->dmap = 0;
  553. msm_dsi_clear_irq(ctrl, DSI_INTR_CMD_DMA_DONE_MASK);
  554. msm_dsi_release_cmd_engine(ctrl);
  555. return rc;
  556. }
  557. /* MIPI_DSI_MRPS, Maximum Return Packet Size */
  558. static char max_pktsize[2] = {0x00, 0x00}; /* LSB tx first, 10 bytes */
  559. static struct dsi_cmd_desc pkt_size_cmd = {
  560. {DTYPE_MAX_PKTSIZE, 1, 0, 0, 0, sizeof(max_pktsize)},
  561. max_pktsize,
  562. };
  563. int msm_dsi_cmd_dma_rx(struct mdss_dsi_ctrl_pdata *ctrl,
  564. struct dsi_buf *rp, int rlen)
  565. {
  566. u32 *lp, data, *temp;
  567. int i, j = 0, off, cnt;
  568. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  569. char reg[16];
  570. int repeated_bytes = 0;
  571. lp = (u32 *)rp->data;
  572. temp = (u32 *)reg;
  573. cnt = rlen;
  574. cnt += 3;
  575. cnt >>= 2;
  576. if (cnt > 4)
  577. cnt = 4; /* 4 x 32 bits registers only */
  578. if (rlen == 4)
  579. rp->read_cnt = 4;
  580. else
  581. rp->read_cnt = (max_pktsize[0] + 6);
  582. if (rp->read_cnt > 16) {
  583. int bytes_shifted, data_lost = 0, rem_header_bytes = 0;
  584. /* Any data more than 16 bytes will be shifted out */
  585. bytes_shifted = rp->read_cnt - rlen;
  586. if (bytes_shifted >= 4)
  587. data_lost = bytes_shifted - 4; /* remove dcs header */
  588. else
  589. rem_header_bytes = 4 - bytes_shifted; /* rem header */
  590. /*
  591. * (rp->len - 4) -> current rx buffer data length.
  592. * If data_lost > 0, then ((rp->len - 4) - data_lost) will be
  593. * the number of repeating bytes.
  594. * If data_lost == 0, then ((rp->len - 4) + rem_header_bytes)
  595. * will be the number of bytes repeating in between rx buffer
  596. * and the current RDBK_DATA registers. We need to skip the
  597. * repeating bytes.
  598. */
  599. repeated_bytes = (rp->len - 4) - data_lost + rem_header_bytes;
  600. }
  601. off = DSI_RDBK_DATA0;
  602. off += ((cnt - 1) * 4);
  603. for (i = 0; i < cnt; i++) {
  604. data = (u32)MIPI_INP(ctrl_base + off);
  605. /* to network byte order */
  606. if (!repeated_bytes)
  607. *lp++ = ntohl(data);
  608. else
  609. *temp++ = ntohl(data);
  610. pr_debug("%s: data = 0x%x and ntohl(data) = 0x%x\n",
  611. __func__, data, ntohl(data));
  612. off -= 4;
  613. if (rlen == 4)
  614. rp->len += sizeof(*lp);
  615. }
  616. /* Skip duplicates and append other data to the rx buffer */
  617. if (repeated_bytes) {
  618. for (i = repeated_bytes; i < 16; i++)
  619. rp->data[j++] = reg[i];
  620. }
  621. return rlen;
  622. }
  623. static int msm_dsi_cmds_tx(struct mdss_dsi_ctrl_pdata *ctrl,
  624. struct dsi_cmd_desc *cmds, int cnt)
  625. {
  626. struct dsi_buf *tp;
  627. struct dsi_cmd_desc *cm;
  628. struct dsi_ctrl_hdr *dchdr;
  629. int len;
  630. int rc = 0;
  631. tp = &ctrl->tx_buf;
  632. mdss_dsi_buf_init(tp);
  633. cm = cmds;
  634. len = 0;
  635. while (cnt--) {
  636. dchdr = &cm->dchdr;
  637. mdss_dsi_buf_reserve(tp, len);
  638. len = mdss_dsi_cmd_dma_add(tp, cm);
  639. if (!len) {
  640. pr_err("%s: failed to add cmd = 0x%x\n",
  641. __func__, cm->payload[0]);
  642. rc = -EINVAL;
  643. goto dsi_cmds_tx_err;
  644. }
  645. if (dchdr->last) {
  646. tp->data = tp->start; /* begin of buf */
  647. rc = msm_dsi_wait4video_eng_busy(ctrl);
  648. if (rc) {
  649. pr_err("%s: wait4video_eng failed\n", __func__);
  650. goto dsi_cmds_tx_err;
  651. }
  652. rc = msm_dsi_cmd_dma_tx(ctrl, tp);
  653. if (IS_ERR_VALUE(len)) {
  654. pr_err("%s: failed to call cmd_dma_tx for cmd = 0x%x\n",
  655. __func__, cmds->payload[0]);
  656. goto dsi_cmds_tx_err;
  657. }
  658. if (dchdr->wait)
  659. usleep(dchdr->wait * 1000);
  660. mdss_dsi_buf_init(tp);
  661. len = 0;
  662. }
  663. cm++;
  664. }
  665. dsi_cmds_tx_err:
  666. return rc;
  667. }
  668. static int msm_dsi_parse_rx_response(struct dsi_buf *rp)
  669. {
  670. int rc = 0;
  671. unsigned char cmd;
  672. cmd = rp->data[0];
  673. switch (cmd) {
  674. case DTYPE_ACK_ERR_RESP:
  675. pr_debug("%s: rx ACK_ERR_PACLAGE\n", __func__);
  676. rc = -EINVAL;
  677. break;
  678. case DTYPE_GEN_READ1_RESP:
  679. case DTYPE_DCS_READ1_RESP:
  680. mdss_dsi_short_read1_resp(rp);
  681. break;
  682. case DTYPE_GEN_READ2_RESP:
  683. case DTYPE_DCS_READ2_RESP:
  684. mdss_dsi_short_read2_resp(rp);
  685. break;
  686. case DTYPE_GEN_LREAD_RESP:
  687. case DTYPE_DCS_LREAD_RESP:
  688. mdss_dsi_long_read_resp(rp);
  689. break;
  690. default:
  691. rc = -EINVAL;
  692. pr_warn("%s: Unknown cmd received\n", __func__);
  693. break;
  694. }
  695. return rc;
  696. }
  697. static int msm_dsi_set_max_packet_size(struct mdss_dsi_ctrl_pdata *ctrl,
  698. int size)
  699. {
  700. struct dsi_buf *tp;
  701. int rc;
  702. tp = &ctrl->tx_buf;
  703. mdss_dsi_buf_init(tp);
  704. max_pktsize[0] = size;
  705. rc = mdss_dsi_cmd_dma_add(tp, &pkt_size_cmd);
  706. if (!rc) {
  707. pr_err("%s: failed to add max_pkt_size\n", __func__);
  708. return -EINVAL;
  709. }
  710. rc = msm_dsi_wait4video_eng_busy(ctrl);
  711. if (rc) {
  712. pr_err("%s: failed to wait4video_eng\n", __func__);
  713. return rc;
  714. }
  715. rc = msm_dsi_cmd_dma_tx(ctrl, tp);
  716. if (IS_ERR_VALUE(rc)) {
  717. pr_err("%s: failed to tx max_pkt_size\n", __func__);
  718. return rc;
  719. }
  720. pr_debug("%s: max_pkt_size=%d sent\n", __func__, size);
  721. return rc;
  722. }
  723. /* read data length is less than or equal to 10 bytes*/
  724. static int msm_dsi_cmds_rx_1(struct mdss_dsi_ctrl_pdata *ctrl,
  725. struct dsi_cmd_desc *cmds, int rlen)
  726. {
  727. int rc;
  728. struct dsi_buf *tp, *rp;
  729. int rx_byte = 0;
  730. if (rlen <= 2)
  731. rx_byte = 4;
  732. else
  733. rx_byte = DSI_MAX_BYTES_TO_READ;
  734. tp = &ctrl->tx_buf;
  735. rp = &ctrl->rx_buf;
  736. mdss_dsi_buf_init(rp);
  737. rc = msm_dsi_set_max_packet_size(ctrl, rlen);
  738. if (rc) {
  739. pr_err("%s: dsi_set_max_pkt failed\n", __func__);
  740. rc = -EINVAL;
  741. goto dsi_cmds_rx_1_error;
  742. }
  743. mdss_dsi_buf_init(tp);
  744. rc = mdss_dsi_cmd_dma_add(tp, cmds);
  745. if (!rc) {
  746. pr_err("%s: dsi_cmd_dma_add failed\n", __func__);
  747. rc = -EINVAL;
  748. goto dsi_cmds_rx_1_error;
  749. }
  750. rc = msm_dsi_wait4video_eng_busy(ctrl);
  751. if (rc) {
  752. pr_err("%s: wait4video_eng failed\n", __func__);
  753. goto dsi_cmds_rx_1_error;
  754. }
  755. rc = msm_dsi_cmd_dma_tx(ctrl, tp);
  756. if (IS_ERR_VALUE(rc)) {
  757. pr_err("%s: msm_dsi_cmd_dma_tx failed\n", __func__);
  758. goto dsi_cmds_rx_1_error;
  759. }
  760. if (rlen <= DSI_SHORT_PKT_DATA_SIZE) {
  761. msm_dsi_cmd_dma_rx(ctrl, rp, rx_byte);
  762. } else {
  763. msm_dsi_cmd_dma_rx(ctrl, rp, rx_byte);
  764. rp->len = rx_byte - 2; /*2 bytes for CRC*/
  765. rp->len = rp->len - (DSI_MAX_PKT_SIZE - rlen);
  766. rp->data = rp->start + (16 - (rlen + 2 + DSI_HOST_HDR_SIZE));
  767. }
  768. rc = msm_dsi_parse_rx_response(rp);
  769. dsi_cmds_rx_1_error:
  770. if (rc)
  771. rp->len = 0;
  772. return rc;
  773. }
  774. /* read data length is more than 10 bytes, which requires multiple DSI read*/
  775. static int msm_dsi_cmds_rx_2(struct mdss_dsi_ctrl_pdata *ctrl,
  776. struct dsi_cmd_desc *cmds, int rlen)
  777. {
  778. int rc;
  779. struct dsi_buf *tp, *rp;
  780. int pkt_size, data_bytes, dlen, end = 0, diff;
  781. tp = &ctrl->tx_buf;
  782. rp = &ctrl->rx_buf;
  783. mdss_dsi_buf_init(rp);
  784. pkt_size = DSI_MAX_PKT_SIZE;
  785. data_bytes = MDSS_DSI_LEN;
  786. while (!end) {
  787. rc = msm_dsi_set_max_packet_size(ctrl, pkt_size);
  788. if (rc)
  789. break;
  790. mdss_dsi_buf_init(tp);
  791. rc = mdss_dsi_cmd_dma_add(tp, cmds);
  792. if (!rc) {
  793. pr_err("%s: dsi_cmd_dma_add failed\n", __func__);
  794. rc = -EINVAL;
  795. break;
  796. }
  797. rc = msm_dsi_wait4video_eng_busy(ctrl);
  798. if (rc) {
  799. pr_err("%s: wait4video_eng failed\n", __func__);
  800. break;
  801. }
  802. rc = msm_dsi_cmd_dma_tx(ctrl, tp);
  803. if (IS_ERR_VALUE(rc)) {
  804. pr_err("%s: msm_dsi_cmd_dma_tx failed\n", __func__);
  805. break;
  806. }
  807. msm_dsi_cmd_dma_rx(ctrl, rp, DSI_MAX_BYTES_TO_READ);
  808. if (rlen <= data_bytes) {
  809. diff = data_bytes - rlen;
  810. end = 1;
  811. } else {
  812. diff = 0;
  813. rlen -= data_bytes;
  814. }
  815. dlen = DSI_MAX_BYTES_TO_READ - 2;
  816. dlen -= diff;
  817. rp->data += dlen;
  818. rp->len += dlen;
  819. if (!end) {
  820. data_bytes = 14;
  821. if (rlen < data_bytes)
  822. pkt_size += rlen;
  823. else
  824. pkt_size += data_bytes;
  825. }
  826. pr_debug("%s: rp data=%x len=%d dlen=%d diff=%d\n",
  827. __func__, (int) (unsigned long) rp->data,
  828. rp->len, dlen, diff);
  829. }
  830. if (!rc) {
  831. rp->data = rp->start;
  832. rc = msm_dsi_parse_rx_response(rp);
  833. }
  834. if (rc)
  835. rp->len = 0;
  836. return rc;
  837. }
  838. int msm_dsi_cmds_rx(struct mdss_dsi_ctrl_pdata *ctrl,
  839. struct dsi_cmd_desc *cmds, int rlen)
  840. {
  841. int rc;
  842. if (rlen <= DSI_MAX_PKT_SIZE)
  843. rc = msm_dsi_cmds_rx_1(ctrl, cmds, rlen);
  844. else
  845. rc = msm_dsi_cmds_rx_2(ctrl, cmds, rlen);
  846. return rc;
  847. }
  848. void msm_dsi_cmdlist_tx(struct mdss_dsi_ctrl_pdata *ctrl,
  849. struct dcs_cmd_req *req)
  850. {
  851. int ret;
  852. ret = msm_dsi_cmds_tx(ctrl, req->cmds, req->cmds_cnt);
  853. if (req->cb)
  854. req->cb(ret);
  855. }
  856. void msm_dsi_cmdlist_rx(struct mdss_dsi_ctrl_pdata *ctrl,
  857. struct dcs_cmd_req *req)
  858. {
  859. struct dsi_buf *rp;
  860. int len = 0;
  861. if (req->rbuf) {
  862. rp = &ctrl->rx_buf;
  863. len = msm_dsi_cmds_rx(ctrl, req->cmds, req->rlen);
  864. memcpy(req->rbuf, rp->data, rp->len);
  865. } else {
  866. pr_err("%s: No rx buffer provided\n", __func__);
  867. }
  868. if (req->cb)
  869. req->cb(len);
  870. }
  871. int msm_dsi_cmdlist_commit(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp)
  872. {
  873. struct dcs_cmd_req *req;
  874. int dsi_on;
  875. int ret = -EINVAL;
  876. mutex_lock(&ctrl->mutex);
  877. dsi_on = dsi_host_private->dsi_on;
  878. mutex_unlock(&ctrl->mutex);
  879. if (!dsi_on) {
  880. pr_err("try to send DSI commands while dsi is off\n");
  881. return ret;
  882. }
  883. mutex_lock(&ctrl->cmd_mutex);
  884. req = mdss_dsi_cmdlist_get(ctrl);
  885. if (!req) {
  886. mutex_unlock(&ctrl->cmd_mutex);
  887. return ret;
  888. }
  889. /*
  890. * mdss interrupt is generated in mdp core clock domain
  891. * mdp clock need to be enabled to receive dsi interrupt
  892. * also, axi bus bandwidth need since dsi controller will
  893. * fetch dcs commands from axi bus
  894. */
  895. mdp3_res_update(1, 1, MDP3_CLIENT_DMA_P);
  896. msm_dsi_clk_ctrl(&ctrl->panel_data, 1);
  897. if (0 == (req->flags & CMD_REQ_LP_MODE))
  898. dsi_set_tx_power_mode(0);
  899. if (req->flags & CMD_REQ_RX)
  900. msm_dsi_cmdlist_rx(ctrl, req);
  901. else
  902. msm_dsi_cmdlist_tx(ctrl, req);
  903. if (0 == (req->flags & CMD_REQ_LP_MODE))
  904. dsi_set_tx_power_mode(1);
  905. msm_dsi_clk_ctrl(&ctrl->panel_data, 0);
  906. mdp3_res_update(0, 1, MDP3_CLIENT_DMA_P);
  907. mutex_unlock(&ctrl->cmd_mutex);
  908. return 0;
  909. }
  910. static int msm_dsi_cal_clk_rate(struct mdss_panel_data *pdata,
  911. u32 *bitclk_rate,
  912. u32 *dsiclk_rate,
  913. u32 *byteclk_rate,
  914. u32 *pclk_rate)
  915. {
  916. struct mdss_panel_info *pinfo;
  917. struct mipi_panel_info *mipi;
  918. u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
  919. int lanes;
  920. pinfo = &pdata->panel_info;
  921. mipi = &pdata->panel_info.mipi;
  922. hbp = pdata->panel_info.lcdc.h_back_porch;
  923. hfp = pdata->panel_info.lcdc.h_front_porch;
  924. vbp = pdata->panel_info.lcdc.v_back_porch;
  925. vfp = pdata->panel_info.lcdc.v_front_porch;
  926. hspw = pdata->panel_info.lcdc.h_pulse_width;
  927. vspw = pdata->panel_info.lcdc.v_pulse_width;
  928. width = pdata->panel_info.xres;
  929. height = pdata->panel_info.yres;
  930. lanes = 0;
  931. if (mipi->data_lane0)
  932. lanes++;
  933. if (mipi->data_lane1)
  934. lanes++;
  935. if (mipi->data_lane2)
  936. lanes++;
  937. if (mipi->data_lane3)
  938. lanes++;
  939. if (lanes == 0)
  940. return -EINVAL;
  941. *bitclk_rate = (width + hbp + hfp + hspw) * (height + vbp + vfp + vspw);
  942. *bitclk_rate *= mipi->frame_rate;
  943. *bitclk_rate *= pdata->panel_info.bpp;
  944. *bitclk_rate /= lanes;
  945. *byteclk_rate = *bitclk_rate / 8;
  946. *dsiclk_rate = *byteclk_rate * lanes;
  947. *pclk_rate = *byteclk_rate * lanes * 8 / pdata->panel_info.bpp;
  948. pr_debug("dsiclk_rate=%u, byteclk=%u, pck_=%u\n",
  949. *dsiclk_rate, *byteclk_rate, *pclk_rate);
  950. return 0;
  951. }
  952. static int msm_dsi_on(struct mdss_panel_data *pdata)
  953. {
  954. int ret = 0;
  955. u32 clk_rate;
  956. struct mdss_panel_info *pinfo;
  957. struct mipi_panel_info *mipi;
  958. u32 hbp, hfp, vbp, vfp, hspw, vspw, width, height;
  959. u32 ystride, bpp, data;
  960. u32 dummy_xres, dummy_yres;
  961. u32 bitclk_rate = 0, byteclk_rate = 0, pclk_rate = 0, dsiclk_rate = 0;
  962. unsigned char *ctrl_base = dsi_host_private->dsi_base;
  963. struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
  964. pr_debug("msm_dsi_on\n");
  965. pinfo = &pdata->panel_info;
  966. ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
  967. panel_data);
  968. mutex_lock(&ctrl_pdata->mutex);
  969. if (!pdata->panel_info.dynamic_switch_pending) {
  970. ret = msm_dss_enable_vreg(
  971. ctrl_pdata->power_data.vreg_config,
  972. ctrl_pdata->power_data.num_vreg, 1);
  973. if (ret) {
  974. pr_err("%s: DSI power on failed\n", __func__);
  975. mutex_unlock(&ctrl_pdata->mutex);
  976. return ret;
  977. }
  978. }
  979. msm_dsi_ahb_ctrl(1);
  980. msm_dsi_phy_sw_reset(dsi_host_private->dsi_base);
  981. msm_dsi_phy_init(dsi_host_private->dsi_base, pdata);
  982. msm_dsi_cal_clk_rate(pdata, &bitclk_rate, &dsiclk_rate,
  983. &byteclk_rate, &pclk_rate);
  984. msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, dsiclk_rate,
  985. byteclk_rate, pclk_rate);
  986. msm_dsi_prepare_clocks();
  987. msm_dsi_clk_enable();
  988. clk_rate = pdata->panel_info.clk_rate;
  989. clk_rate = min(clk_rate, pdata->panel_info.clk_max);
  990. hbp = pdata->panel_info.lcdc.h_back_porch;
  991. hfp = pdata->panel_info.lcdc.h_front_porch;
  992. vbp = pdata->panel_info.lcdc.v_back_porch;
  993. vfp = pdata->panel_info.lcdc.v_front_porch;
  994. hspw = pdata->panel_info.lcdc.h_pulse_width;
  995. vspw = pdata->panel_info.lcdc.v_pulse_width;
  996. width = pdata->panel_info.xres;
  997. height = pdata->panel_info.yres;
  998. mipi = &pdata->panel_info.mipi;
  999. if (pdata->panel_info.type == MIPI_VIDEO_PANEL) {
  1000. dummy_xres = pdata->panel_info.lcdc.xres_pad;
  1001. dummy_yres = pdata->panel_info.lcdc.yres_pad;
  1002. MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_ACTIVE_H,
  1003. ((hspw + hbp + width + dummy_xres) << 16 |
  1004. (hspw + hbp)));
  1005. MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_ACTIVE_V,
  1006. ((vspw + vbp + height + dummy_yres) << 16 |
  1007. (vspw + vbp)));
  1008. MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_TOTAL,
  1009. (vspw + vbp + height + dummy_yres +
  1010. vfp - 1) << 16 | (hspw + hbp +
  1011. width + dummy_xres + hfp - 1));
  1012. MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_HSYNC, (hspw << 16));
  1013. MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_VSYNC, 0);
  1014. MIPI_OUTP(ctrl_base + DSI_VIDEO_MODE_VSYNC_VPOS,
  1015. (vspw << 16));
  1016. } else { /* command mode */
  1017. if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)
  1018. bpp = 3;
  1019. else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB666)
  1020. bpp = 3;
  1021. else if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB565)
  1022. bpp = 2;
  1023. else
  1024. bpp = 3; /* Default format set to RGB888 */
  1025. ystride = width * bpp + 1;
  1026. data = (ystride << 16) | (mipi->vc << 8) | DTYPE_DCS_LWRITE;
  1027. MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_STREAM0_CTRL,
  1028. data);
  1029. MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_STREAM1_CTRL,
  1030. data);
  1031. data = height << 16 | width;
  1032. MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_STREAM1_TOTAL,
  1033. data);
  1034. MIPI_OUTP(ctrl_base + DSI_COMMAND_MODE_MDP_STREAM0_TOTAL,
  1035. data);
  1036. }
  1037. msm_dsi_sw_reset();
  1038. msm_dsi_host_init(mipi);
  1039. if (mipi->force_clk_lane_hs) {
  1040. u32 tmp;
  1041. tmp = MIPI_INP(ctrl_base + DSI_LANE_CTRL);
  1042. tmp |= (1<<28);
  1043. MIPI_OUTP(ctrl_base + DSI_LANE_CTRL, tmp);
  1044. wmb();
  1045. }
  1046. msm_dsi_op_mode_config(mipi->mode, pdata);
  1047. msm_dsi_set_irq(ctrl_pdata, DSI_INTR_ERROR_MASK);
  1048. dsi_host_private->clk_count = 1;
  1049. dsi_host_private->dsi_on = 1;
  1050. #if defined(CONFIG_FB_MSM_MDSS_DSI_DBG)
  1051. dsi_ctrl_on = dsi_host_private->dsi_on;
  1052. #endif
  1053. mutex_unlock(&ctrl_pdata->mutex);
  1054. return ret;
  1055. }
  1056. static int msm_dsi_off(struct mdss_panel_data *pdata)
  1057. {
  1058. int ret = 0;
  1059. struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
  1060. if (pdata == NULL) {
  1061. pr_err("%s: Invalid input data\n", __func__);
  1062. ret = -EINVAL;
  1063. return ret;
  1064. }
  1065. ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
  1066. panel_data);
  1067. pr_debug("msm_dsi_off\n");
  1068. mutex_lock(&ctrl_pdata->mutex);
  1069. msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask);
  1070. msm_dsi_controller_cfg(0);
  1071. msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, 0, 0, 0);
  1072. msm_dsi_clk_disable();
  1073. msm_dsi_unprepare_clocks();
  1074. msm_dsi_phy_off(dsi_host_private->dsi_base);
  1075. msm_dsi_ahb_ctrl(0);
  1076. if (!pdata->panel_info.dynamic_switch_pending) {
  1077. ret = msm_dss_enable_vreg(
  1078. ctrl_pdata->power_data.vreg_config,
  1079. ctrl_pdata->power_data.num_vreg, 0);
  1080. if (ret) {
  1081. pr_err("%s: Panel power off failed\n", __func__);
  1082. }
  1083. }
  1084. dsi_host_private->clk_count = 0;
  1085. dsi_host_private->dsi_on = 0;
  1086. #if defined(CONFIG_FB_MSM_MDSS_DSI_DBG)
  1087. dsi_ctrl_on = dsi_host_private->dsi_on;
  1088. #endif
  1089. mutex_unlock(&ctrl_pdata->mutex);
  1090. return ret;
  1091. }
  1092. static int msm_dsi_cont_on(struct mdss_panel_data *pdata)
  1093. {
  1094. struct mdss_panel_info *pinfo;
  1095. int ret = 0;
  1096. struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
  1097. if (pdata == NULL) {
  1098. pr_err("%s: Invalid input data\n", __func__);
  1099. ret = -EINVAL;
  1100. return ret;
  1101. }
  1102. pr_debug("%s:\n", __func__);
  1103. ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
  1104. panel_data);
  1105. pinfo = &pdata->panel_info;
  1106. mutex_lock(&ctrl_pdata->mutex);
  1107. ret = msm_dss_enable_vreg(
  1108. ctrl_pdata->power_data.vreg_config,
  1109. ctrl_pdata->power_data.num_vreg, 1);
  1110. if (ret) {
  1111. pr_err("%s: DSI power on failed\n", __func__);
  1112. mutex_unlock(&ctrl_pdata->mutex);
  1113. return ret;
  1114. }
  1115. pinfo->panel_power_on = 1;
  1116. ret = mdss_dsi_panel_reset(pdata, 1);
  1117. if (ret) {
  1118. pr_err("%s: Panel reset failed\n", __func__);
  1119. mutex_unlock(&ctrl_pdata->mutex);
  1120. return ret;
  1121. }
  1122. msm_dsi_ahb_ctrl(1);
  1123. msm_dsi_prepare_clocks();
  1124. msm_dsi_clk_enable();
  1125. msm_dsi_set_irq(ctrl_pdata, DSI_INTR_ERROR_MASK);
  1126. dsi_host_private->clk_count = 1;
  1127. dsi_host_private->dsi_on = 1;
  1128. #if defined(CONFIG_FB_MSM_MDSS_DSI_DBG)
  1129. dsi_ctrl_on = dsi_host_private->dsi_on;
  1130. #endif
  1131. mutex_unlock(&ctrl_pdata->mutex);
  1132. return 0;
  1133. }
  1134. static int msm_dsi_read_status(struct mdss_dsi_ctrl_pdata *ctrl)
  1135. {
  1136. struct dcs_cmd_req cmdreq;
  1137. memset(&cmdreq, 0, sizeof(cmdreq));
  1138. cmdreq.cmds = ctrl->status_cmds.cmds;
  1139. cmdreq.cmds_cnt = ctrl->status_cmds.cmd_cnt;
  1140. cmdreq.flags = CMD_REQ_COMMIT | CMD_CLK_CTRL | CMD_REQ_RX;
  1141. cmdreq.rlen = 1;
  1142. cmdreq.cb = NULL;
  1143. cmdreq.rbuf = ctrl->status_buf.data;
  1144. return mdss_dsi_cmdlist_put(ctrl, &cmdreq);
  1145. }
  1146. /**
  1147. * msm_dsi_reg_status_check() - Check dsi panel status through reg read
  1148. * @ctrl_pdata: pointer to the dsi controller structure
  1149. *
  1150. * This function can be used to check the panel status through reading the
  1151. * status register from the panel.
  1152. *
  1153. * Return: positive value if the panel is in good state, negative value or
  1154. * zero otherwise.
  1155. */
  1156. int msm_dsi_reg_status_check(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
  1157. {
  1158. int ret = 0;
  1159. if (ctrl_pdata == NULL) {
  1160. pr_err("%s: Invalid input data\n", __func__);
  1161. return 0;
  1162. }
  1163. pr_debug("%s: Checking Register status\n", __func__);
  1164. msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 1);
  1165. if (ctrl_pdata->status_cmds.link_state == DSI_HS_MODE)
  1166. dsi_set_tx_power_mode(0);
  1167. ret = msm_dsi_read_status(ctrl_pdata);
  1168. if (ctrl_pdata->status_cmds.link_state == DSI_HS_MODE)
  1169. dsi_set_tx_power_mode(1);
  1170. if (ret == 0) {
  1171. if (ctrl_pdata->status_buf.data[0] !=
  1172. ctrl_pdata->status_value) {
  1173. pr_err("%s: Read back value from panel is incorrect\n",
  1174. __func__);
  1175. ret = -EINVAL;
  1176. } else {
  1177. ret = 1;
  1178. }
  1179. } else {
  1180. pr_err("%s: Read status register returned error\n", __func__);
  1181. }
  1182. msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 0);
  1183. pr_debug("%s: Read register done with ret: %d\n", __func__, ret);
  1184. return ret;
  1185. }
  1186. /**
  1187. * msm_dsi_bta_status_check() - Check dsi panel status through bta check
  1188. * @ctrl_pdata: pointer to the dsi controller structure
  1189. *
  1190. * This function can be used to check status of the panel using bta check
  1191. * for the panel.
  1192. *
  1193. * Return: positive value if the panel is in good state, negative value or
  1194. * zero otherwise.
  1195. */
  1196. static int msm_dsi_bta_status_check(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
  1197. {
  1198. int ret = 0;
  1199. if (ctrl_pdata == NULL) {
  1200. pr_err("%s: Invalid input data\n", __func__);
  1201. return 0;
  1202. }
  1203. mutex_lock(&ctrl_pdata->cmd_mutex);
  1204. msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 1);
  1205. msm_dsi_cmd_mdp_busy(ctrl_pdata);
  1206. msm_dsi_set_irq(ctrl_pdata, DSI_INTR_BTA_DONE_MASK);
  1207. INIT_COMPLETION(ctrl_pdata->bta_comp);
  1208. /* BTA trigger */
  1209. MIPI_OUTP(dsi_host_private->dsi_base + DSI_CMD_MODE_BTA_SW_TRIGGER,
  1210. 0x01);
  1211. wmb();
  1212. ret = wait_for_completion_killable_timeout(&ctrl_pdata->bta_comp,
  1213. HZ/10);
  1214. msm_dsi_clear_irq(ctrl_pdata, DSI_INTR_BTA_DONE_MASK);
  1215. msm_dsi_clk_ctrl(&ctrl_pdata->panel_data, 0);
  1216. mutex_unlock(&ctrl_pdata->cmd_mutex);
  1217. if (ret <= 0)
  1218. pr_err("%s: DSI BTA error: %i\n", __func__, __LINE__);
  1219. pr_debug("%s: BTA done with ret: %d\n", __func__, ret);
  1220. return ret;
  1221. }
  1222. static void msm_dsi_debug_enable_clock(int on)
  1223. {
  1224. if (dsi_host_private->debug_enable_clk)
  1225. dsi_host_private->debug_enable_clk(on);
  1226. if (on)
  1227. msm_dsi_ahb_ctrl(1);
  1228. else
  1229. msm_dsi_ahb_ctrl(0);
  1230. }
  1231. static int msm_dsi_debug_init(void)
  1232. {
  1233. int rc;
  1234. if (!mdss_res)
  1235. return 0;
  1236. dsi_host_private->debug_enable_clk =
  1237. mdss_res->debug_inf.debug_enable_clock;
  1238. mdss_res->debug_inf.debug_enable_clock = msm_dsi_debug_enable_clock;
  1239. rc = mdss_debug_register_base("dsi0",
  1240. dsi_host_private->dsi_base,
  1241. dsi_host_private->dsi_reg_size);
  1242. return rc;
  1243. }
  1244. static int dsi_get_panel_cfg(char *panel_cfg)
  1245. {
  1246. int rc;
  1247. struct mdss_panel_cfg *pan_cfg = NULL;
  1248. if (!panel_cfg)
  1249. return MDSS_PANEL_INTF_INVALID;
  1250. pan_cfg = mdp3_panel_intf_type(MDSS_PANEL_INTF_DSI);
  1251. if (IS_ERR(pan_cfg)) {
  1252. panel_cfg[0] = 0;
  1253. return PTR_ERR(pan_cfg);
  1254. } else if (!pan_cfg) {
  1255. panel_cfg[0] = 0;
  1256. return 0;
  1257. }
  1258. pr_debug("%s:%d: cfg:[%s]\n", __func__, __LINE__,
  1259. pan_cfg->arg_cfg);
  1260. rc = strlcpy(panel_cfg, pan_cfg->arg_cfg,
  1261. MDSS_MAX_PANEL_LEN);
  1262. return rc;
  1263. }
  1264. static struct device_node *dsi_pref_prim_panel(
  1265. struct platform_device *pdev)
  1266. {
  1267. struct device_node *dsi_pan_node = NULL;
  1268. pr_debug("%s:%d: Select primary panel from dt\n",
  1269. __func__, __LINE__);
  1270. dsi_pan_node = of_parse_phandle(pdev->dev.of_node,
  1271. "qcom,dsi-pref-prim-pan", 0);
  1272. if (!dsi_pan_node)
  1273. pr_err("%s:can't find panel phandle\n", __func__);
  1274. return dsi_pan_node;
  1275. }
  1276. /**
  1277. * dsi_find_panel_of_node(): find device node of dsi panel
  1278. * @pdev: platform_device of the dsi ctrl node
  1279. * @panel_cfg: string containing intf specific config data
  1280. *
  1281. * Function finds the panel device node using the interface
  1282. * specific configuration data. This configuration data is
  1283. * could be derived from the result of bootloader's GCDB
  1284. * panel detection mechanism. If such config data doesn't
  1285. * exist then this panel returns the default panel configured
  1286. * in the device tree.
  1287. *
  1288. * returns pointer to panel node on success, NULL on error.
  1289. */
  1290. static struct device_node *dsi_find_panel_of_node(
  1291. struct platform_device *pdev, char *panel_cfg)
  1292. {
  1293. int l;
  1294. char *panel_name;
  1295. struct device_node *dsi_pan_node = NULL, *mdss_node = NULL;
  1296. if (!panel_cfg)
  1297. return NULL;
  1298. l = strlen(panel_cfg);
  1299. if (!l) {
  1300. /* no panel cfg chg, parse dt */
  1301. pr_debug("%s:%d: no cmd line cfg present\n",
  1302. __func__, __LINE__);
  1303. dsi_pan_node = dsi_pref_prim_panel(pdev);
  1304. } else {
  1305. if (panel_cfg[0] != '0') {
  1306. pr_err("%s:%d:ctrl id=[%d] not supported\n",
  1307. __func__, __LINE__, panel_cfg[0]);
  1308. return NULL;
  1309. }
  1310. /*
  1311. * skip first two chars '<dsi_ctrl_id>' and
  1312. * ':' to get to the panel name
  1313. */
  1314. panel_name = panel_cfg + 2;
  1315. pr_debug("%s:%d:%s:%s\n", __func__, __LINE__,
  1316. panel_cfg, panel_name);
  1317. mdss_node = of_parse_phandle(pdev->dev.of_node,
  1318. "qcom,mdss-mdp", 0);
  1319. if (!mdss_node) {
  1320. pr_err("%s: %d: mdss_node null\n",
  1321. __func__, __LINE__);
  1322. return NULL;
  1323. }
  1324. dsi_pan_node = of_find_node_by_name(mdss_node,
  1325. panel_name);
  1326. if (!dsi_pan_node) {
  1327. pr_err("%s: invalid pan node\n",
  1328. __func__);
  1329. dsi_pan_node = dsi_pref_prim_panel(pdev);
  1330. }
  1331. }
  1332. return dsi_pan_node;
  1333. }
  1334. static int msm_dsi_clk_ctrl(struct mdss_panel_data *pdata, int enable)
  1335. {
  1336. u32 bitclk_rate = 0, byteclk_rate = 0, pclk_rate = 0, dsiclk_rate = 0;
  1337. struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
  1338. pr_debug("%s:\n", __func__);
  1339. ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata,
  1340. panel_data);
  1341. mutex_lock(&ctrl_pdata->mutex);
  1342. if (enable) {
  1343. dsi_host_private->clk_count++;
  1344. if (dsi_host_private->clk_count == 1) {
  1345. msm_dsi_ahb_ctrl(1);
  1346. msm_dsi_cal_clk_rate(pdata, &bitclk_rate, &dsiclk_rate,
  1347. &byteclk_rate, &pclk_rate);
  1348. msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, dsiclk_rate,
  1349. byteclk_rate, pclk_rate);
  1350. msm_dsi_prepare_clocks();
  1351. msm_dsi_clk_enable();
  1352. }
  1353. } else {
  1354. dsi_host_private->clk_count--;
  1355. if (dsi_host_private->clk_count == 0) {
  1356. msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask);
  1357. msm_dsi_clk_set_rate(DSI_ESC_CLK_RATE, 0, 0, 0);
  1358. msm_dsi_clk_disable();
  1359. msm_dsi_unprepare_clocks();
  1360. msm_dsi_ahb_ctrl(0);
  1361. }
  1362. }
  1363. mutex_unlock(&ctrl_pdata->mutex);
  1364. return 0;
  1365. }
  1366. void msm_dsi_ctrl_init(struct mdss_dsi_ctrl_pdata *ctrl)
  1367. {
  1368. init_completion(&ctrl->dma_comp);
  1369. init_completion(&ctrl->mdp_comp);
  1370. init_completion(&ctrl->bta_comp);
  1371. init_completion(&ctrl->video_comp);
  1372. spin_lock_init(&ctrl->irq_lock);
  1373. spin_lock_init(&ctrl->mdp_lock);
  1374. mutex_init(&ctrl->mutex);
  1375. mutex_init(&ctrl->cmd_mutex);
  1376. complete(&ctrl->mdp_comp);
  1377. dsi_buf_alloc(&ctrl->tx_buf, SZ_4K);
  1378. dsi_buf_alloc(&ctrl->rx_buf, SZ_4K);
  1379. dsi_buf_alloc(&ctrl->status_buf, SZ_4K);
  1380. ctrl->cmdlist_commit = msm_dsi_cmdlist_commit;
  1381. ctrl->panel_mode = ctrl->panel_data.panel_info.mipi.mode;
  1382. if (ctrl->status_mode == ESD_REG)
  1383. ctrl->check_status = msm_dsi_reg_status_check;
  1384. else if (ctrl->status_mode == ESD_BTA)
  1385. ctrl->check_status = msm_dsi_bta_status_check;
  1386. if (ctrl->status_mode == ESD_MAX) {
  1387. pr_err("%s: Using default BTA for ESD check\n", __func__);
  1388. ctrl->check_status = msm_dsi_bta_status_check;
  1389. }
  1390. }
  1391. static int __devinit msm_dsi_probe(struct platform_device *pdev)
  1392. {
  1393. struct dsi_interface intf;
  1394. char panel_cfg[MDSS_MAX_PANEL_LEN];
  1395. struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL;
  1396. int rc = 0;
  1397. struct device_node *dsi_pan_node = NULL;
  1398. bool cmd_cfg_cont_splash = false;
  1399. struct resource *mdss_dsi_mres;
  1400. pr_debug("%s\n", __func__);
  1401. rc = msm_dsi_init();
  1402. if (rc)
  1403. return rc;
  1404. if (!pdev->dev.of_node) {
  1405. pr_err("%s: Device node is not accessible\n", __func__);
  1406. rc = -ENODEV;
  1407. goto error_no_mem;
  1408. }
  1409. pdev->id = 0;
  1410. ctrl_pdata = platform_get_drvdata(pdev);
  1411. if (!ctrl_pdata) {
  1412. ctrl_pdata = devm_kzalloc(&pdev->dev,
  1413. sizeof(struct mdss_dsi_ctrl_pdata), GFP_KERNEL);
  1414. if (!ctrl_pdata) {
  1415. pr_err("%s: FAILED: cannot alloc dsi ctrl\n", __func__);
  1416. rc = -ENOMEM;
  1417. goto error_no_mem;
  1418. }
  1419. platform_set_drvdata(pdev, ctrl_pdata);
  1420. }
  1421. mdss_dsi_mres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1422. if (!mdss_dsi_mres) {
  1423. pr_err("%s:%d unable to get the MDSS reg resources",
  1424. __func__, __LINE__);
  1425. rc = -ENOMEM;
  1426. goto error_io_resource;
  1427. } else {
  1428. dsi_host_private->dsi_reg_size = resource_size(mdss_dsi_mres);
  1429. dsi_host_private->dsi_base = ioremap(mdss_dsi_mres->start,
  1430. dsi_host_private->dsi_reg_size);
  1431. if (!dsi_host_private->dsi_base) {
  1432. pr_err("%s:%d unable to remap dsi resources",
  1433. __func__, __LINE__);
  1434. rc = -ENOMEM;
  1435. goto error_io_resource;
  1436. }
  1437. #if defined(CONFIG_FB_MSM_MDSS_DSI_DBG)
  1438. dsi_ctrl_base = dsi_host_private->dsi_base;
  1439. dsi_ctrl_on = dsi_host_private->dsi_on;
  1440. #endif
  1441. }
  1442. mdss_dsi_mres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1443. if (!mdss_dsi_mres || mdss_dsi_mres->start == 0) {
  1444. pr_err("%s:%d unable to get the MDSS irq resources",
  1445. __func__, __LINE__);
  1446. rc = -ENODEV;
  1447. goto error_irq_resource;
  1448. }
  1449. rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
  1450. if (rc) {
  1451. dev_err(&pdev->dev, "%s: failed to add child nodes, rc=%d\n",
  1452. __func__, rc);
  1453. goto error_platform_pop;
  1454. }
  1455. /* DSI panels can be different between controllers */
  1456. rc = dsi_get_panel_cfg(panel_cfg);
  1457. if (!rc)
  1458. /* dsi panel cfg not present */
  1459. pr_warn("%s:%d:dsi specific cfg not present\n",
  1460. __func__, __LINE__);
  1461. /* find panel device node */
  1462. dsi_pan_node = dsi_find_panel_of_node(pdev, panel_cfg);
  1463. if (!dsi_pan_node) {
  1464. pr_err("%s: can't find panel node %s\n", __func__,
  1465. panel_cfg);
  1466. goto error_pan_node;
  1467. }
  1468. cmd_cfg_cont_splash = mdp3_panel_get_boot_cfg() ? true : false;
  1469. rc = mdss_dsi_panel_init(dsi_pan_node, ctrl_pdata, cmd_cfg_cont_splash);
  1470. if (rc) {
  1471. pr_err("%s: dsi panel init failed\n", __func__);
  1472. goto error_pan_node;
  1473. }
  1474. rc = dsi_ctrl_config_init(pdev, ctrl_pdata);
  1475. if (rc) {
  1476. dev_err(&pdev->dev, "%s: failed to parse mdss dtsi rc=%d\n",
  1477. __func__, rc);
  1478. goto error_pan_node;
  1479. }
  1480. rc = msm_dsi_io_init(pdev, &(ctrl_pdata->power_data));
  1481. if (rc) {
  1482. dev_err(&pdev->dev, "%s: failed to init DSI IO, rc=%d\n",
  1483. __func__, rc);
  1484. goto error_io_init;
  1485. }
  1486. pr_debug("%s: Dsi Ctrl->0 initialized\n", __func__);
  1487. dsi_host_private->dis_dev = pdev->dev;
  1488. intf.on = msm_dsi_on;
  1489. intf.off = msm_dsi_off;
  1490. intf.cont_on = msm_dsi_cont_on;
  1491. intf.clk_ctrl = msm_dsi_clk_ctrl;
  1492. intf.op_mode_config = msm_dsi_op_mode_config;
  1493. intf.index = 0;
  1494. intf.private = NULL;
  1495. dsi_register_interface(&intf);
  1496. msm_dsi_debug_init();
  1497. msm_dsi_ctrl_init(ctrl_pdata);
  1498. rc = msm_dsi_irq_init(&pdev->dev, mdss_dsi_mres->start,
  1499. ctrl_pdata);
  1500. if (rc) {
  1501. dev_err(&pdev->dev, "%s: failed to init irq, rc=%d\n",
  1502. __func__, rc);
  1503. goto error_device_register;
  1504. }
  1505. rc = dsi_panel_device_register_v2(pdev, ctrl_pdata);
  1506. if (rc) {
  1507. pr_err("%s: dsi panel dev reg failed\n", __func__);
  1508. goto error_device_register;
  1509. }
  1510. pr_debug("%s success\n", __func__);
  1511. return 0;
  1512. error_device_register:
  1513. msm_dsi_io_deinit(pdev, &(ctrl_pdata->power_data));
  1514. error_io_init:
  1515. dsi_ctrl_config_deinit(pdev, ctrl_pdata);
  1516. error_pan_node:
  1517. of_node_put(dsi_pan_node);
  1518. error_platform_pop:
  1519. msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask);
  1520. error_irq_resource:
  1521. if (dsi_host_private->dsi_base) {
  1522. iounmap(dsi_host_private->dsi_base);
  1523. dsi_host_private->dsi_base = NULL;
  1524. }
  1525. error_io_resource:
  1526. devm_kfree(&pdev->dev, ctrl_pdata);
  1527. error_no_mem:
  1528. msm_dsi_deinit();
  1529. return rc;
  1530. }
  1531. static int __devexit msm_dsi_remove(struct platform_device *pdev)
  1532. {
  1533. struct mdss_dsi_ctrl_pdata *ctrl_pdata = platform_get_drvdata(pdev);
  1534. if (!ctrl_pdata) {
  1535. pr_err("%s: no driver data\n", __func__);
  1536. return -ENODEV;
  1537. }
  1538. msm_dsi_clear_irq(ctrl_pdata, ctrl_pdata->dsi_irq_mask);
  1539. msm_dsi_io_deinit(pdev, &(ctrl_pdata->power_data));
  1540. dsi_ctrl_config_deinit(pdev, ctrl_pdata);
  1541. iounmap(dsi_host_private->dsi_base);
  1542. dsi_host_private->dsi_base = NULL;
  1543. msm_dsi_deinit();
  1544. devm_kfree(&pdev->dev, ctrl_pdata);
  1545. return 0;
  1546. }
  1547. static const struct of_device_id msm_dsi_v2_dt_match[] = {
  1548. {.compatible = "qcom,msm-dsi-v2"},
  1549. {}
  1550. };
  1551. MODULE_DEVICE_TABLE(of, msm_dsi_v2_dt_match);
  1552. static struct platform_driver msm_dsi_v2_driver = {
  1553. .probe = msm_dsi_probe,
  1554. .remove = __devexit_p(msm_dsi_remove),
  1555. .shutdown = NULL,
  1556. .driver = {
  1557. .name = "msm_dsi_v2",
  1558. .of_match_table = msm_dsi_v2_dt_match,
  1559. },
  1560. };
  1561. static int msm_dsi_v2_register_driver(void)
  1562. {
  1563. return platform_driver_register(&msm_dsi_v2_driver);
  1564. }
  1565. static int __init msm_dsi_v2_driver_init(void)
  1566. {
  1567. int ret;
  1568. ret = msm_dsi_v2_register_driver();
  1569. if (ret) {
  1570. pr_err("msm_dsi_v2_register_driver() failed!\n");
  1571. return ret;
  1572. }
  1573. return ret;
  1574. }
  1575. module_init(msm_dsi_v2_driver_init);
  1576. static void __exit msm_dsi_v2_driver_cleanup(void)
  1577. {
  1578. platform_driver_unregister(&msm_dsi_v2_driver);
  1579. }
  1580. module_exit(msm_dsi_v2_driver_cleanup);