mcbsp.c 25 KB

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  1. /*
  2. * sound/soc/omap/mcbsp.c
  3. *
  4. * Copyright (C) 2004 Nokia Corporation
  5. * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
  6. *
  7. * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
  8. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * Multichannel mode not supported.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/err.h>
  22. #include <linux/clk.h>
  23. #include <linux/delay.h>
  24. #include <linux/io.h>
  25. #include <linux/slab.h>
  26. #include <plat/mcbsp.h>
  27. #include "mcbsp.h"
  28. static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  29. {
  30. void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  31. if (mcbsp->pdata->reg_size == 2) {
  32. ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
  33. __raw_writew((u16)val, addr);
  34. } else {
  35. ((u32 *)mcbsp->reg_cache)[reg] = val;
  36. __raw_writel(val, addr);
  37. }
  38. }
  39. static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  40. {
  41. void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  42. if (mcbsp->pdata->reg_size == 2) {
  43. return !from_cache ? __raw_readw(addr) :
  44. ((u16 *)mcbsp->reg_cache)[reg];
  45. } else {
  46. return !from_cache ? __raw_readl(addr) :
  47. ((u32 *)mcbsp->reg_cache)[reg];
  48. }
  49. }
  50. static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  51. {
  52. __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  53. }
  54. static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  55. {
  56. return __raw_readl(mcbsp->st_data->io_base_st + reg);
  57. }
  58. #define MCBSP_READ(mcbsp, reg) \
  59. omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  60. #define MCBSP_WRITE(mcbsp, reg, val) \
  61. omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  62. #define MCBSP_READ_CACHE(mcbsp, reg) \
  63. omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  64. #define MCBSP_ST_READ(mcbsp, reg) \
  65. omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  66. #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  67. omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  68. static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  69. {
  70. dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  71. dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
  72. MCBSP_READ(mcbsp, DRR2));
  73. dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
  74. MCBSP_READ(mcbsp, DRR1));
  75. dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
  76. MCBSP_READ(mcbsp, DXR2));
  77. dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
  78. MCBSP_READ(mcbsp, DXR1));
  79. dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  80. MCBSP_READ(mcbsp, SPCR2));
  81. dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  82. MCBSP_READ(mcbsp, SPCR1));
  83. dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
  84. MCBSP_READ(mcbsp, RCR2));
  85. dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
  86. MCBSP_READ(mcbsp, RCR1));
  87. dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
  88. MCBSP_READ(mcbsp, XCR2));
  89. dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
  90. MCBSP_READ(mcbsp, XCR1));
  91. dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  92. MCBSP_READ(mcbsp, SRGR2));
  93. dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  94. MCBSP_READ(mcbsp, SRGR1));
  95. dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
  96. MCBSP_READ(mcbsp, PCR0));
  97. dev_dbg(mcbsp->dev, "***********************\n");
  98. }
  99. static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  100. {
  101. struct omap_mcbsp *mcbsp_tx = dev_id;
  102. u16 irqst_spcr2;
  103. irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
  104. dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  105. if (irqst_spcr2 & XSYNC_ERR) {
  106. dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
  107. irqst_spcr2);
  108. /* Writing zero to XSYNC_ERR clears the IRQ */
  109. MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
  110. }
  111. return IRQ_HANDLED;
  112. }
  113. static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
  114. {
  115. struct omap_mcbsp *mcbsp_rx = dev_id;
  116. u16 irqst_spcr1;
  117. irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
  118. dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
  119. if (irqst_spcr1 & RSYNC_ERR) {
  120. dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
  121. irqst_spcr1);
  122. /* Writing zero to RSYNC_ERR clears the IRQ */
  123. MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
  124. }
  125. return IRQ_HANDLED;
  126. }
  127. /*
  128. * omap_mcbsp_config simply write a config to the
  129. * appropriate McBSP.
  130. * You either call this function or set the McBSP registers
  131. * by yourself before calling omap_mcbsp_start().
  132. */
  133. void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
  134. const struct omap_mcbsp_reg_cfg *config)
  135. {
  136. dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
  137. mcbsp->id, mcbsp->phys_base);
  138. /* We write the given config */
  139. MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
  140. MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
  141. MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
  142. MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
  143. MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
  144. MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
  145. MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
  146. MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
  147. MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
  148. MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
  149. MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
  150. if (mcbsp->pdata->has_ccr) {
  151. MCBSP_WRITE(mcbsp, XCCR, config->xccr);
  152. MCBSP_WRITE(mcbsp, RCCR, config->rccr);
  153. }
  154. /* Enable wakeup behavior */
  155. if (mcbsp->pdata->has_wakeup)
  156. MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
  157. }
  158. /**
  159. * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
  160. * @id - mcbsp id
  161. * @stream - indicates the direction of data flow (rx or tx)
  162. *
  163. * Returns the address of mcbsp data transmit register or data receive register
  164. * to be used by DMA for transferring/receiving data based on the value of
  165. * @stream for the requested mcbsp given by @id
  166. */
  167. static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
  168. unsigned int stream)
  169. {
  170. int data_reg;
  171. if (mcbsp->pdata->reg_size == 2) {
  172. if (stream)
  173. data_reg = OMAP_MCBSP_REG_DRR1;
  174. else
  175. data_reg = OMAP_MCBSP_REG_DXR1;
  176. } else {
  177. if (stream)
  178. data_reg = OMAP_MCBSP_REG_DRR;
  179. else
  180. data_reg = OMAP_MCBSP_REG_DXR;
  181. }
  182. return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
  183. }
  184. static void omap_st_on(struct omap_mcbsp *mcbsp)
  185. {
  186. unsigned int w;
  187. if (mcbsp->pdata->enable_st_clock)
  188. mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
  189. /* Enable McBSP Sidetone */
  190. w = MCBSP_READ(mcbsp, SSELCR);
  191. MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
  192. /* Enable Sidetone from Sidetone Core */
  193. w = MCBSP_ST_READ(mcbsp, SSELCR);
  194. MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
  195. }
  196. static void omap_st_off(struct omap_mcbsp *mcbsp)
  197. {
  198. unsigned int w;
  199. w = MCBSP_ST_READ(mcbsp, SSELCR);
  200. MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
  201. w = MCBSP_READ(mcbsp, SSELCR);
  202. MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
  203. if (mcbsp->pdata->enable_st_clock)
  204. mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
  205. }
  206. static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
  207. {
  208. u16 val, i;
  209. val = MCBSP_ST_READ(mcbsp, SSELCR);
  210. if (val & ST_COEFFWREN)
  211. MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
  212. MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
  213. for (i = 0; i < 128; i++)
  214. MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
  215. i = 0;
  216. val = MCBSP_ST_READ(mcbsp, SSELCR);
  217. while (!(val & ST_COEFFWRDONE) && (++i < 1000))
  218. val = MCBSP_ST_READ(mcbsp, SSELCR);
  219. MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
  220. if (i == 1000)
  221. dev_err(mcbsp->dev, "McBSP FIR load error!\n");
  222. }
  223. static void omap_st_chgain(struct omap_mcbsp *mcbsp)
  224. {
  225. u16 w;
  226. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  227. w = MCBSP_ST_READ(mcbsp, SSELCR);
  228. MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
  229. ST_CH1GAIN(st_data->ch1gain));
  230. }
  231. int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
  232. {
  233. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  234. int ret = 0;
  235. if (!st_data)
  236. return -ENOENT;
  237. spin_lock_irq(&mcbsp->lock);
  238. if (channel == 0)
  239. st_data->ch0gain = chgain;
  240. else if (channel == 1)
  241. st_data->ch1gain = chgain;
  242. else
  243. ret = -EINVAL;
  244. if (st_data->enabled)
  245. omap_st_chgain(mcbsp);
  246. spin_unlock_irq(&mcbsp->lock);
  247. return ret;
  248. }
  249. int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
  250. {
  251. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  252. int ret = 0;
  253. if (!st_data)
  254. return -ENOENT;
  255. spin_lock_irq(&mcbsp->lock);
  256. if (channel == 0)
  257. *chgain = st_data->ch0gain;
  258. else if (channel == 1)
  259. *chgain = st_data->ch1gain;
  260. else
  261. ret = -EINVAL;
  262. spin_unlock_irq(&mcbsp->lock);
  263. return ret;
  264. }
  265. static int omap_st_start(struct omap_mcbsp *mcbsp)
  266. {
  267. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  268. if (st_data->enabled && !st_data->running) {
  269. omap_st_fir_write(mcbsp, st_data->taps);
  270. omap_st_chgain(mcbsp);
  271. if (!mcbsp->free) {
  272. omap_st_on(mcbsp);
  273. st_data->running = 1;
  274. }
  275. }
  276. return 0;
  277. }
  278. int omap_st_enable(struct omap_mcbsp *mcbsp)
  279. {
  280. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  281. if (!st_data)
  282. return -ENODEV;
  283. spin_lock_irq(&mcbsp->lock);
  284. st_data->enabled = 1;
  285. omap_st_start(mcbsp);
  286. spin_unlock_irq(&mcbsp->lock);
  287. return 0;
  288. }
  289. static int omap_st_stop(struct omap_mcbsp *mcbsp)
  290. {
  291. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  292. if (st_data->running) {
  293. if (!mcbsp->free) {
  294. omap_st_off(mcbsp);
  295. st_data->running = 0;
  296. }
  297. }
  298. return 0;
  299. }
  300. int omap_st_disable(struct omap_mcbsp *mcbsp)
  301. {
  302. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  303. int ret = 0;
  304. if (!st_data)
  305. return -ENODEV;
  306. spin_lock_irq(&mcbsp->lock);
  307. omap_st_stop(mcbsp);
  308. st_data->enabled = 0;
  309. spin_unlock_irq(&mcbsp->lock);
  310. return ret;
  311. }
  312. int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
  313. {
  314. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  315. if (!st_data)
  316. return -ENODEV;
  317. return st_data->enabled;
  318. }
  319. /*
  320. * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
  321. * The threshold parameter is 1 based, and it is converted (threshold - 1)
  322. * for the THRSH2 register.
  323. */
  324. void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
  325. {
  326. if (mcbsp->pdata->buffer_size == 0)
  327. return;
  328. if (threshold && threshold <= mcbsp->max_tx_thres)
  329. MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
  330. }
  331. /*
  332. * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
  333. * The threshold parameter is 1 based, and it is converted (threshold - 1)
  334. * for the THRSH1 register.
  335. */
  336. void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
  337. {
  338. if (mcbsp->pdata->buffer_size == 0)
  339. return;
  340. if (threshold && threshold <= mcbsp->max_rx_thres)
  341. MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
  342. }
  343. /*
  344. * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
  345. */
  346. u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
  347. {
  348. u16 buffstat;
  349. if (mcbsp->pdata->buffer_size == 0)
  350. return 0;
  351. /* Returns the number of free locations in the buffer */
  352. buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
  353. /* Number of slots are different in McBSP ports */
  354. return mcbsp->pdata->buffer_size - buffstat;
  355. }
  356. /*
  357. * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
  358. * to reach the threshold value (when the DMA will be triggered to read it)
  359. */
  360. u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
  361. {
  362. u16 buffstat, threshold;
  363. if (mcbsp->pdata->buffer_size == 0)
  364. return 0;
  365. /* Returns the number of used locations in the buffer */
  366. buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
  367. /* RX threshold */
  368. threshold = MCBSP_READ(mcbsp, THRSH1);
  369. /* Return the number of location till we reach the threshold limit */
  370. if (threshold <= buffstat)
  371. return 0;
  372. else
  373. return threshold - buffstat;
  374. }
  375. int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
  376. {
  377. void *reg_cache;
  378. int err;
  379. reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
  380. if (!reg_cache) {
  381. return -ENOMEM;
  382. }
  383. spin_lock(&mcbsp->lock);
  384. if (!mcbsp->free) {
  385. dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
  386. mcbsp->id);
  387. err = -EBUSY;
  388. goto err_kfree;
  389. }
  390. mcbsp->free = false;
  391. mcbsp->reg_cache = reg_cache;
  392. spin_unlock(&mcbsp->lock);
  393. if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
  394. mcbsp->pdata->ops->request(mcbsp->id - 1);
  395. /*
  396. * Make sure that transmitter, receiver and sample-rate generator are
  397. * not running before activating IRQs.
  398. */
  399. MCBSP_WRITE(mcbsp, SPCR1, 0);
  400. MCBSP_WRITE(mcbsp, SPCR2, 0);
  401. err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
  402. 0, "McBSP", (void *)mcbsp);
  403. if (err != 0) {
  404. dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
  405. "for McBSP%d\n", mcbsp->tx_irq,
  406. mcbsp->id);
  407. goto err_clk_disable;
  408. }
  409. if (mcbsp->rx_irq) {
  410. err = request_irq(mcbsp->rx_irq,
  411. omap_mcbsp_rx_irq_handler,
  412. 0, "McBSP", (void *)mcbsp);
  413. if (err != 0) {
  414. dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
  415. "for McBSP%d\n", mcbsp->rx_irq,
  416. mcbsp->id);
  417. goto err_free_irq;
  418. }
  419. }
  420. return 0;
  421. err_free_irq:
  422. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  423. err_clk_disable:
  424. if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  425. mcbsp->pdata->ops->free(mcbsp->id - 1);
  426. /* Disable wakeup behavior */
  427. if (mcbsp->pdata->has_wakeup)
  428. MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
  429. spin_lock(&mcbsp->lock);
  430. mcbsp->free = true;
  431. mcbsp->reg_cache = NULL;
  432. err_kfree:
  433. spin_unlock(&mcbsp->lock);
  434. kfree(reg_cache);
  435. return err;
  436. }
  437. void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
  438. {
  439. void *reg_cache;
  440. if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  441. mcbsp->pdata->ops->free(mcbsp->id - 1);
  442. /* Disable wakeup behavior */
  443. if (mcbsp->pdata->has_wakeup)
  444. MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
  445. if (mcbsp->rx_irq)
  446. free_irq(mcbsp->rx_irq, (void *)mcbsp);
  447. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  448. reg_cache = mcbsp->reg_cache;
  449. /*
  450. * Select CLKS source from internal source unconditionally before
  451. * marking the McBSP port as free.
  452. * If the external clock source via MCBSP_CLKS pin has been selected the
  453. * system will refuse to enter idle if the CLKS pin source is not reset
  454. * back to internal source.
  455. */
  456. if (!cpu_class_is_omap1())
  457. omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
  458. spin_lock(&mcbsp->lock);
  459. if (mcbsp->free)
  460. dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
  461. else
  462. mcbsp->free = true;
  463. mcbsp->reg_cache = NULL;
  464. spin_unlock(&mcbsp->lock);
  465. if (reg_cache)
  466. kfree(reg_cache);
  467. }
  468. /*
  469. * Here we start the McBSP, by enabling transmitter, receiver or both.
  470. * If no transmitter or receiver is active prior calling, then sample-rate
  471. * generator and frame sync are started.
  472. */
  473. void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
  474. {
  475. int enable_srg = 0;
  476. u16 w;
  477. if (mcbsp->st_data)
  478. omap_st_start(mcbsp);
  479. /* Only enable SRG, if McBSP is master */
  480. w = MCBSP_READ_CACHE(mcbsp, PCR0);
  481. if (w & (FSXM | FSRM | CLKXM | CLKRM))
  482. enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
  483. MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
  484. if (enable_srg) {
  485. /* Start the sample generator */
  486. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  487. MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
  488. }
  489. /* Enable transmitter and receiver */
  490. tx &= 1;
  491. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  492. MCBSP_WRITE(mcbsp, SPCR2, w | tx);
  493. rx &= 1;
  494. w = MCBSP_READ_CACHE(mcbsp, SPCR1);
  495. MCBSP_WRITE(mcbsp, SPCR1, w | rx);
  496. /*
  497. * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
  498. * REVISIT: 100us may give enough time for two CLKSRG, however
  499. * due to some unknown PM related, clock gating etc. reason it
  500. * is now at 500us.
  501. */
  502. udelay(500);
  503. if (enable_srg) {
  504. /* Start frame sync */
  505. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  506. MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
  507. }
  508. if (mcbsp->pdata->has_ccr) {
  509. /* Release the transmitter and receiver */
  510. w = MCBSP_READ_CACHE(mcbsp, XCCR);
  511. w &= ~(tx ? XDISABLE : 0);
  512. MCBSP_WRITE(mcbsp, XCCR, w);
  513. w = MCBSP_READ_CACHE(mcbsp, RCCR);
  514. w &= ~(rx ? RDISABLE : 0);
  515. MCBSP_WRITE(mcbsp, RCCR, w);
  516. }
  517. /* Dump McBSP Regs */
  518. omap_mcbsp_dump_reg(mcbsp);
  519. }
  520. void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
  521. {
  522. int idle;
  523. u16 w;
  524. /* Reset transmitter */
  525. tx &= 1;
  526. if (mcbsp->pdata->has_ccr) {
  527. w = MCBSP_READ_CACHE(mcbsp, XCCR);
  528. w |= (tx ? XDISABLE : 0);
  529. MCBSP_WRITE(mcbsp, XCCR, w);
  530. }
  531. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  532. MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
  533. /* Reset receiver */
  534. rx &= 1;
  535. if (mcbsp->pdata->has_ccr) {
  536. w = MCBSP_READ_CACHE(mcbsp, RCCR);
  537. w |= (rx ? RDISABLE : 0);
  538. MCBSP_WRITE(mcbsp, RCCR, w);
  539. }
  540. w = MCBSP_READ_CACHE(mcbsp, SPCR1);
  541. MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
  542. idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
  543. MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
  544. if (idle) {
  545. /* Reset the sample rate generator */
  546. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  547. MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
  548. }
  549. if (mcbsp->st_data)
  550. omap_st_stop(mcbsp);
  551. }
  552. int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
  553. {
  554. const char *src;
  555. if (fck_src_id == MCBSP_CLKS_PAD_SRC)
  556. src = "clks_ext";
  557. else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
  558. src = "clks_fclk";
  559. else
  560. return -EINVAL;
  561. if (mcbsp->pdata->set_clk_src)
  562. return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
  563. else
  564. return -EINVAL;
  565. }
  566. int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
  567. {
  568. const char *signal, *src;
  569. if (!mcbsp->pdata->mux_signal)
  570. return -EINVAL;
  571. switch (mux) {
  572. case CLKR_SRC_CLKR:
  573. signal = "clkr";
  574. src = "clkr";
  575. break;
  576. case CLKR_SRC_CLKX:
  577. signal = "clkr";
  578. src = "clkx";
  579. break;
  580. case FSR_SRC_FSR:
  581. signal = "fsr";
  582. src = "fsr";
  583. break;
  584. case FSR_SRC_FSX:
  585. signal = "fsr";
  586. src = "fsx";
  587. break;
  588. default:
  589. return -EINVAL;
  590. }
  591. return mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
  592. }
  593. #define max_thres(m) (mcbsp->pdata->buffer_size)
  594. #define valid_threshold(m, val) ((val) <= max_thres(m))
  595. #define THRESHOLD_PROP_BUILDER(prop) \
  596. static ssize_t prop##_show(struct device *dev, \
  597. struct device_attribute *attr, char *buf) \
  598. { \
  599. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
  600. \
  601. return sprintf(buf, "%u\n", mcbsp->prop); \
  602. } \
  603. \
  604. static ssize_t prop##_store(struct device *dev, \
  605. struct device_attribute *attr, \
  606. const char *buf, size_t size) \
  607. { \
  608. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
  609. unsigned long val; \
  610. int status; \
  611. \
  612. status = strict_strtoul(buf, 0, &val); \
  613. if (status) \
  614. return status; \
  615. \
  616. if (!valid_threshold(mcbsp, val)) \
  617. return -EDOM; \
  618. \
  619. mcbsp->prop = val; \
  620. return size; \
  621. } \
  622. \
  623. static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
  624. THRESHOLD_PROP_BUILDER(max_tx_thres);
  625. THRESHOLD_PROP_BUILDER(max_rx_thres);
  626. static const char *dma_op_modes[] = {
  627. "element", "threshold", "frame",
  628. };
  629. static ssize_t dma_op_mode_show(struct device *dev,
  630. struct device_attribute *attr, char *buf)
  631. {
  632. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  633. int dma_op_mode, i = 0;
  634. ssize_t len = 0;
  635. const char * const *s;
  636. dma_op_mode = mcbsp->dma_op_mode;
  637. for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
  638. if (dma_op_mode == i)
  639. len += sprintf(buf + len, "[%s] ", *s);
  640. else
  641. len += sprintf(buf + len, "%s ", *s);
  642. }
  643. len += sprintf(buf + len, "\n");
  644. return len;
  645. }
  646. static ssize_t dma_op_mode_store(struct device *dev,
  647. struct device_attribute *attr,
  648. const char *buf, size_t size)
  649. {
  650. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  651. const char * const *s;
  652. int i = 0;
  653. for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
  654. if (sysfs_streq(buf, *s))
  655. break;
  656. if (i == ARRAY_SIZE(dma_op_modes))
  657. return -EINVAL;
  658. spin_lock_irq(&mcbsp->lock);
  659. if (!mcbsp->free) {
  660. size = -EBUSY;
  661. goto unlock;
  662. }
  663. mcbsp->dma_op_mode = i;
  664. unlock:
  665. spin_unlock_irq(&mcbsp->lock);
  666. return size;
  667. }
  668. static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
  669. static const struct attribute *additional_attrs[] = {
  670. &dev_attr_max_tx_thres.attr,
  671. &dev_attr_max_rx_thres.attr,
  672. &dev_attr_dma_op_mode.attr,
  673. NULL,
  674. };
  675. static const struct attribute_group additional_attr_group = {
  676. .attrs = (struct attribute **)additional_attrs,
  677. };
  678. static ssize_t st_taps_show(struct device *dev,
  679. struct device_attribute *attr, char *buf)
  680. {
  681. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  682. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  683. ssize_t status = 0;
  684. int i;
  685. spin_lock_irq(&mcbsp->lock);
  686. for (i = 0; i < st_data->nr_taps; i++)
  687. status += sprintf(&buf[status], (i ? ", %d" : "%d"),
  688. st_data->taps[i]);
  689. if (i)
  690. status += sprintf(&buf[status], "\n");
  691. spin_unlock_irq(&mcbsp->lock);
  692. return status;
  693. }
  694. static ssize_t st_taps_store(struct device *dev,
  695. struct device_attribute *attr,
  696. const char *buf, size_t size)
  697. {
  698. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  699. struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
  700. int val, tmp, status, i = 0;
  701. spin_lock_irq(&mcbsp->lock);
  702. memset(st_data->taps, 0, sizeof(st_data->taps));
  703. st_data->nr_taps = 0;
  704. do {
  705. status = sscanf(buf, "%d%n", &val, &tmp);
  706. if (status < 0 || status == 0) {
  707. size = -EINVAL;
  708. goto out;
  709. }
  710. if (val < -32768 || val > 32767) {
  711. size = -EINVAL;
  712. goto out;
  713. }
  714. st_data->taps[i++] = val;
  715. buf += tmp;
  716. if (*buf != ',')
  717. break;
  718. buf++;
  719. } while (1);
  720. st_data->nr_taps = i;
  721. out:
  722. spin_unlock_irq(&mcbsp->lock);
  723. return size;
  724. }
  725. static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
  726. static const struct attribute *sidetone_attrs[] = {
  727. &dev_attr_st_taps.attr,
  728. NULL,
  729. };
  730. static const struct attribute_group sidetone_attr_group = {
  731. .attrs = (struct attribute **)sidetone_attrs,
  732. };
  733. static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
  734. struct resource *res)
  735. {
  736. struct omap_mcbsp_st_data *st_data;
  737. int err;
  738. st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
  739. if (!st_data)
  740. return -ENOMEM;
  741. st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
  742. resource_size(res));
  743. if (!st_data->io_base_st)
  744. return -ENOMEM;
  745. err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
  746. if (err)
  747. return err;
  748. mcbsp->st_data = st_data;
  749. return 0;
  750. }
  751. /*
  752. * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
  753. * 730 has only 2 McBSP, and both of them are MPU peripherals.
  754. */
  755. int __devinit omap_mcbsp_init(struct platform_device *pdev)
  756. {
  757. struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
  758. struct resource *res;
  759. int ret = 0;
  760. spin_lock_init(&mcbsp->lock);
  761. mcbsp->free = true;
  762. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  763. if (!res) {
  764. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  765. if (!res) {
  766. dev_err(mcbsp->dev, "invalid memory resource\n");
  767. return -ENOMEM;
  768. }
  769. }
  770. if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
  771. dev_name(&pdev->dev))) {
  772. dev_err(mcbsp->dev, "memory region already claimed\n");
  773. return -ENODEV;
  774. }
  775. mcbsp->phys_base = res->start;
  776. mcbsp->reg_cache_size = resource_size(res);
  777. mcbsp->io_base = devm_ioremap(&pdev->dev, res->start,
  778. resource_size(res));
  779. if (!mcbsp->io_base)
  780. return -ENOMEM;
  781. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  782. if (!res)
  783. mcbsp->phys_dma_base = mcbsp->phys_base;
  784. else
  785. mcbsp->phys_dma_base = res->start;
  786. mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
  787. mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
  788. /* From OMAP4 there will be a single irq line */
  789. if (mcbsp->tx_irq == -ENXIO) {
  790. mcbsp->tx_irq = platform_get_irq(pdev, 0);
  791. mcbsp->rx_irq = 0;
  792. }
  793. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
  794. if (!res) {
  795. dev_err(&pdev->dev, "invalid rx DMA channel\n");
  796. return -ENODEV;
  797. }
  798. /* RX DMA request number, and port address configuration */
  799. mcbsp->dma_data[1].name = "Audio Capture";
  800. mcbsp->dma_data[1].dma_req = res->start;
  801. mcbsp->dma_data[1].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
  802. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
  803. if (!res) {
  804. dev_err(&pdev->dev, "invalid tx DMA channel\n");
  805. return -ENODEV;
  806. }
  807. /* TX DMA request number, and port address configuration */
  808. mcbsp->dma_data[0].name = "Audio Playback";
  809. mcbsp->dma_data[0].dma_req = res->start;
  810. mcbsp->dma_data[0].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
  811. mcbsp->fclk = clk_get(&pdev->dev, "fck");
  812. if (IS_ERR(mcbsp->fclk)) {
  813. ret = PTR_ERR(mcbsp->fclk);
  814. dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
  815. return ret;
  816. }
  817. mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
  818. if (mcbsp->pdata->buffer_size) {
  819. /*
  820. * Initially configure the maximum thresholds to a safe value.
  821. * The McBSP FIFO usage with these values should not go under
  822. * 16 locations.
  823. * If the whole FIFO without safety buffer is used, than there
  824. * is a possibility that the DMA will be not able to push the
  825. * new data on time, causing channel shifts in runtime.
  826. */
  827. mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
  828. mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
  829. ret = sysfs_create_group(&mcbsp->dev->kobj,
  830. &additional_attr_group);
  831. if (ret) {
  832. dev_err(mcbsp->dev,
  833. "Unable to create additional controls\n");
  834. goto err_thres;
  835. }
  836. } else {
  837. mcbsp->max_tx_thres = -EINVAL;
  838. mcbsp->max_rx_thres = -EINVAL;
  839. }
  840. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
  841. if (res) {
  842. ret = omap_st_add(mcbsp, res);
  843. if (ret) {
  844. dev_err(mcbsp->dev,
  845. "Unable to create sidetone controls\n");
  846. goto err_st;
  847. }
  848. }
  849. return 0;
  850. err_st:
  851. if (mcbsp->pdata->buffer_size)
  852. sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
  853. err_thres:
  854. clk_put(mcbsp->fclk);
  855. return ret;
  856. }
  857. void __devexit omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
  858. {
  859. if (mcbsp->pdata->buffer_size)
  860. sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
  861. if (mcbsp->st_data)
  862. sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
  863. }