ams-delta.c 7.3 KB

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  1. /*
  2. * drivers/mtd/nand/ams-delta.c
  3. *
  4. * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
  5. *
  6. * Derived from drivers/mtd/toto.c
  7. * Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
  8. * Partially stolen from drivers/mtd/nand/plat_nand.c
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * Overview:
  15. * This is a device driver for the NAND flash device found on the
  16. * Amstrad E3 (Delta).
  17. */
  18. #include <linux/slab.h>
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/delay.h>
  22. #include <linux/mtd/mtd.h>
  23. #include <linux/mtd/nand.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <asm/io.h>
  26. #include <mach/hardware.h>
  27. #include <asm/sizes.h>
  28. #include <linux/gpio.h>
  29. #include <plat/board-ams-delta.h>
  30. /*
  31. * MTD structure for E3 (Delta)
  32. */
  33. static struct mtd_info *ams_delta_mtd = NULL;
  34. /*
  35. * Define partitions for flash devices
  36. */
  37. static struct mtd_partition partition_info[] = {
  38. { .name = "Kernel",
  39. .offset = 0,
  40. .size = 3 * SZ_1M + SZ_512K },
  41. { .name = "u-boot",
  42. .offset = 3 * SZ_1M + SZ_512K,
  43. .size = SZ_256K },
  44. { .name = "u-boot params",
  45. .offset = 3 * SZ_1M + SZ_512K + SZ_256K,
  46. .size = SZ_256K },
  47. { .name = "Amstrad LDR",
  48. .offset = 4 * SZ_1M,
  49. .size = SZ_256K },
  50. { .name = "File system",
  51. .offset = 4 * SZ_1M + 1 * SZ_256K,
  52. .size = 27 * SZ_1M },
  53. { .name = "PBL reserved",
  54. .offset = 32 * SZ_1M - 3 * SZ_256K,
  55. .size = 3 * SZ_256K },
  56. };
  57. static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
  58. {
  59. struct nand_chip *this = mtd->priv;
  60. void __iomem *io_base = this->priv;
  61. writew(0, io_base + OMAP_MPUIO_IO_CNTL);
  62. writew(byte, this->IO_ADDR_W);
  63. gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
  64. ndelay(40);
  65. gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
  66. }
  67. static u_char ams_delta_read_byte(struct mtd_info *mtd)
  68. {
  69. u_char res;
  70. struct nand_chip *this = mtd->priv;
  71. void __iomem *io_base = this->priv;
  72. gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0);
  73. ndelay(40);
  74. writew(~0, io_base + OMAP_MPUIO_IO_CNTL);
  75. res = readw(this->IO_ADDR_R);
  76. gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1);
  77. return res;
  78. }
  79. static void ams_delta_write_buf(struct mtd_info *mtd, const u_char *buf,
  80. int len)
  81. {
  82. int i;
  83. for (i=0; i<len; i++)
  84. ams_delta_write_byte(mtd, buf[i]);
  85. }
  86. static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  87. {
  88. int i;
  89. for (i=0; i<len; i++)
  90. buf[i] = ams_delta_read_byte(mtd);
  91. }
  92. static int ams_delta_verify_buf(struct mtd_info *mtd, const u_char *buf,
  93. int len)
  94. {
  95. int i;
  96. for (i=0; i<len; i++)
  97. if (buf[i] != ams_delta_read_byte(mtd))
  98. return -EFAULT;
  99. return 0;
  100. }
  101. /*
  102. * Command control function
  103. *
  104. * ctrl:
  105. * NAND_NCE: bit 0 -> bit 2
  106. * NAND_CLE: bit 1 -> bit 7
  107. * NAND_ALE: bit 2 -> bit 6
  108. */
  109. static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd,
  110. unsigned int ctrl)
  111. {
  112. if (ctrl & NAND_CTRL_CHANGE) {
  113. gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE,
  114. (ctrl & NAND_NCE) == 0);
  115. gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE,
  116. (ctrl & NAND_CLE) != 0);
  117. gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE,
  118. (ctrl & NAND_ALE) != 0);
  119. }
  120. if (cmd != NAND_CMD_NONE)
  121. ams_delta_write_byte(mtd, cmd);
  122. }
  123. static int ams_delta_nand_ready(struct mtd_info *mtd)
  124. {
  125. return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB);
  126. }
  127. static const struct gpio _mandatory_gpio[] = {
  128. {
  129. .gpio = AMS_DELTA_GPIO_PIN_NAND_NCE,
  130. .flags = GPIOF_OUT_INIT_HIGH,
  131. .label = "nand_nce",
  132. },
  133. {
  134. .gpio = AMS_DELTA_GPIO_PIN_NAND_NRE,
  135. .flags = GPIOF_OUT_INIT_HIGH,
  136. .label = "nand_nre",
  137. },
  138. {
  139. .gpio = AMS_DELTA_GPIO_PIN_NAND_NWP,
  140. .flags = GPIOF_OUT_INIT_HIGH,
  141. .label = "nand_nwp",
  142. },
  143. {
  144. .gpio = AMS_DELTA_GPIO_PIN_NAND_NWE,
  145. .flags = GPIOF_OUT_INIT_HIGH,
  146. .label = "nand_nwe",
  147. },
  148. {
  149. .gpio = AMS_DELTA_GPIO_PIN_NAND_ALE,
  150. .flags = GPIOF_OUT_INIT_LOW,
  151. .label = "nand_ale",
  152. },
  153. {
  154. .gpio = AMS_DELTA_GPIO_PIN_NAND_CLE,
  155. .flags = GPIOF_OUT_INIT_LOW,
  156. .label = "nand_cle",
  157. },
  158. };
  159. /*
  160. * Main initialization routine
  161. */
  162. static int __devinit ams_delta_init(struct platform_device *pdev)
  163. {
  164. struct nand_chip *this;
  165. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  166. void __iomem *io_base;
  167. int err = 0;
  168. if (!res)
  169. return -ENXIO;
  170. /* Allocate memory for MTD device structure and private data */
  171. ams_delta_mtd = kmalloc(sizeof(struct mtd_info) +
  172. sizeof(struct nand_chip), GFP_KERNEL);
  173. if (!ams_delta_mtd) {
  174. printk (KERN_WARNING "Unable to allocate E3 NAND MTD device structure.\n");
  175. err = -ENOMEM;
  176. goto out;
  177. }
  178. ams_delta_mtd->owner = THIS_MODULE;
  179. /* Get pointer to private data */
  180. this = (struct nand_chip *) (&ams_delta_mtd[1]);
  181. /* Initialize structures */
  182. memset(ams_delta_mtd, 0, sizeof(struct mtd_info));
  183. memset(this, 0, sizeof(struct nand_chip));
  184. /* Link the private data with the MTD structure */
  185. ams_delta_mtd->priv = this;
  186. /*
  187. * Don't try to request the memory region from here,
  188. * it should have been already requested from the
  189. * gpio-omap driver and requesting it again would fail.
  190. */
  191. io_base = ioremap(res->start, resource_size(res));
  192. if (io_base == NULL) {
  193. dev_err(&pdev->dev, "ioremap failed\n");
  194. err = -EIO;
  195. goto out_free;
  196. }
  197. this->priv = io_base;
  198. /* Set address of NAND IO lines */
  199. this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH;
  200. this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT;
  201. this->read_byte = ams_delta_read_byte;
  202. this->write_buf = ams_delta_write_buf;
  203. this->read_buf = ams_delta_read_buf;
  204. this->verify_buf = ams_delta_verify_buf;
  205. this->cmd_ctrl = ams_delta_hwcontrol;
  206. if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
  207. this->dev_ready = ams_delta_nand_ready;
  208. } else {
  209. this->dev_ready = NULL;
  210. printk(KERN_NOTICE "Couldn't request gpio for Delta NAND ready.\n");
  211. }
  212. /* 25 us command delay time */
  213. this->chip_delay = 30;
  214. this->ecc.mode = NAND_ECC_SOFT;
  215. platform_set_drvdata(pdev, io_base);
  216. /* Set chip enabled, but */
  217. err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
  218. if (err)
  219. goto out_gpio;
  220. /* Scan to find existence of the device */
  221. if (nand_scan(ams_delta_mtd, 1)) {
  222. err = -ENXIO;
  223. goto out_mtd;
  224. }
  225. /* Register the partitions */
  226. mtd_device_register(ams_delta_mtd, partition_info,
  227. ARRAY_SIZE(partition_info));
  228. goto out;
  229. out_mtd:
  230. gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
  231. out_gpio:
  232. platform_set_drvdata(pdev, NULL);
  233. gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
  234. iounmap(io_base);
  235. out_free:
  236. kfree(ams_delta_mtd);
  237. out:
  238. return err;
  239. }
  240. /*
  241. * Clean up routine
  242. */
  243. static int __devexit ams_delta_cleanup(struct platform_device *pdev)
  244. {
  245. void __iomem *io_base = platform_get_drvdata(pdev);
  246. /* Release resources, unregister device */
  247. nand_release(ams_delta_mtd);
  248. gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
  249. gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
  250. iounmap(io_base);
  251. /* Free the MTD device structure */
  252. kfree(ams_delta_mtd);
  253. return 0;
  254. }
  255. static struct platform_driver ams_delta_nand_driver = {
  256. .probe = ams_delta_init,
  257. .remove = __devexit_p(ams_delta_cleanup),
  258. .driver = {
  259. .name = "ams-delta-nand",
  260. .owner = THIS_MODULE,
  261. },
  262. };
  263. module_platform_driver(ams_delta_nand_driver);
  264. MODULE_LICENSE("GPL");
  265. MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
  266. MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");