devices-msm7x30.c 29 KB

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  1. /*
  2. * Copyright (C) 2008 Google, Inc.
  3. * Copyright (c) 2008-2012, The Linux Foundation. All rights reserved.
  4. *
  5. * This software is licensed under the terms of the GNU General Public
  6. * License version 2, as published by the Free Software Foundation, and
  7. * may be copied, distributed, and modified under those terms.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/msm_rotator.h>
  18. #include <linux/dma-mapping.h>
  19. #include <mach/kgsl.h>
  20. #include <linux/regulator/machine.h>
  21. #include <linux/init.h>
  22. #include <mach/irqs.h>
  23. #include <mach/msm_iomap.h>
  24. #include <mach/dma.h>
  25. #include <mach/board.h>
  26. #include <asm/clkdev.h>
  27. #include <linux/msm_ion.h>
  28. #include "devices.h"
  29. #include "footswitch.h"
  30. #include <asm/mach/flash.h>
  31. #include <asm/mach/mmc.h>
  32. #include <mach/msm_hsusb.h>
  33. #ifdef CONFIG_PMIC8058
  34. #include <linux/mfd/pmic8058.h>
  35. #endif
  36. #include <mach/dal_axi.h>
  37. #include <mach/msm_memtypes.h>
  38. #include "pm.h"
  39. #include "irq.h"
  40. struct platform_device msm7x30_device_acpuclk = {
  41. .name = "acpuclk-7x30",
  42. .id = -1,
  43. };
  44. /* EBI THERMAL DRIVER */
  45. static struct resource msm_ebi0_thermal_resources[] = {
  46. {
  47. .start = 0xA8600000,
  48. .end = 0xA86005FF,
  49. .name = "physbase",
  50. .flags = IORESOURCE_MEM
  51. }
  52. };
  53. struct platform_device msm_ebi0_thermal = {
  54. .name = "msm_popmem-tm",
  55. .id = 0,
  56. .num_resources = 1,
  57. .resource = msm_ebi0_thermal_resources
  58. };
  59. static struct resource msm_ebi1_thermal_resources[] = {
  60. {
  61. .start = 0xA8700000,
  62. .end = 0xA87005FF,
  63. .name = "physbase",
  64. .flags = IORESOURCE_MEM
  65. }
  66. };
  67. struct platform_device msm_ebi1_thermal = {
  68. .name = "msm_popmem-tm",
  69. .id = 1,
  70. .num_resources = 1,
  71. .resource = msm_ebi1_thermal_resources
  72. };
  73. static struct resource resources_adsp[] = {
  74. {
  75. .start = INT_ADSP_A9_A11,
  76. .end = INT_ADSP_A9_A11,
  77. .flags = IORESOURCE_IRQ,
  78. },
  79. };
  80. struct platform_device msm_adsp_device = {
  81. .name = "msm_adsp",
  82. .id = -1,
  83. .num_resources = ARRAY_SIZE(resources_adsp),
  84. .resource = resources_adsp,
  85. };
  86. static struct resource resources_uart1[] = {
  87. {
  88. .start = INT_UART1,
  89. .end = INT_UART1,
  90. .flags = IORESOURCE_IRQ,
  91. },
  92. {
  93. .start = MSM7X30_UART1_PHYS,
  94. .end = MSM7X30_UART1_PHYS + MSM7X30_UART1_SIZE - 1,
  95. .flags = IORESOURCE_MEM,
  96. },
  97. };
  98. static struct resource resources_uart2[] = {
  99. {
  100. .start = INT_UART2,
  101. .end = INT_UART2,
  102. .flags = IORESOURCE_IRQ,
  103. },
  104. {
  105. .start = MSM7X30_UART2_PHYS,
  106. .end = MSM7X30_UART2_PHYS + MSM7X30_UART2_SIZE - 1,
  107. .flags = IORESOURCE_MEM,
  108. .name = "uart_resource"
  109. },
  110. };
  111. static struct resource resources_uart3[] = {
  112. {
  113. .start = INT_UART3,
  114. .end = INT_UART3,
  115. .flags = IORESOURCE_IRQ,
  116. },
  117. {
  118. .start = MSM7X30_UART3_PHYS,
  119. .end = MSM7X30_UART3_PHYS + MSM7X30_UART3_SIZE - 1,
  120. .flags = IORESOURCE_MEM,
  121. },
  122. };
  123. struct platform_device msm_device_uart1 = {
  124. .name = "msm_serial",
  125. .id = 0,
  126. .num_resources = ARRAY_SIZE(resources_uart1),
  127. .resource = resources_uart1,
  128. };
  129. struct platform_device msm_device_uart2 = {
  130. .name = "msm_serial",
  131. .id = 1,
  132. .num_resources = ARRAY_SIZE(resources_uart2),
  133. .resource = resources_uart2,
  134. };
  135. struct platform_device msm_device_uart3 = {
  136. .name = "msm_serial",
  137. .id = 2,
  138. .num_resources = ARRAY_SIZE(resources_uart3),
  139. .resource = resources_uart3,
  140. };
  141. #define MSM_UART1DM_PHYS 0xA3300000
  142. #define MSM_UART2DM_PHYS 0xA3200000
  143. static struct resource msm_uart1_dm_resources[] = {
  144. {
  145. .start = MSM_UART1DM_PHYS,
  146. .end = MSM_UART1DM_PHYS + PAGE_SIZE - 1,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. {
  150. .start = INT_UART1DM_IRQ,
  151. .end = INT_UART1DM_IRQ,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. {
  155. .start = INT_UART1DM_RX,
  156. .end = INT_UART1DM_RX,
  157. .flags = IORESOURCE_IRQ,
  158. },
  159. {
  160. .start = DMOV_HSUART1_TX_CHAN,
  161. .end = DMOV_HSUART1_RX_CHAN,
  162. .name = "uartdm_channels",
  163. .flags = IORESOURCE_DMA,
  164. },
  165. {
  166. .start = DMOV_HSUART1_TX_CRCI,
  167. .end = DMOV_HSUART1_RX_CRCI,
  168. .name = "uartdm_crci",
  169. .flags = IORESOURCE_DMA,
  170. },
  171. };
  172. static u64 msm_uart_dm1_dma_mask = DMA_BIT_MASK(32);
  173. struct platform_device msm_device_uart_dm1 = {
  174. .name = "msm_serial_hs",
  175. .id = 0,
  176. .num_resources = ARRAY_SIZE(msm_uart1_dm_resources),
  177. .resource = msm_uart1_dm_resources,
  178. .dev = {
  179. .dma_mask = &msm_uart_dm1_dma_mask,
  180. .coherent_dma_mask = DMA_BIT_MASK(32),
  181. },
  182. };
  183. static struct resource msm_uart2_dm_resources[] = {
  184. {
  185. .start = MSM_UART2DM_PHYS,
  186. .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
  187. .flags = IORESOURCE_MEM,
  188. },
  189. {
  190. .start = INT_UART2DM_IRQ,
  191. .end = INT_UART2DM_IRQ,
  192. .flags = IORESOURCE_IRQ,
  193. },
  194. {
  195. .start = INT_UART2DM_RX,
  196. .end = INT_UART2DM_RX,
  197. .flags = IORESOURCE_IRQ,
  198. },
  199. {
  200. .start = DMOV_HSUART2_TX_CHAN,
  201. .end = DMOV_HSUART2_RX_CHAN,
  202. .name = "uartdm_channels",
  203. .flags = IORESOURCE_DMA,
  204. },
  205. {
  206. .start = DMOV_HSUART2_TX_CRCI,
  207. .end = DMOV_HSUART2_RX_CRCI,
  208. .name = "uartdm_crci",
  209. .flags = IORESOURCE_DMA,
  210. },
  211. };
  212. static u64 msm_uart_dm2_dma_mask = DMA_BIT_MASK(32);
  213. struct platform_device msm_device_uart_dm2 = {
  214. .name = "msm_serial_hs",
  215. .id = 1,
  216. .num_resources = ARRAY_SIZE(msm_uart2_dm_resources),
  217. .resource = msm_uart2_dm_resources,
  218. .dev = {
  219. .dma_mask = &msm_uart_dm2_dma_mask,
  220. .coherent_dma_mask = DMA_BIT_MASK(32),
  221. },
  222. };
  223. #define MSM_I2C_SIZE SZ_4K
  224. #define MSM_I2C_PHYS 0xACD00000
  225. #define MSM_I2C_2_PHYS 0xACF00000
  226. static struct resource resources_i2c_2[] = {
  227. {
  228. .start = MSM_I2C_2_PHYS,
  229. .end = MSM_I2C_2_PHYS + MSM_I2C_SIZE - 1,
  230. .flags = IORESOURCE_MEM,
  231. },
  232. {
  233. .start = INT_PWB_I2C_2,
  234. .end = INT_PWB_I2C_2,
  235. .flags = IORESOURCE_IRQ,
  236. },
  237. };
  238. struct platform_device msm_device_i2c_2 = {
  239. .name = "msm_i2c",
  240. .id = 2,
  241. .num_resources = ARRAY_SIZE(resources_i2c_2),
  242. .resource = resources_i2c_2,
  243. };
  244. static struct resource resources_i2c[] = {
  245. {
  246. .start = MSM_I2C_PHYS,
  247. .end = MSM_I2C_PHYS + MSM_I2C_SIZE - 1,
  248. .flags = IORESOURCE_MEM,
  249. },
  250. {
  251. .start = INT_PWB_I2C,
  252. .end = INT_PWB_I2C,
  253. .flags = IORESOURCE_IRQ,
  254. },
  255. };
  256. struct platform_device msm_device_i2c = {
  257. .name = "msm_i2c",
  258. .id = 0,
  259. .num_resources = ARRAY_SIZE(resources_i2c),
  260. .resource = resources_i2c,
  261. };
  262. #ifdef CONFIG_MSM_CAMERA_V4L2
  263. static struct resource msm_csic_resources[] = {
  264. {
  265. .name = "csic",
  266. .start = 0xA6100000,
  267. .end = 0xA6100000 + 0x00000400 - 1,
  268. .flags = IORESOURCE_MEM,
  269. },
  270. {
  271. .name = "csic",
  272. .start = INT_CSI,
  273. .end = INT_CSI,
  274. .flags = IORESOURCE_IRQ,
  275. },
  276. };
  277. struct resource msm_vfe_resources[] = {
  278. {
  279. .name = "msm_vfe",
  280. .start = 0xA6000000,
  281. .end = 0xA6000000 + SZ_1M - 1,
  282. .flags = IORESOURCE_MEM,
  283. },
  284. {
  285. .name = "msm_vfe",
  286. .start = INT_VFE,
  287. .end = INT_VFE,
  288. .flags = IORESOURCE_IRQ,
  289. },
  290. {
  291. .name = "msm_camif",
  292. .start = 0xAB000000,
  293. .end = 0xAB000000 + SZ_1K - 1,
  294. .flags = IORESOURCE_MEM,
  295. },
  296. };
  297. static struct resource msm_vpe_resources[] = {
  298. {
  299. .name = "vpe",
  300. .start = 0xAD200000,
  301. .end = 0xAD200000 + SZ_1M - 1,
  302. .flags = IORESOURCE_MEM,
  303. },
  304. {
  305. .name = "vpe",
  306. .start = INT_VPE,
  307. .end = INT_VPE,
  308. .flags = IORESOURCE_IRQ,
  309. },
  310. };
  311. struct platform_device msm_device_csic0 = {
  312. .name = "msm_csic",
  313. .id = 0,
  314. .resource = msm_csic_resources,
  315. .num_resources = ARRAY_SIZE(msm_csic_resources),
  316. };
  317. struct platform_device msm_device_vfe = {
  318. .name = "msm_vfe",
  319. .id = 0,
  320. .resource = msm_vfe_resources,
  321. .num_resources = ARRAY_SIZE(msm_vfe_resources),
  322. };
  323. struct platform_device msm_device_vpe = {
  324. .name = "msm_vpe",
  325. .id = 0,
  326. .resource = msm_vpe_resources,
  327. .num_resources = ARRAY_SIZE(msm_vpe_resources),
  328. };
  329. #endif
  330. #define MSM_QUP_PHYS 0xA8301000
  331. #define MSM_GSBI_QUP_I2C_PHYS 0xA8300000
  332. #define MSM_QUP_SIZE SZ_4K
  333. static struct resource resources_qup[] = {
  334. {
  335. .name = "qup_phys_addr",
  336. .start = MSM_QUP_PHYS,
  337. .end = MSM_QUP_PHYS + MSM_QUP_SIZE - 1,
  338. .flags = IORESOURCE_MEM,
  339. },
  340. {
  341. .name = "gsbi_qup_i2c_addr",
  342. .start = MSM_GSBI_QUP_I2C_PHYS,
  343. .end = MSM_GSBI_QUP_I2C_PHYS + 4 - 1,
  344. .flags = IORESOURCE_MEM,
  345. },
  346. {
  347. .name = "qup_in_intr",
  348. .start = INT_PWB_QUP_IN,
  349. .end = INT_PWB_QUP_IN,
  350. .flags = IORESOURCE_IRQ,
  351. },
  352. {
  353. .name = "qup_out_intr",
  354. .start = INT_PWB_QUP_OUT,
  355. .end = INT_PWB_QUP_OUT,
  356. .flags = IORESOURCE_IRQ,
  357. },
  358. {
  359. .name = "qup_err_intr",
  360. .start = INT_PWB_QUP_ERR,
  361. .end = INT_PWB_QUP_ERR,
  362. .flags = IORESOURCE_IRQ,
  363. },
  364. };
  365. struct platform_device qup_device_i2c = {
  366. .name = "qup_i2c",
  367. .id = 4,
  368. .num_resources = ARRAY_SIZE(resources_qup),
  369. .resource = resources_qup,
  370. };
  371. #ifdef CONFIG_MSM_SSBI
  372. #define MSM_SSBI_PMIC1_PHYS 0xAD900000
  373. static struct resource msm_ssbi_pmic1_resources[] = {
  374. {
  375. .start = MSM_SSBI_PMIC1_PHYS,
  376. .end = MSM_SSBI_PMIC1_PHYS + SZ_4K - 1,
  377. .flags = IORESOURCE_MEM,
  378. },
  379. };
  380. struct platform_device msm_device_ssbi_pmic1 = {
  381. .name = "msm_ssbi",
  382. .id = 0,
  383. .resource = msm_ssbi_pmic1_resources,
  384. .num_resources = ARRAY_SIZE(msm_ssbi_pmic1_resources),
  385. };
  386. #endif
  387. #ifdef CONFIG_I2C_SSBI
  388. #define MSM_SSBI7_PHYS 0xAC800000
  389. static struct resource msm_ssbi7_resources[] = {
  390. {
  391. .name = "ssbi_base",
  392. .start = MSM_SSBI7_PHYS,
  393. .end = MSM_SSBI7_PHYS + SZ_4K - 1,
  394. .flags = IORESOURCE_MEM,
  395. },
  396. };
  397. struct platform_device msm_device_ssbi7 = {
  398. .name = "i2c_ssbi",
  399. .id = 7,
  400. .num_resources = ARRAY_SIZE(msm_ssbi7_resources),
  401. .resource = msm_ssbi7_resources,
  402. };
  403. #endif /* CONFIG_I2C_SSBI */
  404. #define MSM_HSUSB_PHYS 0xA3600000
  405. static struct resource resources_hsusb_otg[] = {
  406. {
  407. .start = MSM_HSUSB_PHYS,
  408. .end = MSM_HSUSB_PHYS + SZ_1K - 1,
  409. .flags = IORESOURCE_MEM,
  410. },
  411. {
  412. .start = INT_USB_HS,
  413. .end = INT_USB_HS,
  414. .flags = IORESOURCE_IRQ,
  415. },
  416. };
  417. static u64 dma_mask = 0xffffffffULL;
  418. struct platform_device msm_device_hsusb_otg = {
  419. .name = "msm_hsusb_otg",
  420. .id = -1,
  421. .num_resources = ARRAY_SIZE(resources_hsusb_otg),
  422. .resource = resources_hsusb_otg,
  423. .dev = {
  424. .dma_mask = &dma_mask,
  425. .coherent_dma_mask = 0xffffffffULL,
  426. },
  427. };
  428. static struct resource resources_hsusb_peripheral[] = {
  429. {
  430. .start = MSM_HSUSB_PHYS,
  431. .end = MSM_HSUSB_PHYS + SZ_1K - 1,
  432. .flags = IORESOURCE_MEM,
  433. },
  434. {
  435. .start = INT_USB_HS,
  436. .end = INT_USB_HS,
  437. .flags = IORESOURCE_IRQ,
  438. },
  439. };
  440. static struct resource resources_gadget_peripheral[] = {
  441. {
  442. .start = MSM_HSUSB_PHYS,
  443. .end = MSM_HSUSB_PHYS + SZ_1K - 1,
  444. .flags = IORESOURCE_MEM,
  445. },
  446. {
  447. .start = INT_USB_HS,
  448. .end = INT_USB_HS,
  449. .flags = IORESOURCE_IRQ,
  450. },
  451. };
  452. struct platform_device msm_device_hsusb_peripheral = {
  453. .name = "msm_hsusb_peripheral",
  454. .id = -1,
  455. .num_resources = ARRAY_SIZE(resources_hsusb_peripheral),
  456. .resource = resources_hsusb_peripheral,
  457. .dev = {
  458. .dma_mask = &dma_mask,
  459. .coherent_dma_mask = 0xffffffffULL,
  460. },
  461. };
  462. struct platform_device msm_device_gadget_peripheral = {
  463. .name = "msm_hsusb",
  464. .id = -1,
  465. .num_resources = ARRAY_SIZE(resources_gadget_peripheral),
  466. .resource = resources_gadget_peripheral,
  467. .dev = {
  468. .dma_mask = &dma_mask,
  469. .coherent_dma_mask = 0xffffffffULL,
  470. },
  471. };
  472. static struct resource resources_hsusb_host[] = {
  473. {
  474. .start = MSM_HSUSB_PHYS,
  475. .end = MSM_HSUSB_PHYS + SZ_1K - 1,
  476. .flags = IORESOURCE_MEM,
  477. },
  478. {
  479. .start = INT_USB_HS,
  480. .end = INT_USB_HS,
  481. .flags = IORESOURCE_IRQ,
  482. },
  483. };
  484. struct platform_device msm_device_hsusb_host = {
  485. .name = "msm_hsusb_host",
  486. .id = 0,
  487. .num_resources = ARRAY_SIZE(resources_hsusb_host),
  488. .resource = resources_hsusb_host,
  489. .dev = {
  490. .dma_mask = &dma_mask,
  491. .coherent_dma_mask = 0xffffffffULL,
  492. },
  493. };
  494. static struct platform_device *msm_host_devices[] = {
  495. &msm_device_hsusb_host,
  496. };
  497. int msm_add_host(unsigned int host, struct msm_usb_host_platform_data *plat)
  498. {
  499. struct platform_device *pdev;
  500. pdev = msm_host_devices[host];
  501. if (!pdev)
  502. return -ENODEV;
  503. pdev->dev.platform_data = plat;
  504. return platform_device_register(pdev);
  505. }
  506. struct platform_device asoc_msm_pcm = {
  507. .name = "msm-dsp-audio",
  508. .id = 0,
  509. };
  510. struct platform_device asoc_msm_dai0 = {
  511. .name = "msm-codec-dai",
  512. .id = 0,
  513. };
  514. struct platform_device asoc_msm_dai1 = {
  515. .name = "msm-cpu-dai",
  516. .id = 0,
  517. };
  518. #if defined (CONFIG_SND_MSM_MVS_DAI_SOC)
  519. struct platform_device asoc_msm_mvs = {
  520. .name = "msm-mvs-audio",
  521. .id = 0,
  522. };
  523. struct platform_device asoc_mvs_dai0 = {
  524. .name = "mvs-codec-dai",
  525. .id = 0,
  526. };
  527. struct platform_device asoc_mvs_dai1 = {
  528. .name = "mvs-cpu-dai",
  529. .id = 0,
  530. };
  531. #endif
  532. #define MSM_NAND_PHYS 0xA0200000
  533. #define MSM_NANDC01_PHYS 0xA0240000
  534. #define MSM_NANDC10_PHYS 0xA0280000
  535. #define MSM_NANDC11_PHYS 0xA02C0000
  536. #define EBI2_REG_BASE 0xA0000000
  537. static struct resource resources_nand[] = {
  538. [0] = {
  539. .name = "msm_nand_dmac",
  540. .start = DMOV_NAND_CHAN,
  541. .end = DMOV_NAND_CHAN,
  542. .flags = IORESOURCE_DMA,
  543. },
  544. [1] = {
  545. .name = "msm_nand_phys",
  546. .start = MSM_NAND_PHYS,
  547. .end = MSM_NAND_PHYS + 0x7FF,
  548. .flags = IORESOURCE_MEM,
  549. },
  550. [2] = {
  551. .name = "msm_nandc01_phys",
  552. .start = MSM_NANDC01_PHYS,
  553. .end = MSM_NANDC01_PHYS + 0x7FF,
  554. .flags = IORESOURCE_MEM,
  555. },
  556. [3] = {
  557. .name = "msm_nandc10_phys",
  558. .start = MSM_NANDC10_PHYS,
  559. .end = MSM_NANDC10_PHYS + 0x7FF,
  560. .flags = IORESOURCE_MEM,
  561. },
  562. [4] = {
  563. .name = "msm_nandc11_phys",
  564. .start = MSM_NANDC11_PHYS,
  565. .end = MSM_NANDC11_PHYS + 0x7FF,
  566. .flags = IORESOURCE_MEM,
  567. },
  568. [5] = {
  569. .name = "ebi2_reg_base",
  570. .start = EBI2_REG_BASE,
  571. .end = EBI2_REG_BASE + 0x60,
  572. .flags = IORESOURCE_MEM,
  573. },
  574. };
  575. static struct resource resources_otg[] = {
  576. {
  577. .start = MSM_HSUSB_PHYS,
  578. .end = MSM_HSUSB_PHYS + SZ_1K - 1,
  579. .flags = IORESOURCE_MEM,
  580. },
  581. {
  582. .start = INT_USB_HS,
  583. .end = INT_USB_HS,
  584. .flags = IORESOURCE_IRQ,
  585. },
  586. {
  587. .name = "vbus_on",
  588. .start = PMIC8058_IRQ_BASE + PM8058_CHGVAL_IRQ,
  589. .end = PMIC8058_IRQ_BASE + PM8058_CHGVAL_IRQ,
  590. .flags = IORESOURCE_IRQ,
  591. },
  592. };
  593. struct platform_device msm_device_otg = {
  594. .name = "msm_otg",
  595. .id = -1,
  596. .num_resources = ARRAY_SIZE(resources_otg),
  597. .resource = resources_otg,
  598. .dev = {
  599. .coherent_dma_mask = 0xffffffffULL,
  600. },
  601. };
  602. struct flash_platform_data msm_nand_data = {
  603. .version = VERSION_2,
  604. };
  605. struct platform_device msm_device_nand = {
  606. .name = "msm_nand",
  607. .id = -1,
  608. .num_resources = ARRAY_SIZE(resources_nand),
  609. .resource = resources_nand,
  610. .dev = {
  611. .platform_data = &msm_nand_data,
  612. },
  613. };
  614. static struct msm_pm_irq_calls msm7x30_pm_irq_calls = {
  615. .irq_pending = msm_irq_pending,
  616. .idle_sleep_allowed = msm_irq_idle_sleep_allowed,
  617. .enter_sleep1 = msm_irq_enter_sleep1,
  618. .enter_sleep2 = msm_irq_enter_sleep2,
  619. .exit_sleep1 = msm_irq_exit_sleep1,
  620. .exit_sleep2 = msm_irq_exit_sleep2,
  621. .exit_sleep3 = msm_irq_exit_sleep3,
  622. };
  623. void __init msm_pm_register_irqs(void)
  624. {
  625. msm_pm_set_irq_extns(&msm7x30_pm_irq_calls);
  626. }
  627. static struct resource smd_resource[] = {
  628. {
  629. .name = "a9_m2a_0",
  630. .start = INT_A9_M2A_0,
  631. .flags = IORESOURCE_IRQ,
  632. },
  633. {
  634. .name = "a9_m2a_5",
  635. .start = INT_A9_M2A_5,
  636. .flags = IORESOURCE_IRQ,
  637. },
  638. {
  639. .name = "adsp_a11_smsm",
  640. .start = INT_ADSP_A11,
  641. .flags = IORESOURCE_IRQ,
  642. },
  643. };
  644. static struct smd_subsystem_config smd_config_list[] = {
  645. {
  646. .irq_config_id = SMD_MODEM,
  647. .subsys_name = "modem",
  648. .edge = SMD_APPS_MODEM,
  649. .smd_int.irq_name = "a9_m2a_0",
  650. .smd_int.flags = IRQF_TRIGGER_RISING,
  651. .smd_int.irq_id = -1,
  652. .smd_int.device_name = "smd_dev",
  653. .smd_int.dev_id = 0,
  654. .smd_int.out_bit_pos = 1 << 0,
  655. .smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
  656. .smd_int.out_offset = 0x8,
  657. .smsm_int.irq_name = "a9_m2a_5",
  658. .smsm_int.flags = IRQF_TRIGGER_RISING,
  659. .smsm_int.irq_id = -1,
  660. .smsm_int.device_name = "smd_dev",
  661. .smsm_int.dev_id = 0,
  662. .smsm_int.out_bit_pos = 1 << 5,
  663. .smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
  664. .smsm_int.out_offset = 0x8,
  665. }
  666. };
  667. static struct smd_platform smd_platform_data = {
  668. .num_ss_configs = ARRAY_SIZE(smd_config_list),
  669. .smd_ss_configs = smd_config_list,
  670. };
  671. struct platform_device msm_device_smd = {
  672. .name = "msm_smd",
  673. .id = -1,
  674. .resource = smd_resource,
  675. .num_resources = ARRAY_SIZE(smd_resource),
  676. .dev = {
  677. .platform_data = &smd_platform_data,
  678. }
  679. };
  680. static struct resource msm_dmov_resource[] = {
  681. {
  682. .start = INT_ADM_AARM,
  683. .flags = IORESOURCE_IRQ,
  684. },
  685. {
  686. .start = 0xAC400000,
  687. .end = 0xAC400000 + SZ_4K - 1,
  688. .flags = IORESOURCE_MEM,
  689. },
  690. };
  691. static struct msm_dmov_pdata msm_dmov_pdata = {
  692. .sd = 2,
  693. .sd_size = 0x400,
  694. };
  695. struct platform_device msm_device_dmov = {
  696. .name = "msm_dmov",
  697. .id = -1,
  698. .resource = msm_dmov_resource,
  699. .num_resources = ARRAY_SIZE(msm_dmov_resource),
  700. .dev = {
  701. .platform_data = &msm_dmov_pdata,
  702. },
  703. };
  704. #define MSM_SDC1_BASE 0xA0400000
  705. #define MSM_SDC2_BASE 0xA0500000
  706. #define MSM_SDC3_BASE 0xA3000000
  707. #define MSM_SDC4_BASE 0xA3100000
  708. static struct resource resources_sdc1[] = {
  709. {
  710. .name = "core_mem",
  711. .start = MSM_SDC1_BASE,
  712. .end = MSM_SDC1_BASE + SZ_4K - 1,
  713. .flags = IORESOURCE_MEM,
  714. },
  715. {
  716. .name = "core_irq",
  717. .start = INT_SDC1_0,
  718. .end = INT_SDC1_1,
  719. .flags = IORESOURCE_IRQ,
  720. },
  721. {
  722. .name = "dma_chnl",
  723. .start = DMOV_SDC1_CHAN,
  724. .end = DMOV_SDC1_CHAN,
  725. .flags = IORESOURCE_DMA,
  726. },
  727. {
  728. .name = "dma_crci",
  729. .start = DMOV_SDC1_CRCI,
  730. .end = DMOV_SDC1_CRCI,
  731. .flags = IORESOURCE_DMA,
  732. }
  733. };
  734. static struct resource resources_sdc2[] = {
  735. {
  736. .name = "core_mem",
  737. .start = MSM_SDC2_BASE,
  738. .end = MSM_SDC2_BASE + SZ_4K - 1,
  739. .flags = IORESOURCE_MEM,
  740. },
  741. {
  742. .name = "core_irq",
  743. .start = INT_SDC2_0,
  744. .end = INT_SDC2_1,
  745. .flags = IORESOURCE_IRQ,
  746. },
  747. {
  748. .name = "dma_chnl",
  749. .start = DMOV_NAND_CHAN,
  750. .end = DMOV_NAND_CHAN,
  751. .flags = IORESOURCE_DMA,
  752. },
  753. {
  754. .name = "dma_crci",
  755. .start = DMOV_SDC2_CRCI,
  756. .end = DMOV_SDC2_CRCI,
  757. .flags = IORESOURCE_DMA,
  758. }
  759. };
  760. static struct resource resources_sdc3[] = {
  761. {
  762. .name = "core_mem",
  763. .start = MSM_SDC3_BASE,
  764. .end = MSM_SDC3_BASE + SZ_4K - 1,
  765. .flags = IORESOURCE_MEM,
  766. },
  767. {
  768. .name = "core_irq",
  769. .start = INT_SDC3_0,
  770. .end = INT_SDC3_1,
  771. .flags = IORESOURCE_IRQ,
  772. },
  773. {
  774. .name = "dma_chnl",
  775. .start = DMOV_SDC3_CHAN,
  776. .end = DMOV_SDC3_CHAN,
  777. .flags = IORESOURCE_DMA,
  778. },
  779. {
  780. .name = "dma_crci",
  781. .start = DMOV_SDC3_CRCI,
  782. .end = DMOV_SDC3_CRCI,
  783. .flags = IORESOURCE_DMA,
  784. },
  785. };
  786. static struct resource resources_sdc4[] = {
  787. {
  788. .name = "core_mem",
  789. .start = MSM_SDC4_BASE,
  790. .end = MSM_SDC4_BASE + SZ_4K - 1,
  791. .flags = IORESOURCE_MEM,
  792. },
  793. {
  794. .name = "core_irq",
  795. .start = INT_SDC4_0,
  796. .end = INT_SDC4_1,
  797. .flags = IORESOURCE_IRQ,
  798. },
  799. {
  800. .name = "dma_chnl",
  801. .start = DMOV_SDC4_CHAN,
  802. .end = DMOV_SDC4_CHAN,
  803. .flags = IORESOURCE_DMA,
  804. },
  805. {
  806. .name = "dma_crci",
  807. .start = DMOV_SDC4_CRCI,
  808. .end = DMOV_SDC4_CRCI,
  809. .flags = IORESOURCE_DMA,
  810. },
  811. };
  812. struct platform_device msm_device_sdc1 = {
  813. .name = "msm_sdcc",
  814. .id = 1,
  815. .num_resources = ARRAY_SIZE(resources_sdc1),
  816. .resource = resources_sdc1,
  817. .dev = {
  818. .coherent_dma_mask = 0xffffffff,
  819. },
  820. };
  821. struct platform_device msm_device_sdc2 = {
  822. .name = "msm_sdcc",
  823. .id = 2,
  824. .num_resources = ARRAY_SIZE(resources_sdc2),
  825. .resource = resources_sdc2,
  826. .dev = {
  827. .coherent_dma_mask = 0xffffffff,
  828. },
  829. };
  830. struct platform_device msm_device_sdc3 = {
  831. .name = "msm_sdcc",
  832. .id = 3,
  833. .num_resources = ARRAY_SIZE(resources_sdc3),
  834. .resource = resources_sdc3,
  835. .dev = {
  836. .coherent_dma_mask = 0xffffffff,
  837. },
  838. };
  839. struct platform_device msm_device_sdc4 = {
  840. .name = "msm_sdcc",
  841. .id = 4,
  842. .num_resources = ARRAY_SIZE(resources_sdc4),
  843. .resource = resources_sdc4,
  844. .dev = {
  845. .coherent_dma_mask = 0xffffffff,
  846. },
  847. };
  848. static struct platform_device *msm_sdcc_devices[] __initdata = {
  849. &msm_device_sdc1,
  850. &msm_device_sdc2,
  851. &msm_device_sdc3,
  852. &msm_device_sdc4,
  853. };
  854. int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat)
  855. {
  856. struct platform_device *pdev;
  857. if (controller < 1 || controller > 4)
  858. return -EINVAL;
  859. pdev = msm_sdcc_devices[controller-1];
  860. pdev->dev.platform_data = plat;
  861. return platform_device_register(pdev);
  862. }
  863. static struct resource msm_vidc_720p_resources[] = {
  864. {
  865. .start = 0xA3B00000,
  866. .end = 0xA3B00000 + SZ_4K - 1,
  867. .flags = IORESOURCE_MEM,
  868. },
  869. {
  870. .start = INT_MFC720,
  871. .end = INT_MFC720,
  872. .flags = IORESOURCE_IRQ,
  873. },
  874. };
  875. struct msm_vidc_platform_data vidc_platform_data = {
  876. .memtype = ION_CAMERA_HEAP_ID,
  877. .enable_ion = 1,
  878. .disable_dmx = 0,
  879. .cont_mode_dpb_count = 8
  880. };
  881. struct platform_device msm_device_vidc_720p = {
  882. .name = "msm_vidc",
  883. .id = 0,
  884. .num_resources = ARRAY_SIZE(msm_vidc_720p_resources),
  885. .resource = msm_vidc_720p_resources,
  886. .dev = {
  887. .platform_data = &vidc_platform_data,
  888. },
  889. };
  890. #if defined(CONFIG_FB_MSM_MDP40)
  891. #define MDP_BASE 0xA3F00000
  892. #define PMDH_BASE 0xAD600000
  893. #define EMDH_BASE 0xAD700000
  894. #define TVENC_BASE 0xAD400000
  895. #else
  896. #define MDP_BASE 0xAA200000
  897. #define PMDH_BASE 0xAA600000
  898. #define EMDH_BASE 0xAA700000
  899. #define TVENC_BASE 0xAA400000
  900. #endif
  901. static struct resource msm_mdp_resources[] = {
  902. {
  903. .name = "mdp",
  904. .start = MDP_BASE,
  905. .end = MDP_BASE + 0x000F0000 - 1,
  906. .flags = IORESOURCE_MEM,
  907. },
  908. {
  909. .start = INT_MDP,
  910. .end = INT_MDP,
  911. .flags = IORESOURCE_IRQ,
  912. },
  913. };
  914. static struct resource msm_mddi_resources[] = {
  915. {
  916. .name = "pmdh",
  917. .start = PMDH_BASE,
  918. .end = PMDH_BASE + PAGE_SIZE - 1,
  919. .flags = IORESOURCE_MEM,
  920. }
  921. };
  922. static struct resource msm_mddi_ext_resources[] = {
  923. {
  924. .name = "emdh",
  925. .start = EMDH_BASE,
  926. .end = EMDH_BASE + PAGE_SIZE - 1,
  927. .flags = IORESOURCE_MEM,
  928. }
  929. };
  930. static struct resource msm_ebi2_lcd_resources[] = {
  931. {
  932. .name = "base",
  933. .start = 0xa0d00000,
  934. .end = 0xa0d00000 + PAGE_SIZE - 1,
  935. .flags = IORESOURCE_MEM,
  936. },
  937. {
  938. .name = "lcd01",
  939. .start = 0x98000000,
  940. .end = 0x98000000 + 0x80000 - 1,
  941. .flags = IORESOURCE_MEM,
  942. },
  943. {
  944. .name = "lcd02",
  945. .start = 0x9c000000,
  946. .end = 0x9c000000 + 0x80000 - 1,
  947. .flags = IORESOURCE_MEM,
  948. },
  949. };
  950. static struct resource msm_tvenc_resources[] = {
  951. {
  952. .name = "tvenc",
  953. .start = TVENC_BASE,
  954. .end = TVENC_BASE + PAGE_SIZE - 1,
  955. .flags = IORESOURCE_MEM,
  956. }
  957. };
  958. #ifdef CONFIG_FB_MSM_TVOUT
  959. static struct resource tvout_device_resources[] = {
  960. {
  961. .name = "tvout_device_irq",
  962. .start = INT_TV_ENC,
  963. .end = INT_TV_ENC,
  964. .flags = IORESOURCE_IRQ,
  965. },
  966. };
  967. #endif
  968. static struct platform_device msm_mdp_device = {
  969. .name = "mdp",
  970. .id = 0,
  971. .num_resources = ARRAY_SIZE(msm_mdp_resources),
  972. .resource = msm_mdp_resources,
  973. };
  974. static struct platform_device msm_mddi_device = {
  975. .name = "mddi",
  976. .id = 0,
  977. .num_resources = ARRAY_SIZE(msm_mddi_resources),
  978. .resource = msm_mddi_resources,
  979. };
  980. static struct platform_device msm_mddi_ext_device = {
  981. .name = "mddi_ext",
  982. .id = 0,
  983. .num_resources = ARRAY_SIZE(msm_mddi_ext_resources),
  984. .resource = msm_mddi_ext_resources,
  985. };
  986. static struct platform_device msm_ebi2_lcd_device = {
  987. .name = "ebi2_lcd",
  988. .id = 0,
  989. .num_resources = ARRAY_SIZE(msm_ebi2_lcd_resources),
  990. .resource = msm_ebi2_lcd_resources,
  991. };
  992. struct platform_device msm_lcdc_device = {
  993. .name = "lcdc",
  994. .id = 0,
  995. };
  996. static struct platform_device msm_dtv_device = {
  997. .name = "dtv",
  998. .id = 0,
  999. };
  1000. static struct platform_device msm_tvenc_device = {
  1001. .name = "tvenc",
  1002. .id = 0,
  1003. .num_resources = ARRAY_SIZE(msm_tvenc_resources),
  1004. .resource = msm_tvenc_resources,
  1005. };
  1006. #ifdef CONFIG_FB_MSM_TVOUT
  1007. static struct platform_device tvout_msm_device = {
  1008. .name = "tvout_device",
  1009. .id = 0,
  1010. .num_resources = ARRAY_SIZE(tvout_device_resources),
  1011. .resource = tvout_device_resources,
  1012. };
  1013. #endif
  1014. /* TSIF begin */
  1015. #if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
  1016. #define MSM_TSIF_PHYS (0xa3400000)
  1017. #define MSM_TSIF_SIZE (0x200)
  1018. static struct resource tsif_resources[] = {
  1019. [0] = {
  1020. .flags = IORESOURCE_IRQ,
  1021. .start = INT_TSIF,
  1022. .end = INT_TSIF,
  1023. },
  1024. [1] = {
  1025. .flags = IORESOURCE_MEM,
  1026. .start = MSM_TSIF_PHYS,
  1027. .end = MSM_TSIF_PHYS + MSM_TSIF_SIZE - 1,
  1028. },
  1029. [2] = {
  1030. .flags = IORESOURCE_DMA,
  1031. .start = DMOV_TSIF_CHAN,
  1032. .end = DMOV_TSIF_CRCI,
  1033. },
  1034. };
  1035. static void tsif_release(struct device *dev)
  1036. {
  1037. dev_info(dev, "release\n");
  1038. }
  1039. struct platform_device msm_device_tsif = {
  1040. .name = "msm_tsif",
  1041. .id = 0,
  1042. .num_resources = ARRAY_SIZE(tsif_resources),
  1043. .resource = tsif_resources,
  1044. .dev = {
  1045. .release = tsif_release,
  1046. },
  1047. };
  1048. #endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */
  1049. /* TSIF end */
  1050. #ifdef CONFIG_MSM_ROTATOR
  1051. static struct resource resources_msm_rotator[] = {
  1052. {
  1053. .start = 0xA3E00000,
  1054. .end = 0xA3F00000 - 1,
  1055. .flags = IORESOURCE_MEM,
  1056. },
  1057. {
  1058. .start = INT_ROTATOR,
  1059. .end = INT_ROTATOR,
  1060. .flags = IORESOURCE_IRQ,
  1061. },
  1062. };
  1063. static struct msm_rot_clocks rotator_clocks[] = {
  1064. {
  1065. .clk_name = "core_clk",
  1066. .clk_type = ROTATOR_CORE_CLK,
  1067. .clk_rate = 0,
  1068. },
  1069. {
  1070. .clk_name = "iface_clk",
  1071. .clk_type = ROTATOR_PCLK,
  1072. .clk_rate = 0,
  1073. },
  1074. {
  1075. .clk_name = "mem_clk",
  1076. .clk_type = ROTATOR_IMEM_CLK,
  1077. .clk_rate = 0,
  1078. },
  1079. };
  1080. static struct msm_rotator_platform_data rotator_pdata = {
  1081. .number_of_clocks = ARRAY_SIZE(rotator_clocks),
  1082. .hardware_version_number = 0x1000303,
  1083. .rotator_clks = rotator_clocks,
  1084. };
  1085. struct platform_device msm_rotator_device = {
  1086. .name = "msm_rotator",
  1087. .id = 0,
  1088. .num_resources = ARRAY_SIZE(resources_msm_rotator),
  1089. .resource = resources_msm_rotator,
  1090. .dev = {
  1091. .platform_data = &rotator_pdata,
  1092. },
  1093. };
  1094. #endif
  1095. static void __init msm_register_device(struct platform_device *pdev, void *data)
  1096. {
  1097. int ret;
  1098. pdev->dev.platform_data = data;
  1099. ret = platform_device_register(pdev);
  1100. if (ret)
  1101. dev_err(&pdev->dev,
  1102. "%s: platform_device_register() failed = %d\n",
  1103. __func__, ret);
  1104. }
  1105. void __init msm_fb_register_device(char *name, void *data)
  1106. {
  1107. if (!strncmp(name, "mdp", 3))
  1108. msm_register_device(&msm_mdp_device, data);
  1109. else if (!strncmp(name, "pmdh", 4))
  1110. msm_register_device(&msm_mddi_device, data);
  1111. else if (!strncmp(name, "emdh", 4))
  1112. msm_register_device(&msm_mddi_ext_device, data);
  1113. else if (!strncmp(name, "ebi2", 4))
  1114. msm_register_device(&msm_ebi2_lcd_device, data);
  1115. else if (!strncmp(name, "tvenc", 5))
  1116. msm_register_device(&msm_tvenc_device, data);
  1117. else if (!strncmp(name, "lcdc", 4))
  1118. msm_register_device(&msm_lcdc_device, data);
  1119. else if (!strncmp(name, "dtv", 3))
  1120. msm_register_device(&msm_dtv_device, data);
  1121. #ifdef CONFIG_FB_MSM_TVOUT
  1122. else if (!strncmp(name, "tvout_device", 12))
  1123. msm_register_device(&tvout_msm_device, data);
  1124. #endif
  1125. else
  1126. printk(KERN_ERR "%s: unknown device! %s\n", __func__, name);
  1127. }
  1128. static struct platform_device msm_camera_device = {
  1129. .name = "msm_camera",
  1130. .id = 0,
  1131. };
  1132. void __init msm_camera_register_device(void *res, uint32_t num,
  1133. void *data)
  1134. {
  1135. msm_camera_device.num_resources = num;
  1136. msm_camera_device.resource = res;
  1137. msm_register_device(&msm_camera_device, data);
  1138. }
  1139. struct resource kgsl_3d0_resources[] = {
  1140. {
  1141. .name = KGSL_3D0_REG_MEMORY,
  1142. .start = 0xA3500000, /* 3D GRP address */
  1143. .end = 0xA351ffff,
  1144. .flags = IORESOURCE_MEM,
  1145. },
  1146. {
  1147. .name = KGSL_3D0_IRQ,
  1148. .start = INT_GRP_3D,
  1149. .end = INT_GRP_3D,
  1150. .flags = IORESOURCE_IRQ,
  1151. },
  1152. };
  1153. static struct kgsl_device_platform_data kgsl_3d0_pdata = {
  1154. .pwrlevel = {
  1155. {
  1156. .gpu_freq = 245760000,
  1157. .bus_freq = 192000000,
  1158. },
  1159. {
  1160. .gpu_freq = 192000000,
  1161. .bus_freq = 152000000,
  1162. },
  1163. {
  1164. .gpu_freq = 192000000,
  1165. .bus_freq = 0,
  1166. },
  1167. },
  1168. .init_level = 0,
  1169. .num_levels = 3,
  1170. .set_grp_async = set_grp3d_async,
  1171. .idle_timeout = HZ/20,
  1172. .idle_needed = true,
  1173. .clk_map = KGSL_CLK_SRC | KGSL_CLK_CORE |
  1174. KGSL_CLK_IFACE | KGSL_CLK_MEM,
  1175. };
  1176. struct platform_device msm_kgsl_3d0 = {
  1177. .name = "kgsl-3d0",
  1178. .id = 0,
  1179. .num_resources = ARRAY_SIZE(kgsl_3d0_resources),
  1180. .resource = kgsl_3d0_resources,
  1181. .dev = {
  1182. .platform_data = &kgsl_3d0_pdata,
  1183. },
  1184. };
  1185. static struct resource kgsl_2d0_resources[] = {
  1186. {
  1187. .name = KGSL_2D0_REG_MEMORY,
  1188. .start = 0xA3900000, /* Z180 base address */
  1189. .end = 0xA3900FFF,
  1190. .flags = IORESOURCE_MEM,
  1191. },
  1192. {
  1193. .name = KGSL_2D0_IRQ,
  1194. .start = INT_GRP_2D,
  1195. .end = INT_GRP_2D,
  1196. .flags = IORESOURCE_IRQ,
  1197. },
  1198. };
  1199. static struct kgsl_device_platform_data kgsl_2d0_pdata = {
  1200. .pwrlevel = {
  1201. {
  1202. .gpu_freq = 0,
  1203. .bus_freq = 192000000,
  1204. },
  1205. },
  1206. .init_level = 0,
  1207. .num_levels = 1,
  1208. /* HW workaround, run Z180 SYNC @ 192 MHZ */
  1209. .set_grp_async = NULL,
  1210. .idle_timeout = HZ/10,
  1211. .idle_needed = true,
  1212. .clk_map = KGSL_CLK_CORE | KGSL_CLK_IFACE,
  1213. };
  1214. struct platform_device msm_kgsl_2d0 = {
  1215. .name = "kgsl-2d0",
  1216. .id = 0,
  1217. .num_resources = ARRAY_SIZE(kgsl_2d0_resources),
  1218. .resource = kgsl_2d0_resources,
  1219. .dev = {
  1220. .platform_data = &kgsl_2d0_pdata,
  1221. },
  1222. };
  1223. struct platform_device *msm_footswitch_devices[] = {
  1224. FS_PCOM(FS_GFX2D0, "vdd", "kgsl-2d0.0"),
  1225. FS_PCOM(FS_GFX3D, "vdd", "kgsl-3d0.0"),
  1226. FS_PCOM(FS_MDP, "vdd", "mdp.0"),
  1227. FS_PCOM(FS_MFC, "fs_mfc", NULL),
  1228. FS_PCOM(FS_ROT, "vdd", "msm_rotator.0"),
  1229. FS_PCOM(FS_VFE, "fs_vfe", NULL),
  1230. FS_PCOM(FS_VPE, "fs_vpe", NULL),
  1231. };
  1232. unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
  1233. static struct resource gpio_resources[] = {
  1234. {
  1235. .start = INT_GPIO_GROUP1,
  1236. .flags = IORESOURCE_IRQ,
  1237. },
  1238. {
  1239. .start = INT_GPIO_GROUP2,
  1240. .flags = IORESOURCE_IRQ,
  1241. },
  1242. };
  1243. static struct platform_device msm_device_gpio = {
  1244. .name = "msmgpio",
  1245. .id = -1,
  1246. .resource = gpio_resources,
  1247. .num_resources = ARRAY_SIZE(gpio_resources),
  1248. };
  1249. static int __init msm7630_init_gpio(void)
  1250. {
  1251. platform_device_register(&msm_device_gpio);
  1252. return 0;
  1253. }
  1254. postcore_initcall(msm7630_init_gpio);