cs4231.c 56 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122
  1. /*
  2. * Driver for CS4231 sound chips found on Sparcs.
  3. * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
  4. *
  5. * Based entirely upon drivers/sbus/audio/cs4231.c which is:
  6. * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
  7. * and also sound/isa/cs423x/cs4231_lib.c which is:
  8. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/delay.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/moduleparam.h>
  16. #include <linux/irq.h>
  17. #include <linux/io.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/info.h>
  23. #include <sound/control.h>
  24. #include <sound/timer.h>
  25. #include <sound/initval.h>
  26. #include <sound/pcm_params.h>
  27. #ifdef CONFIG_SBUS
  28. #define SBUS_SUPPORT
  29. #endif
  30. #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
  31. #define EBUS_SUPPORT
  32. #include <linux/pci.h>
  33. #include <asm/ebus_dma.h>
  34. #endif
  35. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  36. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  37. /* Enable this card */
  38. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  39. module_param_array(index, int, NULL, 0444);
  40. MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
  41. module_param_array(id, charp, NULL, 0444);
  42. MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
  43. module_param_array(enable, bool, NULL, 0444);
  44. MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
  45. MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
  46. MODULE_DESCRIPTION("Sun CS4231");
  47. MODULE_LICENSE("GPL");
  48. MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
  49. #ifdef SBUS_SUPPORT
  50. struct sbus_dma_info {
  51. spinlock_t lock; /* DMA access lock */
  52. int dir;
  53. void __iomem *regs;
  54. };
  55. #endif
  56. struct snd_cs4231;
  57. struct cs4231_dma_control {
  58. void (*prepare)(struct cs4231_dma_control *dma_cont,
  59. int dir);
  60. void (*enable)(struct cs4231_dma_control *dma_cont, int on);
  61. int (*request)(struct cs4231_dma_control *dma_cont,
  62. dma_addr_t bus_addr, size_t len);
  63. unsigned int (*address)(struct cs4231_dma_control *dma_cont);
  64. #ifdef EBUS_SUPPORT
  65. struct ebus_dma_info ebus_info;
  66. #endif
  67. #ifdef SBUS_SUPPORT
  68. struct sbus_dma_info sbus_info;
  69. #endif
  70. };
  71. struct snd_cs4231 {
  72. spinlock_t lock; /* registers access lock */
  73. void __iomem *port;
  74. struct cs4231_dma_control p_dma;
  75. struct cs4231_dma_control c_dma;
  76. u32 flags;
  77. #define CS4231_FLAG_EBUS 0x00000001
  78. #define CS4231_FLAG_PLAYBACK 0x00000002
  79. #define CS4231_FLAG_CAPTURE 0x00000004
  80. struct snd_card *card;
  81. struct snd_pcm *pcm;
  82. struct snd_pcm_substream *playback_substream;
  83. unsigned int p_periods_sent;
  84. struct snd_pcm_substream *capture_substream;
  85. unsigned int c_periods_sent;
  86. struct snd_timer *timer;
  87. unsigned short mode;
  88. #define CS4231_MODE_NONE 0x0000
  89. #define CS4231_MODE_PLAY 0x0001
  90. #define CS4231_MODE_RECORD 0x0002
  91. #define CS4231_MODE_TIMER 0x0004
  92. #define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \
  93. CS4231_MODE_TIMER)
  94. unsigned char image[32]; /* registers image */
  95. int mce_bit;
  96. int calibrate_mute;
  97. struct mutex mce_mutex; /* mutex for mce register */
  98. struct mutex open_mutex; /* mutex for ALSA open/close */
  99. struct platform_device *op;
  100. unsigned int irq[2];
  101. unsigned int regs_size;
  102. struct snd_cs4231 *next;
  103. };
  104. /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
  105. * now.... -DaveM
  106. */
  107. /* IO ports */
  108. #include <sound/cs4231-regs.h>
  109. /* XXX offsets are different than PC ISA chips... */
  110. #define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
  111. /* SBUS DMA register defines. */
  112. #define APCCSR 0x10UL /* APC DMA CSR */
  113. #define APCCVA 0x20UL /* APC Capture DMA Address */
  114. #define APCCC 0x24UL /* APC Capture Count */
  115. #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
  116. #define APCCNC 0x2cUL /* APC Capture Next Count */
  117. #define APCPVA 0x30UL /* APC Play DMA Address */
  118. #define APCPC 0x34UL /* APC Play Count */
  119. #define APCPNVA 0x38UL /* APC Play DMA Next Address */
  120. #define APCPNC 0x3cUL /* APC Play Next Count */
  121. /* Defines for SBUS DMA-routines */
  122. #define APCVA 0x0UL /* APC DMA Address */
  123. #define APCC 0x4UL /* APC Count */
  124. #define APCNVA 0x8UL /* APC DMA Next Address */
  125. #define APCNC 0xcUL /* APC Next Count */
  126. #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
  127. #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
  128. /* APCCSR bits */
  129. #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
  130. #define APC_PLAY_INT 0x400000 /* Playback interrupt */
  131. #define APC_CAPT_INT 0x200000 /* Capture interrupt */
  132. #define APC_GENL_INT 0x100000 /* General interrupt */
  133. #define APC_XINT_ENA 0x80000 /* General ext int. enable */
  134. #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
  135. #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
  136. #define APC_XINT_GENL 0x10000 /* Error ext intr */
  137. #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
  138. #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
  139. #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
  140. #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
  141. #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
  142. #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
  143. #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
  144. #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
  145. #define APC_PPAUSE 0x80 /* Pause the play DMA */
  146. #define APC_CPAUSE 0x40 /* Pause the capture DMA */
  147. #define APC_CDC_RESET 0x20 /* CODEC RESET */
  148. #define APC_PDMA_READY 0x08 /* Play DMA Go */
  149. #define APC_CDMA_READY 0x04 /* Capture DMA Go */
  150. #define APC_CHIP_RESET 0x01 /* Reset the chip */
  151. /* EBUS DMA register offsets */
  152. #define EBDMA_CSR 0x00UL /* Control/Status */
  153. #define EBDMA_ADDR 0x04UL /* DMA Address */
  154. #define EBDMA_COUNT 0x08UL /* DMA Count */
  155. /*
  156. * Some variables
  157. */
  158. static unsigned char freq_bits[14] = {
  159. /* 5510 */ 0x00 | CS4231_XTAL2,
  160. /* 6620 */ 0x0E | CS4231_XTAL2,
  161. /* 8000 */ 0x00 | CS4231_XTAL1,
  162. /* 9600 */ 0x0E | CS4231_XTAL1,
  163. /* 11025 */ 0x02 | CS4231_XTAL2,
  164. /* 16000 */ 0x02 | CS4231_XTAL1,
  165. /* 18900 */ 0x04 | CS4231_XTAL2,
  166. /* 22050 */ 0x06 | CS4231_XTAL2,
  167. /* 27042 */ 0x04 | CS4231_XTAL1,
  168. /* 32000 */ 0x06 | CS4231_XTAL1,
  169. /* 33075 */ 0x0C | CS4231_XTAL2,
  170. /* 37800 */ 0x08 | CS4231_XTAL2,
  171. /* 44100 */ 0x0A | CS4231_XTAL2,
  172. /* 48000 */ 0x0C | CS4231_XTAL1
  173. };
  174. static unsigned int rates[14] = {
  175. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  176. 27042, 32000, 33075, 37800, 44100, 48000
  177. };
  178. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  179. .count = ARRAY_SIZE(rates),
  180. .list = rates,
  181. };
  182. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  183. {
  184. return snd_pcm_hw_constraint_list(runtime, 0,
  185. SNDRV_PCM_HW_PARAM_RATE,
  186. &hw_constraints_rates);
  187. }
  188. static unsigned char snd_cs4231_original_image[32] =
  189. {
  190. 0x00, /* 00/00 - lic */
  191. 0x00, /* 01/01 - ric */
  192. 0x9f, /* 02/02 - la1ic */
  193. 0x9f, /* 03/03 - ra1ic */
  194. 0x9f, /* 04/04 - la2ic */
  195. 0x9f, /* 05/05 - ra2ic */
  196. 0xbf, /* 06/06 - loc */
  197. 0xbf, /* 07/07 - roc */
  198. 0x20, /* 08/08 - pdfr */
  199. CS4231_AUTOCALIB, /* 09/09 - ic */
  200. 0x00, /* 0a/10 - pc */
  201. 0x00, /* 0b/11 - ti */
  202. CS4231_MODE2, /* 0c/12 - mi */
  203. 0x00, /* 0d/13 - lbc */
  204. 0x00, /* 0e/14 - pbru */
  205. 0x00, /* 0f/15 - pbrl */
  206. 0x80, /* 10/16 - afei */
  207. 0x01, /* 11/17 - afeii */
  208. 0x9f, /* 12/18 - llic */
  209. 0x9f, /* 13/19 - rlic */
  210. 0x00, /* 14/20 - tlb */
  211. 0x00, /* 15/21 - thb */
  212. 0x00, /* 16/22 - la3mic/reserved */
  213. 0x00, /* 17/23 - ra3mic/reserved */
  214. 0x00, /* 18/24 - afs */
  215. 0x00, /* 19/25 - lamoc/version */
  216. 0x00, /* 1a/26 - mioc */
  217. 0x00, /* 1b/27 - ramoc/reserved */
  218. 0x20, /* 1c/28 - cdfr */
  219. 0x00, /* 1d/29 - res4 */
  220. 0x00, /* 1e/30 - cbru */
  221. 0x00, /* 1f/31 - cbrl */
  222. };
  223. static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
  224. {
  225. if (cp->flags & CS4231_FLAG_EBUS)
  226. return readb(reg_addr);
  227. else
  228. return sbus_readb(reg_addr);
  229. }
  230. static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val,
  231. void __iomem *reg_addr)
  232. {
  233. if (cp->flags & CS4231_FLAG_EBUS)
  234. return writeb(val, reg_addr);
  235. else
  236. return sbus_writeb(val, reg_addr);
  237. }
  238. /*
  239. * Basic I/O functions
  240. */
  241. static void snd_cs4231_ready(struct snd_cs4231 *chip)
  242. {
  243. int timeout;
  244. for (timeout = 250; timeout > 0; timeout--) {
  245. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  246. if ((val & CS4231_INIT) == 0)
  247. break;
  248. udelay(100);
  249. }
  250. }
  251. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
  252. unsigned char value)
  253. {
  254. snd_cs4231_ready(chip);
  255. #ifdef CONFIG_SND_DEBUG
  256. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  257. snd_printdd("out: auto calibration time out - reg = 0x%x, "
  258. "value = 0x%x\n",
  259. reg, value);
  260. #endif
  261. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  262. wmb();
  263. __cs4231_writeb(chip, value, CS4231U(chip, REG));
  264. mb();
  265. }
  266. static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  267. unsigned char mask, unsigned char value)
  268. {
  269. unsigned char tmp = (chip->image[reg] & mask) | value;
  270. chip->image[reg] = tmp;
  271. if (!chip->calibrate_mute)
  272. snd_cs4231_dout(chip, reg, tmp);
  273. }
  274. static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
  275. unsigned char value)
  276. {
  277. snd_cs4231_dout(chip, reg, value);
  278. chip->image[reg] = value;
  279. mb();
  280. }
  281. static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  282. {
  283. snd_cs4231_ready(chip);
  284. #ifdef CONFIG_SND_DEBUG
  285. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  286. snd_printdd("in: auto calibration time out - reg = 0x%x\n",
  287. reg);
  288. #endif
  289. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  290. mb();
  291. return __cs4231_readb(chip, CS4231U(chip, REG));
  292. }
  293. /*
  294. * CS4231 detection / MCE routines
  295. */
  296. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  297. {
  298. int timeout;
  299. /* looks like this sequence is proper for CS4231A chip (GUS MAX) */
  300. for (timeout = 5; timeout > 0; timeout--)
  301. __cs4231_readb(chip, CS4231U(chip, REGSEL));
  302. /* end of cleanup sequence */
  303. for (timeout = 500; timeout > 0; timeout--) {
  304. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  305. if ((val & CS4231_INIT) == 0)
  306. break;
  307. msleep(1);
  308. }
  309. }
  310. static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  311. {
  312. unsigned long flags;
  313. int timeout;
  314. spin_lock_irqsave(&chip->lock, flags);
  315. snd_cs4231_ready(chip);
  316. #ifdef CONFIG_SND_DEBUG
  317. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  318. snd_printdd("mce_up - auto calibration time out (0)\n");
  319. #endif
  320. chip->mce_bit |= CS4231_MCE;
  321. timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  322. if (timeout == 0x80)
  323. snd_printdd("mce_up [%p]: serious init problem - "
  324. "codec still busy\n",
  325. chip->port);
  326. if (!(timeout & CS4231_MCE))
  327. __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
  328. CS4231U(chip, REGSEL));
  329. spin_unlock_irqrestore(&chip->lock, flags);
  330. }
  331. static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  332. {
  333. unsigned long flags, timeout;
  334. int reg;
  335. snd_cs4231_busy_wait(chip);
  336. spin_lock_irqsave(&chip->lock, flags);
  337. #ifdef CONFIG_SND_DEBUG
  338. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  339. snd_printdd("mce_down [%p] - auto calibration time out (0)\n",
  340. CS4231U(chip, REGSEL));
  341. #endif
  342. chip->mce_bit &= ~CS4231_MCE;
  343. reg = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  344. __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f),
  345. CS4231U(chip, REGSEL));
  346. if (reg == 0x80)
  347. snd_printdd("mce_down [%p]: serious init problem "
  348. "- codec still busy\n", chip->port);
  349. if ((reg & CS4231_MCE) == 0) {
  350. spin_unlock_irqrestore(&chip->lock, flags);
  351. return;
  352. }
  353. /*
  354. * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
  355. */
  356. timeout = jiffies + msecs_to_jiffies(250);
  357. do {
  358. spin_unlock_irqrestore(&chip->lock, flags);
  359. msleep(1);
  360. spin_lock_irqsave(&chip->lock, flags);
  361. reg = snd_cs4231_in(chip, CS4231_TEST_INIT);
  362. reg &= CS4231_CALIB_IN_PROGRESS;
  363. } while (reg && time_before(jiffies, timeout));
  364. spin_unlock_irqrestore(&chip->lock, flags);
  365. if (reg)
  366. snd_printk(KERN_ERR
  367. "mce_down - auto calibration time out (2)\n");
  368. }
  369. static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
  370. struct snd_pcm_substream *substream,
  371. unsigned int *periods_sent)
  372. {
  373. struct snd_pcm_runtime *runtime = substream->runtime;
  374. while (1) {
  375. unsigned int period_size = snd_pcm_lib_period_bytes(substream);
  376. unsigned int offset = period_size * (*periods_sent);
  377. BUG_ON(period_size >= (1 << 24));
  378. if (dma_cont->request(dma_cont,
  379. runtime->dma_addr + offset, period_size))
  380. return;
  381. (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
  382. }
  383. }
  384. static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
  385. unsigned int what, int on)
  386. {
  387. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  388. struct cs4231_dma_control *dma_cont;
  389. if (what & CS4231_PLAYBACK_ENABLE) {
  390. dma_cont = &chip->p_dma;
  391. if (on) {
  392. dma_cont->prepare(dma_cont, 0);
  393. dma_cont->enable(dma_cont, 1);
  394. snd_cs4231_advance_dma(dma_cont,
  395. chip->playback_substream,
  396. &chip->p_periods_sent);
  397. } else {
  398. dma_cont->enable(dma_cont, 0);
  399. }
  400. }
  401. if (what & CS4231_RECORD_ENABLE) {
  402. dma_cont = &chip->c_dma;
  403. if (on) {
  404. dma_cont->prepare(dma_cont, 1);
  405. dma_cont->enable(dma_cont, 1);
  406. snd_cs4231_advance_dma(dma_cont,
  407. chip->capture_substream,
  408. &chip->c_periods_sent);
  409. } else {
  410. dma_cont->enable(dma_cont, 0);
  411. }
  412. }
  413. }
  414. static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
  415. {
  416. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  417. int result = 0;
  418. switch (cmd) {
  419. case SNDRV_PCM_TRIGGER_START:
  420. case SNDRV_PCM_TRIGGER_STOP:
  421. {
  422. unsigned int what = 0;
  423. struct snd_pcm_substream *s;
  424. unsigned long flags;
  425. snd_pcm_group_for_each_entry(s, substream) {
  426. if (s == chip->playback_substream) {
  427. what |= CS4231_PLAYBACK_ENABLE;
  428. snd_pcm_trigger_done(s, substream);
  429. } else if (s == chip->capture_substream) {
  430. what |= CS4231_RECORD_ENABLE;
  431. snd_pcm_trigger_done(s, substream);
  432. }
  433. }
  434. spin_lock_irqsave(&chip->lock, flags);
  435. if (cmd == SNDRV_PCM_TRIGGER_START) {
  436. cs4231_dma_trigger(substream, what, 1);
  437. chip->image[CS4231_IFACE_CTRL] |= what;
  438. } else {
  439. cs4231_dma_trigger(substream, what, 0);
  440. chip->image[CS4231_IFACE_CTRL] &= ~what;
  441. }
  442. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  443. chip->image[CS4231_IFACE_CTRL]);
  444. spin_unlock_irqrestore(&chip->lock, flags);
  445. break;
  446. }
  447. default:
  448. result = -EINVAL;
  449. break;
  450. }
  451. return result;
  452. }
  453. /*
  454. * CODEC I/O
  455. */
  456. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  457. {
  458. int i;
  459. for (i = 0; i < 14; i++)
  460. if (rate == rates[i])
  461. return freq_bits[i];
  462. return freq_bits[13];
  463. }
  464. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format,
  465. int channels)
  466. {
  467. unsigned char rformat;
  468. rformat = CS4231_LINEAR_8;
  469. switch (format) {
  470. case SNDRV_PCM_FORMAT_MU_LAW:
  471. rformat = CS4231_ULAW_8;
  472. break;
  473. case SNDRV_PCM_FORMAT_A_LAW:
  474. rformat = CS4231_ALAW_8;
  475. break;
  476. case SNDRV_PCM_FORMAT_S16_LE:
  477. rformat = CS4231_LINEAR_16;
  478. break;
  479. case SNDRV_PCM_FORMAT_S16_BE:
  480. rformat = CS4231_LINEAR_16_BIG;
  481. break;
  482. case SNDRV_PCM_FORMAT_IMA_ADPCM:
  483. rformat = CS4231_ADPCM_16;
  484. break;
  485. }
  486. if (channels > 1)
  487. rformat |= CS4231_STEREO;
  488. return rformat;
  489. }
  490. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  491. {
  492. unsigned long flags;
  493. mute = mute ? 1 : 0;
  494. spin_lock_irqsave(&chip->lock, flags);
  495. if (chip->calibrate_mute == mute) {
  496. spin_unlock_irqrestore(&chip->lock, flags);
  497. return;
  498. }
  499. if (!mute) {
  500. snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
  501. chip->image[CS4231_LEFT_INPUT]);
  502. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
  503. chip->image[CS4231_RIGHT_INPUT]);
  504. snd_cs4231_dout(chip, CS4231_LOOPBACK,
  505. chip->image[CS4231_LOOPBACK]);
  506. }
  507. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
  508. mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  509. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
  510. mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  511. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
  512. mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  513. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
  514. mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  515. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
  516. mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  517. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
  518. mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  519. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
  520. mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  521. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
  522. mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  523. snd_cs4231_dout(chip, CS4231_MONO_CTRL,
  524. mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  525. chip->calibrate_mute = mute;
  526. spin_unlock_irqrestore(&chip->lock, flags);
  527. }
  528. static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
  529. struct snd_pcm_hw_params *params,
  530. unsigned char pdfr)
  531. {
  532. unsigned long flags;
  533. mutex_lock(&chip->mce_mutex);
  534. snd_cs4231_calibrate_mute(chip, 1);
  535. snd_cs4231_mce_up(chip);
  536. spin_lock_irqsave(&chip->lock, flags);
  537. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  538. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  539. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  540. pdfr);
  541. spin_unlock_irqrestore(&chip->lock, flags);
  542. snd_cs4231_mce_down(chip);
  543. snd_cs4231_calibrate_mute(chip, 0);
  544. mutex_unlock(&chip->mce_mutex);
  545. }
  546. static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
  547. struct snd_pcm_hw_params *params,
  548. unsigned char cdfr)
  549. {
  550. unsigned long flags;
  551. mutex_lock(&chip->mce_mutex);
  552. snd_cs4231_calibrate_mute(chip, 1);
  553. snd_cs4231_mce_up(chip);
  554. spin_lock_irqsave(&chip->lock, flags);
  555. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  556. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  557. ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  558. (cdfr & 0x0f));
  559. spin_unlock_irqrestore(&chip->lock, flags);
  560. snd_cs4231_mce_down(chip);
  561. snd_cs4231_mce_up(chip);
  562. spin_lock_irqsave(&chip->lock, flags);
  563. }
  564. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  565. spin_unlock_irqrestore(&chip->lock, flags);
  566. snd_cs4231_mce_down(chip);
  567. snd_cs4231_calibrate_mute(chip, 0);
  568. mutex_unlock(&chip->mce_mutex);
  569. }
  570. /*
  571. * Timer interface
  572. */
  573. static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
  574. {
  575. struct snd_cs4231 *chip = snd_timer_chip(timer);
  576. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  577. }
  578. static int snd_cs4231_timer_start(struct snd_timer *timer)
  579. {
  580. unsigned long flags;
  581. unsigned int ticks;
  582. struct snd_cs4231 *chip = snd_timer_chip(timer);
  583. spin_lock_irqsave(&chip->lock, flags);
  584. ticks = timer->sticks;
  585. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  586. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  587. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  588. snd_cs4231_out(chip, CS4231_TIMER_HIGH,
  589. chip->image[CS4231_TIMER_HIGH] =
  590. (unsigned char) (ticks >> 8));
  591. snd_cs4231_out(chip, CS4231_TIMER_LOW,
  592. chip->image[CS4231_TIMER_LOW] =
  593. (unsigned char) ticks);
  594. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  595. chip->image[CS4231_ALT_FEATURE_1] |
  596. CS4231_TIMER_ENABLE);
  597. }
  598. spin_unlock_irqrestore(&chip->lock, flags);
  599. return 0;
  600. }
  601. static int snd_cs4231_timer_stop(struct snd_timer *timer)
  602. {
  603. unsigned long flags;
  604. struct snd_cs4231 *chip = snd_timer_chip(timer);
  605. spin_lock_irqsave(&chip->lock, flags);
  606. chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
  607. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  608. chip->image[CS4231_ALT_FEATURE_1]);
  609. spin_unlock_irqrestore(&chip->lock, flags);
  610. return 0;
  611. }
  612. static void __devinit snd_cs4231_init(struct snd_cs4231 *chip)
  613. {
  614. unsigned long flags;
  615. snd_cs4231_mce_down(chip);
  616. #ifdef SNDRV_DEBUG_MCE
  617. snd_printdd("init: (1)\n");
  618. #endif
  619. snd_cs4231_mce_up(chip);
  620. spin_lock_irqsave(&chip->lock, flags);
  621. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  622. CS4231_PLAYBACK_PIO |
  623. CS4231_RECORD_ENABLE |
  624. CS4231_RECORD_PIO |
  625. CS4231_CALIB_MODE);
  626. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  627. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  628. spin_unlock_irqrestore(&chip->lock, flags);
  629. snd_cs4231_mce_down(chip);
  630. #ifdef SNDRV_DEBUG_MCE
  631. snd_printdd("init: (2)\n");
  632. #endif
  633. snd_cs4231_mce_up(chip);
  634. spin_lock_irqsave(&chip->lock, flags);
  635. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  636. chip->image[CS4231_ALT_FEATURE_1]);
  637. spin_unlock_irqrestore(&chip->lock, flags);
  638. snd_cs4231_mce_down(chip);
  639. #ifdef SNDRV_DEBUG_MCE
  640. snd_printdd("init: (3) - afei = 0x%x\n",
  641. chip->image[CS4231_ALT_FEATURE_1]);
  642. #endif
  643. spin_lock_irqsave(&chip->lock, flags);
  644. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2,
  645. chip->image[CS4231_ALT_FEATURE_2]);
  646. spin_unlock_irqrestore(&chip->lock, flags);
  647. snd_cs4231_mce_up(chip);
  648. spin_lock_irqsave(&chip->lock, flags);
  649. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  650. chip->image[CS4231_PLAYBK_FORMAT]);
  651. spin_unlock_irqrestore(&chip->lock, flags);
  652. snd_cs4231_mce_down(chip);
  653. #ifdef SNDRV_DEBUG_MCE
  654. snd_printdd("init: (4)\n");
  655. #endif
  656. snd_cs4231_mce_up(chip);
  657. spin_lock_irqsave(&chip->lock, flags);
  658. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  659. spin_unlock_irqrestore(&chip->lock, flags);
  660. snd_cs4231_mce_down(chip);
  661. #ifdef SNDRV_DEBUG_MCE
  662. snd_printdd("init: (5)\n");
  663. #endif
  664. }
  665. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  666. {
  667. unsigned long flags;
  668. mutex_lock(&chip->open_mutex);
  669. if ((chip->mode & mode)) {
  670. mutex_unlock(&chip->open_mutex);
  671. return -EAGAIN;
  672. }
  673. if (chip->mode & CS4231_MODE_OPEN) {
  674. chip->mode |= mode;
  675. mutex_unlock(&chip->open_mutex);
  676. return 0;
  677. }
  678. /* ok. now enable and ack CODEC IRQ */
  679. spin_lock_irqsave(&chip->lock, flags);
  680. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  681. CS4231_RECORD_IRQ |
  682. CS4231_TIMER_IRQ);
  683. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  684. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  685. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  686. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  687. CS4231_RECORD_IRQ |
  688. CS4231_TIMER_IRQ);
  689. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  690. spin_unlock_irqrestore(&chip->lock, flags);
  691. chip->mode = mode;
  692. mutex_unlock(&chip->open_mutex);
  693. return 0;
  694. }
  695. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  696. {
  697. unsigned long flags;
  698. mutex_lock(&chip->open_mutex);
  699. chip->mode &= ~mode;
  700. if (chip->mode & CS4231_MODE_OPEN) {
  701. mutex_unlock(&chip->open_mutex);
  702. return;
  703. }
  704. snd_cs4231_calibrate_mute(chip, 1);
  705. /* disable IRQ */
  706. spin_lock_irqsave(&chip->lock, flags);
  707. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  708. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  709. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  710. /* now disable record & playback */
  711. if (chip->image[CS4231_IFACE_CTRL] &
  712. (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  713. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  714. spin_unlock_irqrestore(&chip->lock, flags);
  715. snd_cs4231_mce_up(chip);
  716. spin_lock_irqsave(&chip->lock, flags);
  717. chip->image[CS4231_IFACE_CTRL] &=
  718. ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  719. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  720. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  721. chip->image[CS4231_IFACE_CTRL]);
  722. spin_unlock_irqrestore(&chip->lock, flags);
  723. snd_cs4231_mce_down(chip);
  724. spin_lock_irqsave(&chip->lock, flags);
  725. }
  726. /* clear IRQ again */
  727. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  728. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  729. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  730. spin_unlock_irqrestore(&chip->lock, flags);
  731. snd_cs4231_calibrate_mute(chip, 0);
  732. chip->mode = 0;
  733. mutex_unlock(&chip->open_mutex);
  734. }
  735. /*
  736. * timer open/close
  737. */
  738. static int snd_cs4231_timer_open(struct snd_timer *timer)
  739. {
  740. struct snd_cs4231 *chip = snd_timer_chip(timer);
  741. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  742. return 0;
  743. }
  744. static int snd_cs4231_timer_close(struct snd_timer *timer)
  745. {
  746. struct snd_cs4231 *chip = snd_timer_chip(timer);
  747. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  748. return 0;
  749. }
  750. static struct snd_timer_hardware snd_cs4231_timer_table = {
  751. .flags = SNDRV_TIMER_HW_AUTO,
  752. .resolution = 9945,
  753. .ticks = 65535,
  754. .open = snd_cs4231_timer_open,
  755. .close = snd_cs4231_timer_close,
  756. .c_resolution = snd_cs4231_timer_resolution,
  757. .start = snd_cs4231_timer_start,
  758. .stop = snd_cs4231_timer_stop,
  759. };
  760. /*
  761. * ok.. exported functions..
  762. */
  763. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  764. struct snd_pcm_hw_params *hw_params)
  765. {
  766. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  767. unsigned char new_pdfr;
  768. int err;
  769. err = snd_pcm_lib_malloc_pages(substream,
  770. params_buffer_bytes(hw_params));
  771. if (err < 0)
  772. return err;
  773. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  774. params_channels(hw_params)) |
  775. snd_cs4231_get_rate(params_rate(hw_params));
  776. snd_cs4231_playback_format(chip, hw_params, new_pdfr);
  777. return 0;
  778. }
  779. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  780. {
  781. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  782. struct snd_pcm_runtime *runtime = substream->runtime;
  783. unsigned long flags;
  784. spin_lock_irqsave(&chip->lock, flags);
  785. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  786. CS4231_PLAYBACK_PIO);
  787. BUG_ON(runtime->period_size > 0xffff + 1);
  788. chip->p_periods_sent = 0;
  789. spin_unlock_irqrestore(&chip->lock, flags);
  790. return 0;
  791. }
  792. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  793. struct snd_pcm_hw_params *hw_params)
  794. {
  795. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  796. unsigned char new_cdfr;
  797. int err;
  798. err = snd_pcm_lib_malloc_pages(substream,
  799. params_buffer_bytes(hw_params));
  800. if (err < 0)
  801. return err;
  802. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  803. params_channels(hw_params)) |
  804. snd_cs4231_get_rate(params_rate(hw_params));
  805. snd_cs4231_capture_format(chip, hw_params, new_cdfr);
  806. return 0;
  807. }
  808. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  809. {
  810. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  811. unsigned long flags;
  812. spin_lock_irqsave(&chip->lock, flags);
  813. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
  814. CS4231_RECORD_PIO);
  815. chip->c_periods_sent = 0;
  816. spin_unlock_irqrestore(&chip->lock, flags);
  817. return 0;
  818. }
  819. static void snd_cs4231_overrange(struct snd_cs4231 *chip)
  820. {
  821. unsigned long flags;
  822. unsigned char res;
  823. spin_lock_irqsave(&chip->lock, flags);
  824. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  825. spin_unlock_irqrestore(&chip->lock, flags);
  826. /* detect overrange only above 0dB; may be user selectable? */
  827. if (res & (0x08 | 0x02))
  828. chip->capture_substream->runtime->overrange++;
  829. }
  830. static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
  831. {
  832. if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
  833. snd_pcm_period_elapsed(chip->playback_substream);
  834. snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
  835. &chip->p_periods_sent);
  836. }
  837. }
  838. static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
  839. {
  840. if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
  841. snd_pcm_period_elapsed(chip->capture_substream);
  842. snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
  843. &chip->c_periods_sent);
  844. }
  845. }
  846. static snd_pcm_uframes_t snd_cs4231_playback_pointer(
  847. struct snd_pcm_substream *substream)
  848. {
  849. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  850. struct cs4231_dma_control *dma_cont = &chip->p_dma;
  851. size_t ptr;
  852. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  853. return 0;
  854. ptr = dma_cont->address(dma_cont);
  855. if (ptr != 0)
  856. ptr -= substream->runtime->dma_addr;
  857. return bytes_to_frames(substream->runtime, ptr);
  858. }
  859. static snd_pcm_uframes_t snd_cs4231_capture_pointer(
  860. struct snd_pcm_substream *substream)
  861. {
  862. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  863. struct cs4231_dma_control *dma_cont = &chip->c_dma;
  864. size_t ptr;
  865. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  866. return 0;
  867. ptr = dma_cont->address(dma_cont);
  868. if (ptr != 0)
  869. ptr -= substream->runtime->dma_addr;
  870. return bytes_to_frames(substream->runtime, ptr);
  871. }
  872. static int __devinit snd_cs4231_probe(struct snd_cs4231 *chip)
  873. {
  874. unsigned long flags;
  875. int i;
  876. int id = 0;
  877. int vers = 0;
  878. unsigned char *ptr;
  879. for (i = 0; i < 50; i++) {
  880. mb();
  881. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  882. msleep(2);
  883. else {
  884. spin_lock_irqsave(&chip->lock, flags);
  885. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  886. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  887. vers = snd_cs4231_in(chip, CS4231_VERSION);
  888. spin_unlock_irqrestore(&chip->lock, flags);
  889. if (id == 0x0a)
  890. break; /* this is valid value */
  891. }
  892. }
  893. snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
  894. if (id != 0x0a)
  895. return -ENODEV; /* no valid device found */
  896. spin_lock_irqsave(&chip->lock, flags);
  897. /* clear any pendings IRQ */
  898. __cs4231_readb(chip, CS4231U(chip, STATUS));
  899. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS));
  900. mb();
  901. spin_unlock_irqrestore(&chip->lock, flags);
  902. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  903. chip->image[CS4231_IFACE_CTRL] =
  904. chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
  905. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  906. chip->image[CS4231_ALT_FEATURE_2] = 0x01;
  907. if (vers & 0x20)
  908. chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
  909. ptr = (unsigned char *) &chip->image;
  910. snd_cs4231_mce_down(chip);
  911. spin_lock_irqsave(&chip->lock, flags);
  912. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  913. snd_cs4231_out(chip, i, *ptr++);
  914. spin_unlock_irqrestore(&chip->lock, flags);
  915. snd_cs4231_mce_up(chip);
  916. snd_cs4231_mce_down(chip);
  917. mdelay(2);
  918. return 0; /* all things are ok.. */
  919. }
  920. static struct snd_pcm_hardware snd_cs4231_playback = {
  921. .info = SNDRV_PCM_INFO_MMAP |
  922. SNDRV_PCM_INFO_INTERLEAVED |
  923. SNDRV_PCM_INFO_MMAP_VALID |
  924. SNDRV_PCM_INFO_SYNC_START,
  925. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  926. SNDRV_PCM_FMTBIT_A_LAW |
  927. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  928. SNDRV_PCM_FMTBIT_U8 |
  929. SNDRV_PCM_FMTBIT_S16_LE |
  930. SNDRV_PCM_FMTBIT_S16_BE,
  931. .rates = SNDRV_PCM_RATE_KNOT |
  932. SNDRV_PCM_RATE_8000_48000,
  933. .rate_min = 5510,
  934. .rate_max = 48000,
  935. .channels_min = 1,
  936. .channels_max = 2,
  937. .buffer_bytes_max = 32 * 1024,
  938. .period_bytes_min = 64,
  939. .period_bytes_max = 32 * 1024,
  940. .periods_min = 1,
  941. .periods_max = 1024,
  942. };
  943. static struct snd_pcm_hardware snd_cs4231_capture = {
  944. .info = SNDRV_PCM_INFO_MMAP |
  945. SNDRV_PCM_INFO_INTERLEAVED |
  946. SNDRV_PCM_INFO_MMAP_VALID |
  947. SNDRV_PCM_INFO_SYNC_START,
  948. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  949. SNDRV_PCM_FMTBIT_A_LAW |
  950. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  951. SNDRV_PCM_FMTBIT_U8 |
  952. SNDRV_PCM_FMTBIT_S16_LE |
  953. SNDRV_PCM_FMTBIT_S16_BE,
  954. .rates = SNDRV_PCM_RATE_KNOT |
  955. SNDRV_PCM_RATE_8000_48000,
  956. .rate_min = 5510,
  957. .rate_max = 48000,
  958. .channels_min = 1,
  959. .channels_max = 2,
  960. .buffer_bytes_max = 32 * 1024,
  961. .period_bytes_min = 64,
  962. .period_bytes_max = 32 * 1024,
  963. .periods_min = 1,
  964. .periods_max = 1024,
  965. };
  966. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  967. {
  968. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  969. struct snd_pcm_runtime *runtime = substream->runtime;
  970. int err;
  971. runtime->hw = snd_cs4231_playback;
  972. err = snd_cs4231_open(chip, CS4231_MODE_PLAY);
  973. if (err < 0) {
  974. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  975. return err;
  976. }
  977. chip->playback_substream = substream;
  978. chip->p_periods_sent = 0;
  979. snd_pcm_set_sync(substream);
  980. snd_cs4231_xrate(runtime);
  981. return 0;
  982. }
  983. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  984. {
  985. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  986. struct snd_pcm_runtime *runtime = substream->runtime;
  987. int err;
  988. runtime->hw = snd_cs4231_capture;
  989. err = snd_cs4231_open(chip, CS4231_MODE_RECORD);
  990. if (err < 0) {
  991. snd_free_pages(runtime->dma_area, runtime->dma_bytes);
  992. return err;
  993. }
  994. chip->capture_substream = substream;
  995. chip->c_periods_sent = 0;
  996. snd_pcm_set_sync(substream);
  997. snd_cs4231_xrate(runtime);
  998. return 0;
  999. }
  1000. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  1001. {
  1002. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1003. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  1004. chip->playback_substream = NULL;
  1005. return 0;
  1006. }
  1007. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1008. {
  1009. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1010. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1011. chip->capture_substream = NULL;
  1012. return 0;
  1013. }
  1014. /* XXX We can do some power-management, in particular on EBUS using
  1015. * XXX the audio AUXIO register...
  1016. */
  1017. static struct snd_pcm_ops snd_cs4231_playback_ops = {
  1018. .open = snd_cs4231_playback_open,
  1019. .close = snd_cs4231_playback_close,
  1020. .ioctl = snd_pcm_lib_ioctl,
  1021. .hw_params = snd_cs4231_playback_hw_params,
  1022. .hw_free = snd_pcm_lib_free_pages,
  1023. .prepare = snd_cs4231_playback_prepare,
  1024. .trigger = snd_cs4231_trigger,
  1025. .pointer = snd_cs4231_playback_pointer,
  1026. };
  1027. static struct snd_pcm_ops snd_cs4231_capture_ops = {
  1028. .open = snd_cs4231_capture_open,
  1029. .close = snd_cs4231_capture_close,
  1030. .ioctl = snd_pcm_lib_ioctl,
  1031. .hw_params = snd_cs4231_capture_hw_params,
  1032. .hw_free = snd_pcm_lib_free_pages,
  1033. .prepare = snd_cs4231_capture_prepare,
  1034. .trigger = snd_cs4231_trigger,
  1035. .pointer = snd_cs4231_capture_pointer,
  1036. };
  1037. static int __devinit snd_cs4231_pcm(struct snd_card *card)
  1038. {
  1039. struct snd_cs4231 *chip = card->private_data;
  1040. struct snd_pcm *pcm;
  1041. int err;
  1042. err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
  1043. if (err < 0)
  1044. return err;
  1045. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1046. &snd_cs4231_playback_ops);
  1047. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1048. &snd_cs4231_capture_ops);
  1049. /* global setup */
  1050. pcm->private_data = chip;
  1051. pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1052. strcpy(pcm->name, "CS4231");
  1053. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1054. &chip->op->dev,
  1055. 64 * 1024, 128 * 1024);
  1056. chip->pcm = pcm;
  1057. return 0;
  1058. }
  1059. static int __devinit snd_cs4231_timer(struct snd_card *card)
  1060. {
  1061. struct snd_cs4231 *chip = card->private_data;
  1062. struct snd_timer *timer;
  1063. struct snd_timer_id tid;
  1064. int err;
  1065. /* Timer initialization */
  1066. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1067. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1068. tid.card = card->number;
  1069. tid.device = 0;
  1070. tid.subdevice = 0;
  1071. err = snd_timer_new(card, "CS4231", &tid, &timer);
  1072. if (err < 0)
  1073. return err;
  1074. strcpy(timer->name, "CS4231");
  1075. timer->private_data = chip;
  1076. timer->hw = snd_cs4231_timer_table;
  1077. chip->timer = timer;
  1078. return 0;
  1079. }
  1080. /*
  1081. * MIXER part
  1082. */
  1083. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
  1084. struct snd_ctl_elem_info *uinfo)
  1085. {
  1086. static char *texts[4] = {
  1087. "Line", "CD", "Mic", "Mix"
  1088. };
  1089. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1090. uinfo->count = 2;
  1091. uinfo->value.enumerated.items = 4;
  1092. if (uinfo->value.enumerated.item > 3)
  1093. uinfo->value.enumerated.item = 3;
  1094. strcpy(uinfo->value.enumerated.name,
  1095. texts[uinfo->value.enumerated.item]);
  1096. return 0;
  1097. }
  1098. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
  1099. struct snd_ctl_elem_value *ucontrol)
  1100. {
  1101. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1102. unsigned long flags;
  1103. spin_lock_irqsave(&chip->lock, flags);
  1104. ucontrol->value.enumerated.item[0] =
  1105. (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1106. ucontrol->value.enumerated.item[1] =
  1107. (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1108. spin_unlock_irqrestore(&chip->lock, flags);
  1109. return 0;
  1110. }
  1111. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
  1112. struct snd_ctl_elem_value *ucontrol)
  1113. {
  1114. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1115. unsigned long flags;
  1116. unsigned short left, right;
  1117. int change;
  1118. if (ucontrol->value.enumerated.item[0] > 3 ||
  1119. ucontrol->value.enumerated.item[1] > 3)
  1120. return -EINVAL;
  1121. left = ucontrol->value.enumerated.item[0] << 6;
  1122. right = ucontrol->value.enumerated.item[1] << 6;
  1123. spin_lock_irqsave(&chip->lock, flags);
  1124. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1125. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1126. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1127. right != chip->image[CS4231_RIGHT_INPUT];
  1128. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1129. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1130. spin_unlock_irqrestore(&chip->lock, flags);
  1131. return change;
  1132. }
  1133. static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
  1134. struct snd_ctl_elem_info *uinfo)
  1135. {
  1136. int mask = (kcontrol->private_value >> 16) & 0xff;
  1137. uinfo->type = (mask == 1) ?
  1138. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1139. uinfo->count = 1;
  1140. uinfo->value.integer.min = 0;
  1141. uinfo->value.integer.max = mask;
  1142. return 0;
  1143. }
  1144. static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
  1145. struct snd_ctl_elem_value *ucontrol)
  1146. {
  1147. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1148. unsigned long flags;
  1149. int reg = kcontrol->private_value & 0xff;
  1150. int shift = (kcontrol->private_value >> 8) & 0xff;
  1151. int mask = (kcontrol->private_value >> 16) & 0xff;
  1152. int invert = (kcontrol->private_value >> 24) & 0xff;
  1153. spin_lock_irqsave(&chip->lock, flags);
  1154. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1155. spin_unlock_irqrestore(&chip->lock, flags);
  1156. if (invert)
  1157. ucontrol->value.integer.value[0] =
  1158. (mask - ucontrol->value.integer.value[0]);
  1159. return 0;
  1160. }
  1161. static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
  1162. struct snd_ctl_elem_value *ucontrol)
  1163. {
  1164. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1165. unsigned long flags;
  1166. int reg = kcontrol->private_value & 0xff;
  1167. int shift = (kcontrol->private_value >> 8) & 0xff;
  1168. int mask = (kcontrol->private_value >> 16) & 0xff;
  1169. int invert = (kcontrol->private_value >> 24) & 0xff;
  1170. int change;
  1171. unsigned short val;
  1172. val = (ucontrol->value.integer.value[0] & mask);
  1173. if (invert)
  1174. val = mask - val;
  1175. val <<= shift;
  1176. spin_lock_irqsave(&chip->lock, flags);
  1177. val = (chip->image[reg] & ~(mask << shift)) | val;
  1178. change = val != chip->image[reg];
  1179. snd_cs4231_out(chip, reg, val);
  1180. spin_unlock_irqrestore(&chip->lock, flags);
  1181. return change;
  1182. }
  1183. static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
  1184. struct snd_ctl_elem_info *uinfo)
  1185. {
  1186. int mask = (kcontrol->private_value >> 24) & 0xff;
  1187. uinfo->type = mask == 1 ?
  1188. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1189. uinfo->count = 2;
  1190. uinfo->value.integer.min = 0;
  1191. uinfo->value.integer.max = mask;
  1192. return 0;
  1193. }
  1194. static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
  1195. struct snd_ctl_elem_value *ucontrol)
  1196. {
  1197. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1198. unsigned long flags;
  1199. int left_reg = kcontrol->private_value & 0xff;
  1200. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1201. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1202. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1203. int mask = (kcontrol->private_value >> 24) & 0xff;
  1204. int invert = (kcontrol->private_value >> 22) & 1;
  1205. spin_lock_irqsave(&chip->lock, flags);
  1206. ucontrol->value.integer.value[0] =
  1207. (chip->image[left_reg] >> shift_left) & mask;
  1208. ucontrol->value.integer.value[1] =
  1209. (chip->image[right_reg] >> shift_right) & mask;
  1210. spin_unlock_irqrestore(&chip->lock, flags);
  1211. if (invert) {
  1212. ucontrol->value.integer.value[0] =
  1213. (mask - ucontrol->value.integer.value[0]);
  1214. ucontrol->value.integer.value[1] =
  1215. (mask - ucontrol->value.integer.value[1]);
  1216. }
  1217. return 0;
  1218. }
  1219. static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
  1220. struct snd_ctl_elem_value *ucontrol)
  1221. {
  1222. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1223. unsigned long flags;
  1224. int left_reg = kcontrol->private_value & 0xff;
  1225. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1226. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1227. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1228. int mask = (kcontrol->private_value >> 24) & 0xff;
  1229. int invert = (kcontrol->private_value >> 22) & 1;
  1230. int change;
  1231. unsigned short val1, val2;
  1232. val1 = ucontrol->value.integer.value[0] & mask;
  1233. val2 = ucontrol->value.integer.value[1] & mask;
  1234. if (invert) {
  1235. val1 = mask - val1;
  1236. val2 = mask - val2;
  1237. }
  1238. val1 <<= shift_left;
  1239. val2 <<= shift_right;
  1240. spin_lock_irqsave(&chip->lock, flags);
  1241. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1242. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1243. change = val1 != chip->image[left_reg];
  1244. change |= val2 != chip->image[right_reg];
  1245. snd_cs4231_out(chip, left_reg, val1);
  1246. snd_cs4231_out(chip, right_reg, val2);
  1247. spin_unlock_irqrestore(&chip->lock, flags);
  1248. return change;
  1249. }
  1250. #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
  1251. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1252. .info = snd_cs4231_info_single, \
  1253. .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
  1254. .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) }
  1255. #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \
  1256. shift_right, mask, invert) \
  1257. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1258. .info = snd_cs4231_info_double, \
  1259. .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
  1260. .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \
  1261. ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) }
  1262. static struct snd_kcontrol_new snd_cs4231_controls[] __devinitdata = {
  1263. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT,
  1264. CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1265. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT,
  1266. CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1267. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN,
  1268. CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1269. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN,
  1270. CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1271. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT,
  1272. CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1273. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT,
  1274. CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1275. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT,
  1276. CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1277. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT,
  1278. CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1279. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1280. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1281. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1282. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1283. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0,
  1284. 15, 0),
  1285. {
  1286. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1287. .name = "Capture Source",
  1288. .info = snd_cs4231_info_mux,
  1289. .get = snd_cs4231_get_mux,
  1290. .put = snd_cs4231_put_mux,
  1291. },
  1292. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5,
  1293. 1, 0),
  1294. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1295. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
  1296. /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
  1297. CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
  1298. CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
  1299. };
  1300. static int __devinit snd_cs4231_mixer(struct snd_card *card)
  1301. {
  1302. struct snd_cs4231 *chip = card->private_data;
  1303. int err, idx;
  1304. if (snd_BUG_ON(!chip || !chip->pcm))
  1305. return -EINVAL;
  1306. strcpy(card->mixername, chip->pcm->name);
  1307. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1308. err = snd_ctl_add(card,
  1309. snd_ctl_new1(&snd_cs4231_controls[idx], chip));
  1310. if (err < 0)
  1311. return err;
  1312. }
  1313. return 0;
  1314. }
  1315. static int dev;
  1316. static int __devinit cs4231_attach_begin(struct snd_card **rcard)
  1317. {
  1318. struct snd_card *card;
  1319. struct snd_cs4231 *chip;
  1320. int err;
  1321. *rcard = NULL;
  1322. if (dev >= SNDRV_CARDS)
  1323. return -ENODEV;
  1324. if (!enable[dev]) {
  1325. dev++;
  1326. return -ENOENT;
  1327. }
  1328. err = snd_card_create(index[dev], id[dev], THIS_MODULE,
  1329. sizeof(struct snd_cs4231), &card);
  1330. if (err < 0)
  1331. return err;
  1332. strcpy(card->driver, "CS4231");
  1333. strcpy(card->shortname, "Sun CS4231");
  1334. chip = card->private_data;
  1335. chip->card = card;
  1336. *rcard = card;
  1337. return 0;
  1338. }
  1339. static int __devinit cs4231_attach_finish(struct snd_card *card)
  1340. {
  1341. struct snd_cs4231 *chip = card->private_data;
  1342. int err;
  1343. err = snd_cs4231_pcm(card);
  1344. if (err < 0)
  1345. goto out_err;
  1346. err = snd_cs4231_mixer(card);
  1347. if (err < 0)
  1348. goto out_err;
  1349. err = snd_cs4231_timer(card);
  1350. if (err < 0)
  1351. goto out_err;
  1352. err = snd_card_register(card);
  1353. if (err < 0)
  1354. goto out_err;
  1355. dev_set_drvdata(&chip->op->dev, chip);
  1356. dev++;
  1357. return 0;
  1358. out_err:
  1359. snd_card_free(card);
  1360. return err;
  1361. }
  1362. #ifdef SBUS_SUPPORT
  1363. static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
  1364. {
  1365. unsigned long flags;
  1366. unsigned char status;
  1367. u32 csr;
  1368. struct snd_cs4231 *chip = dev_id;
  1369. /*This is IRQ is not raised by the cs4231*/
  1370. if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ))
  1371. return IRQ_NONE;
  1372. /* ACK the APC interrupt. */
  1373. csr = sbus_readl(chip->port + APCCSR);
  1374. sbus_writel(csr, chip->port + APCCSR);
  1375. if ((csr & APC_PDMA_READY) &&
  1376. (csr & APC_PLAY_INT) &&
  1377. (csr & APC_XINT_PNVA) &&
  1378. !(csr & APC_XINT_EMPT))
  1379. snd_cs4231_play_callback(chip);
  1380. if ((csr & APC_CDMA_READY) &&
  1381. (csr & APC_CAPT_INT) &&
  1382. (csr & APC_XINT_CNVA) &&
  1383. !(csr & APC_XINT_EMPT))
  1384. snd_cs4231_capture_callback(chip);
  1385. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  1386. if (status & CS4231_TIMER_IRQ) {
  1387. if (chip->timer)
  1388. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1389. }
  1390. if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
  1391. snd_cs4231_overrange(chip);
  1392. /* ACK the CS4231 interrupt. */
  1393. spin_lock_irqsave(&chip->lock, flags);
  1394. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  1395. spin_unlock_irqrestore(&chip->lock, flags);
  1396. return IRQ_HANDLED;
  1397. }
  1398. /*
  1399. * SBUS DMA routines
  1400. */
  1401. static int sbus_dma_request(struct cs4231_dma_control *dma_cont,
  1402. dma_addr_t bus_addr, size_t len)
  1403. {
  1404. unsigned long flags;
  1405. u32 test, csr;
  1406. int err;
  1407. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1408. if (len >= (1 << 24))
  1409. return -EINVAL;
  1410. spin_lock_irqsave(&base->lock, flags);
  1411. csr = sbus_readl(base->regs + APCCSR);
  1412. err = -EINVAL;
  1413. test = APC_CDMA_READY;
  1414. if (base->dir == APC_PLAY)
  1415. test = APC_PDMA_READY;
  1416. if (!(csr & test))
  1417. goto out;
  1418. err = -EBUSY;
  1419. test = APC_XINT_CNVA;
  1420. if (base->dir == APC_PLAY)
  1421. test = APC_XINT_PNVA;
  1422. if (!(csr & test))
  1423. goto out;
  1424. err = 0;
  1425. sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
  1426. sbus_writel(len, base->regs + base->dir + APCNC);
  1427. out:
  1428. spin_unlock_irqrestore(&base->lock, flags);
  1429. return err;
  1430. }
  1431. static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
  1432. {
  1433. unsigned long flags;
  1434. u32 csr, test;
  1435. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1436. spin_lock_irqsave(&base->lock, flags);
  1437. csr = sbus_readl(base->regs + APCCSR);
  1438. test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
  1439. APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
  1440. APC_XINT_PENA;
  1441. if (base->dir == APC_RECORD)
  1442. test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
  1443. APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
  1444. csr |= test;
  1445. sbus_writel(csr, base->regs + APCCSR);
  1446. spin_unlock_irqrestore(&base->lock, flags);
  1447. }
  1448. static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1449. {
  1450. unsigned long flags;
  1451. u32 csr, shift;
  1452. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1453. spin_lock_irqsave(&base->lock, flags);
  1454. if (!on) {
  1455. sbus_writel(0, base->regs + base->dir + APCNC);
  1456. sbus_writel(0, base->regs + base->dir + APCNVA);
  1457. if (base->dir == APC_PLAY) {
  1458. sbus_writel(0, base->regs + base->dir + APCC);
  1459. sbus_writel(0, base->regs + base->dir + APCVA);
  1460. }
  1461. udelay(1200);
  1462. }
  1463. csr = sbus_readl(base->regs + APCCSR);
  1464. shift = 0;
  1465. if (base->dir == APC_PLAY)
  1466. shift = 1;
  1467. if (on)
  1468. csr &= ~(APC_CPAUSE << shift);
  1469. else
  1470. csr |= (APC_CPAUSE << shift);
  1471. sbus_writel(csr, base->regs + APCCSR);
  1472. if (on)
  1473. csr |= (APC_CDMA_READY << shift);
  1474. else
  1475. csr &= ~(APC_CDMA_READY << shift);
  1476. sbus_writel(csr, base->regs + APCCSR);
  1477. spin_unlock_irqrestore(&base->lock, flags);
  1478. }
  1479. static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
  1480. {
  1481. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1482. return sbus_readl(base->regs + base->dir + APCVA);
  1483. }
  1484. /*
  1485. * Init and exit routines
  1486. */
  1487. static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
  1488. {
  1489. struct platform_device *op = chip->op;
  1490. if (chip->irq[0])
  1491. free_irq(chip->irq[0], chip);
  1492. if (chip->port)
  1493. of_iounmap(&op->resource[0], chip->port, chip->regs_size);
  1494. return 0;
  1495. }
  1496. static int snd_cs4231_sbus_dev_free(struct snd_device *device)
  1497. {
  1498. struct snd_cs4231 *cp = device->device_data;
  1499. return snd_cs4231_sbus_free(cp);
  1500. }
  1501. static struct snd_device_ops snd_cs4231_sbus_dev_ops = {
  1502. .dev_free = snd_cs4231_sbus_dev_free,
  1503. };
  1504. static int __devinit snd_cs4231_sbus_create(struct snd_card *card,
  1505. struct platform_device *op,
  1506. int dev)
  1507. {
  1508. struct snd_cs4231 *chip = card->private_data;
  1509. int err;
  1510. spin_lock_init(&chip->lock);
  1511. spin_lock_init(&chip->c_dma.sbus_info.lock);
  1512. spin_lock_init(&chip->p_dma.sbus_info.lock);
  1513. mutex_init(&chip->mce_mutex);
  1514. mutex_init(&chip->open_mutex);
  1515. chip->op = op;
  1516. chip->regs_size = resource_size(&op->resource[0]);
  1517. memcpy(&chip->image, &snd_cs4231_original_image,
  1518. sizeof(snd_cs4231_original_image));
  1519. chip->port = of_ioremap(&op->resource[0], 0,
  1520. chip->regs_size, "cs4231");
  1521. if (!chip->port) {
  1522. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1523. return -EIO;
  1524. }
  1525. chip->c_dma.sbus_info.regs = chip->port;
  1526. chip->p_dma.sbus_info.regs = chip->port;
  1527. chip->c_dma.sbus_info.dir = APC_RECORD;
  1528. chip->p_dma.sbus_info.dir = APC_PLAY;
  1529. chip->p_dma.prepare = sbus_dma_prepare;
  1530. chip->p_dma.enable = sbus_dma_enable;
  1531. chip->p_dma.request = sbus_dma_request;
  1532. chip->p_dma.address = sbus_dma_addr;
  1533. chip->c_dma.prepare = sbus_dma_prepare;
  1534. chip->c_dma.enable = sbus_dma_enable;
  1535. chip->c_dma.request = sbus_dma_request;
  1536. chip->c_dma.address = sbus_dma_addr;
  1537. if (request_irq(op->archdata.irqs[0], snd_cs4231_sbus_interrupt,
  1538. IRQF_SHARED, "cs4231", chip)) {
  1539. snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
  1540. dev, op->archdata.irqs[0]);
  1541. snd_cs4231_sbus_free(chip);
  1542. return -EBUSY;
  1543. }
  1544. chip->irq[0] = op->archdata.irqs[0];
  1545. if (snd_cs4231_probe(chip) < 0) {
  1546. snd_cs4231_sbus_free(chip);
  1547. return -ENODEV;
  1548. }
  1549. snd_cs4231_init(chip);
  1550. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1551. chip, &snd_cs4231_sbus_dev_ops)) < 0) {
  1552. snd_cs4231_sbus_free(chip);
  1553. return err;
  1554. }
  1555. return 0;
  1556. }
  1557. static int __devinit cs4231_sbus_probe(struct platform_device *op)
  1558. {
  1559. struct resource *rp = &op->resource[0];
  1560. struct snd_card *card;
  1561. int err;
  1562. err = cs4231_attach_begin(&card);
  1563. if (err)
  1564. return err;
  1565. sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
  1566. card->shortname,
  1567. rp->flags & 0xffL,
  1568. (unsigned long long)rp->start,
  1569. op->archdata.irqs[0]);
  1570. err = snd_cs4231_sbus_create(card, op, dev);
  1571. if (err < 0) {
  1572. snd_card_free(card);
  1573. return err;
  1574. }
  1575. return cs4231_attach_finish(card);
  1576. }
  1577. #endif
  1578. #ifdef EBUS_SUPPORT
  1579. static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event,
  1580. void *cookie)
  1581. {
  1582. struct snd_cs4231 *chip = cookie;
  1583. snd_cs4231_play_callback(chip);
  1584. }
  1585. static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p,
  1586. int event, void *cookie)
  1587. {
  1588. struct snd_cs4231 *chip = cookie;
  1589. snd_cs4231_capture_callback(chip);
  1590. }
  1591. /*
  1592. * EBUS DMA wrappers
  1593. */
  1594. static int _ebus_dma_request(struct cs4231_dma_control *dma_cont,
  1595. dma_addr_t bus_addr, size_t len)
  1596. {
  1597. return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
  1598. }
  1599. static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1600. {
  1601. ebus_dma_enable(&dma_cont->ebus_info, on);
  1602. }
  1603. static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
  1604. {
  1605. ebus_dma_prepare(&dma_cont->ebus_info, dir);
  1606. }
  1607. static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
  1608. {
  1609. return ebus_dma_addr(&dma_cont->ebus_info);
  1610. }
  1611. /*
  1612. * Init and exit routines
  1613. */
  1614. static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
  1615. {
  1616. struct platform_device *op = chip->op;
  1617. if (chip->c_dma.ebus_info.regs) {
  1618. ebus_dma_unregister(&chip->c_dma.ebus_info);
  1619. of_iounmap(&op->resource[2], chip->c_dma.ebus_info.regs, 0x10);
  1620. }
  1621. if (chip->p_dma.ebus_info.regs) {
  1622. ebus_dma_unregister(&chip->p_dma.ebus_info);
  1623. of_iounmap(&op->resource[1], chip->p_dma.ebus_info.regs, 0x10);
  1624. }
  1625. if (chip->port)
  1626. of_iounmap(&op->resource[0], chip->port, 0x10);
  1627. return 0;
  1628. }
  1629. static int snd_cs4231_ebus_dev_free(struct snd_device *device)
  1630. {
  1631. struct snd_cs4231 *cp = device->device_data;
  1632. return snd_cs4231_ebus_free(cp);
  1633. }
  1634. static struct snd_device_ops snd_cs4231_ebus_dev_ops = {
  1635. .dev_free = snd_cs4231_ebus_dev_free,
  1636. };
  1637. static int __devinit snd_cs4231_ebus_create(struct snd_card *card,
  1638. struct platform_device *op,
  1639. int dev)
  1640. {
  1641. struct snd_cs4231 *chip = card->private_data;
  1642. int err;
  1643. spin_lock_init(&chip->lock);
  1644. spin_lock_init(&chip->c_dma.ebus_info.lock);
  1645. spin_lock_init(&chip->p_dma.ebus_info.lock);
  1646. mutex_init(&chip->mce_mutex);
  1647. mutex_init(&chip->open_mutex);
  1648. chip->flags |= CS4231_FLAG_EBUS;
  1649. chip->op = op;
  1650. memcpy(&chip->image, &snd_cs4231_original_image,
  1651. sizeof(snd_cs4231_original_image));
  1652. strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
  1653. chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1654. chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
  1655. chip->c_dma.ebus_info.client_cookie = chip;
  1656. chip->c_dma.ebus_info.irq = op->archdata.irqs[0];
  1657. strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
  1658. chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1659. chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
  1660. chip->p_dma.ebus_info.client_cookie = chip;
  1661. chip->p_dma.ebus_info.irq = op->archdata.irqs[1];
  1662. chip->p_dma.prepare = _ebus_dma_prepare;
  1663. chip->p_dma.enable = _ebus_dma_enable;
  1664. chip->p_dma.request = _ebus_dma_request;
  1665. chip->p_dma.address = _ebus_dma_addr;
  1666. chip->c_dma.prepare = _ebus_dma_prepare;
  1667. chip->c_dma.enable = _ebus_dma_enable;
  1668. chip->c_dma.request = _ebus_dma_request;
  1669. chip->c_dma.address = _ebus_dma_addr;
  1670. chip->port = of_ioremap(&op->resource[0], 0, 0x10, "cs4231");
  1671. chip->p_dma.ebus_info.regs =
  1672. of_ioremap(&op->resource[1], 0, 0x10, "cs4231_pdma");
  1673. chip->c_dma.ebus_info.regs =
  1674. of_ioremap(&op->resource[2], 0, 0x10, "cs4231_cdma");
  1675. if (!chip->port || !chip->p_dma.ebus_info.regs ||
  1676. !chip->c_dma.ebus_info.regs) {
  1677. snd_cs4231_ebus_free(chip);
  1678. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1679. return -EIO;
  1680. }
  1681. if (ebus_dma_register(&chip->c_dma.ebus_info)) {
  1682. snd_cs4231_ebus_free(chip);
  1683. snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n",
  1684. dev);
  1685. return -EBUSY;
  1686. }
  1687. if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
  1688. snd_cs4231_ebus_free(chip);
  1689. snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n",
  1690. dev);
  1691. return -EBUSY;
  1692. }
  1693. if (ebus_dma_register(&chip->p_dma.ebus_info)) {
  1694. snd_cs4231_ebus_free(chip);
  1695. snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n",
  1696. dev);
  1697. return -EBUSY;
  1698. }
  1699. if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
  1700. snd_cs4231_ebus_free(chip);
  1701. snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
  1702. return -EBUSY;
  1703. }
  1704. if (snd_cs4231_probe(chip) < 0) {
  1705. snd_cs4231_ebus_free(chip);
  1706. return -ENODEV;
  1707. }
  1708. snd_cs4231_init(chip);
  1709. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1710. chip, &snd_cs4231_ebus_dev_ops)) < 0) {
  1711. snd_cs4231_ebus_free(chip);
  1712. return err;
  1713. }
  1714. return 0;
  1715. }
  1716. static int __devinit cs4231_ebus_probe(struct platform_device *op)
  1717. {
  1718. struct snd_card *card;
  1719. int err;
  1720. err = cs4231_attach_begin(&card);
  1721. if (err)
  1722. return err;
  1723. sprintf(card->longname, "%s at 0x%llx, irq %d",
  1724. card->shortname,
  1725. op->resource[0].start,
  1726. op->archdata.irqs[0]);
  1727. err = snd_cs4231_ebus_create(card, op, dev);
  1728. if (err < 0) {
  1729. snd_card_free(card);
  1730. return err;
  1731. }
  1732. return cs4231_attach_finish(card);
  1733. }
  1734. #endif
  1735. static int __devinit cs4231_probe(struct platform_device *op)
  1736. {
  1737. #ifdef EBUS_SUPPORT
  1738. if (!strcmp(op->dev.of_node->parent->name, "ebus"))
  1739. return cs4231_ebus_probe(op);
  1740. #endif
  1741. #ifdef SBUS_SUPPORT
  1742. if (!strcmp(op->dev.of_node->parent->name, "sbus") ||
  1743. !strcmp(op->dev.of_node->parent->name, "sbi"))
  1744. return cs4231_sbus_probe(op);
  1745. #endif
  1746. return -ENODEV;
  1747. }
  1748. static int __devexit cs4231_remove(struct platform_device *op)
  1749. {
  1750. struct snd_cs4231 *chip = dev_get_drvdata(&op->dev);
  1751. snd_card_free(chip->card);
  1752. return 0;
  1753. }
  1754. static const struct of_device_id cs4231_match[] = {
  1755. {
  1756. .name = "SUNW,CS4231",
  1757. },
  1758. {
  1759. .name = "audio",
  1760. .compatible = "SUNW,CS4231",
  1761. },
  1762. {},
  1763. };
  1764. MODULE_DEVICE_TABLE(of, cs4231_match);
  1765. static struct platform_driver cs4231_driver = {
  1766. .driver = {
  1767. .name = "audio",
  1768. .owner = THIS_MODULE,
  1769. .of_match_table = cs4231_match,
  1770. },
  1771. .probe = cs4231_probe,
  1772. .remove = __devexit_p(cs4231_remove),
  1773. };
  1774. module_platform_driver(cs4231_driver);