ehci-mem.c 6.8 KB

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  1. /*
  2. * Copyright (c) 2001 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* this file is part of ehci-hcd.c */
  19. /*-------------------------------------------------------------------------*/
  20. /*
  21. * There's basically three types of memory:
  22. * - data used only by the HCD ... kmalloc is fine
  23. * - async and periodic schedules, shared by HC and HCD ... these
  24. * need to use dma_pool or dma_alloc_coherent
  25. * - driver buffers, read/written by HC ... single shot DMA mapped
  26. *
  27. * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
  28. * No memory seen by this driver is pageable.
  29. */
  30. /*-------------------------------------------------------------------------*/
  31. /* Allocate the key transfer structures from the previously allocated pool */
  32. static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
  33. dma_addr_t dma)
  34. {
  35. memset (qtd, 0, sizeof *qtd);
  36. qtd->qtd_dma = dma;
  37. qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
  38. qtd->hw_next = EHCI_LIST_END(ehci);
  39. qtd->hw_alt_next = EHCI_LIST_END(ehci);
  40. INIT_LIST_HEAD (&qtd->qtd_list);
  41. }
  42. static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
  43. {
  44. struct ehci_qtd *qtd;
  45. dma_addr_t dma;
  46. qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
  47. if (qtd != NULL) {
  48. ehci_qtd_init(ehci, qtd, dma);
  49. }
  50. return qtd;
  51. }
  52. static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
  53. {
  54. dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
  55. }
  56. static void qh_destroy(struct ehci_qh *qh)
  57. {
  58. struct ehci_hcd *ehci = qh->ehci;
  59. /* clean qtds first, and know this is not linked */
  60. if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
  61. ehci_dbg (ehci, "unused qh not empty!\n");
  62. BUG ();
  63. }
  64. if (qh->dummy)
  65. ehci_qtd_free (ehci, qh->dummy);
  66. dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
  67. kfree(qh);
  68. }
  69. static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
  70. {
  71. struct ehci_qh *qh;
  72. dma_addr_t dma;
  73. qh = kzalloc(sizeof *qh, GFP_ATOMIC);
  74. if (!qh)
  75. goto done;
  76. qh->hw = (struct ehci_qh_hw *)
  77. dma_pool_alloc(ehci->qh_pool, flags, &dma);
  78. if (!qh->hw)
  79. goto fail;
  80. memset(qh->hw, 0, sizeof *qh->hw);
  81. qh->refcount = 1;
  82. qh->ehci = ehci;
  83. qh->qh_dma = dma;
  84. // INIT_LIST_HEAD (&qh->qh_list);
  85. INIT_LIST_HEAD (&qh->qtd_list);
  86. /* dummy td enables safe urb queuing */
  87. qh->dummy = ehci_qtd_alloc (ehci, flags);
  88. if (qh->dummy == NULL) {
  89. ehci_dbg (ehci, "no dummy td\n");
  90. goto fail1;
  91. }
  92. done:
  93. return qh;
  94. fail1:
  95. dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
  96. fail:
  97. kfree(qh);
  98. return NULL;
  99. }
  100. /* to share a qh (cpu threads, or hc) */
  101. static inline struct ehci_qh *qh_get (struct ehci_qh *qh)
  102. {
  103. WARN_ON(!qh->refcount);
  104. qh->refcount++;
  105. return qh;
  106. }
  107. static inline void qh_put (struct ehci_qh *qh)
  108. {
  109. if (!--qh->refcount)
  110. qh_destroy(qh);
  111. }
  112. /*-------------------------------------------------------------------------*/
  113. /* The queue heads and transfer descriptors are managed from pools tied
  114. * to each of the "per device" structures.
  115. * This is the initialisation and cleanup code.
  116. */
  117. static void ehci_mem_cleanup (struct ehci_hcd *ehci)
  118. {
  119. free_cached_lists(ehci);
  120. if (ehci->async)
  121. qh_put (ehci->async);
  122. ehci->async = NULL;
  123. if (ehci->dummy)
  124. qh_put(ehci->dummy);
  125. ehci->dummy = NULL;
  126. /* DMA consistent memory and pools */
  127. if (ehci->qtd_pool)
  128. dma_pool_destroy (ehci->qtd_pool);
  129. ehci->qtd_pool = NULL;
  130. if (ehci->qh_pool) {
  131. dma_pool_destroy (ehci->qh_pool);
  132. ehci->qh_pool = NULL;
  133. }
  134. if (ehci->itd_pool)
  135. dma_pool_destroy (ehci->itd_pool);
  136. ehci->itd_pool = NULL;
  137. if (ehci->sitd_pool)
  138. dma_pool_destroy (ehci->sitd_pool);
  139. ehci->sitd_pool = NULL;
  140. if (ehci->periodic)
  141. dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
  142. ehci->periodic_size * sizeof (u32),
  143. ehci->periodic, ehci->periodic_dma);
  144. ehci->periodic = NULL;
  145. /* shadow periodic table */
  146. kfree(ehci->pshadow);
  147. ehci->pshadow = NULL;
  148. }
  149. /* remember to add cleanup code (above) if you add anything here */
  150. static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
  151. {
  152. int i;
  153. size_t align;
  154. align = ((ehci->pool_64_bit_align) ? 64 : 32);
  155. /* QTDs for control/bulk/intr transfers */
  156. ehci->qtd_pool = dma_pool_create ("ehci_qtd",
  157. ehci_to_hcd(ehci)->self.controller,
  158. sizeof (struct ehci_qtd),
  159. align /* byte alignment (for hw parts) */,
  160. 4096 /* can't cross 4K */);
  161. if (!ehci->qtd_pool) {
  162. goto fail;
  163. }
  164. /* QHs for control/bulk/intr transfers */
  165. ehci->qh_pool = dma_pool_create ("ehci_qh",
  166. ehci_to_hcd(ehci)->self.controller,
  167. sizeof(struct ehci_qh_hw),
  168. align /* byte alignment (for hw parts) */,
  169. 4096 /* can't cross 4K */);
  170. if (!ehci->qh_pool) {
  171. goto fail;
  172. }
  173. ehci->async = ehci_qh_alloc (ehci, flags);
  174. if (!ehci->async) {
  175. goto fail;
  176. }
  177. /* ITD for high speed ISO transfers */
  178. ehci->itd_pool = dma_pool_create ("ehci_itd",
  179. ehci_to_hcd(ehci)->self.controller,
  180. sizeof (struct ehci_itd),
  181. 32 /* byte alignment (for hw parts) */,
  182. 4096 /* can't cross 4K */);
  183. if (!ehci->itd_pool) {
  184. goto fail;
  185. }
  186. /* SITD for full/low speed split ISO transfers */
  187. ehci->sitd_pool = dma_pool_create ("ehci_sitd",
  188. ehci_to_hcd(ehci)->self.controller,
  189. sizeof (struct ehci_sitd),
  190. 32 /* byte alignment (for hw parts) */,
  191. 4096 /* can't cross 4K */);
  192. if (!ehci->sitd_pool) {
  193. goto fail;
  194. }
  195. /* Hardware periodic table */
  196. ehci->periodic = (__le32 *)
  197. dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
  198. ehci->periodic_size * sizeof(__le32),
  199. &ehci->periodic_dma, 0);
  200. if (ehci->periodic == NULL) {
  201. goto fail;
  202. }
  203. if (ehci->use_dummy_qh) {
  204. struct ehci_qh_hw *hw;
  205. ehci->dummy = ehci_qh_alloc(ehci, flags);
  206. if (!ehci->dummy)
  207. goto fail;
  208. hw = ehci->dummy->hw;
  209. hw->hw_next = EHCI_LIST_END(ehci);
  210. hw->hw_qtd_next = EHCI_LIST_END(ehci);
  211. hw->hw_alt_next = EHCI_LIST_END(ehci);
  212. hw->hw_token &= ~QTD_STS_ACTIVE;
  213. ehci->dummy->hw = hw;
  214. for (i = 0; i < ehci->periodic_size; i++)
  215. ehci->periodic[i] = ehci->dummy->qh_dma;
  216. } else {
  217. for (i = 0; i < ehci->periodic_size; i++)
  218. ehci->periodic[i] = EHCI_LIST_END(ehci);
  219. }
  220. /* software shadow of hardware table */
  221. ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
  222. if (ehci->pshadow != NULL)
  223. return 0;
  224. fail:
  225. ehci_dbg (ehci, "couldn't init memory\n");
  226. ehci_mem_cleanup (ehci);
  227. return -ENOMEM;
  228. }