zd_rf_al7230b.c 13 KB

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  1. /* ZD1211 USB-WLAN driver for Linux
  2. *
  3. * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
  4. * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/kernel.h>
  21. #include "zd_rf.h"
  22. #include "zd_usb.h"
  23. #include "zd_chip.h"
  24. static const u32 chan_rv[][2] = {
  25. RF_CHANNEL( 1) = { 0x09ec00, 0x8cccc8 },
  26. RF_CHANNEL( 2) = { 0x09ec00, 0x8cccd8 },
  27. RF_CHANNEL( 3) = { 0x09ec00, 0x8cccc0 },
  28. RF_CHANNEL( 4) = { 0x09ec00, 0x8cccd0 },
  29. RF_CHANNEL( 5) = { 0x05ec00, 0x8cccc8 },
  30. RF_CHANNEL( 6) = { 0x05ec00, 0x8cccd8 },
  31. RF_CHANNEL( 7) = { 0x05ec00, 0x8cccc0 },
  32. RF_CHANNEL( 8) = { 0x05ec00, 0x8cccd0 },
  33. RF_CHANNEL( 9) = { 0x0dec00, 0x8cccc8 },
  34. RF_CHANNEL(10) = { 0x0dec00, 0x8cccd8 },
  35. RF_CHANNEL(11) = { 0x0dec00, 0x8cccc0 },
  36. RF_CHANNEL(12) = { 0x0dec00, 0x8cccd0 },
  37. RF_CHANNEL(13) = { 0x03ec00, 0x8cccc8 },
  38. RF_CHANNEL(14) = { 0x03ec00, 0x866660 },
  39. };
  40. static const u32 std_rv[] = {
  41. 0x4ff821,
  42. 0xc5fbfc,
  43. 0x21ebfe,
  44. 0xafd401, /* freq shift 0xaad401 */
  45. 0x6cf56a,
  46. 0xe04073,
  47. 0x193d76,
  48. 0x9dd844,
  49. 0x500007,
  50. 0xd8c010,
  51. };
  52. static const u32 rv_init1[] = {
  53. 0x3c9000,
  54. 0xbfffff,
  55. 0x700000,
  56. 0xf15d58,
  57. };
  58. static const u32 rv_init2[] = {
  59. 0xf15d59,
  60. 0xf15d5c,
  61. 0xf15d58,
  62. };
  63. static const struct zd_ioreq16 ioreqs_sw[] = {
  64. { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
  65. { ZD_CR38, 0x38 }, { ZD_CR136, 0xdf },
  66. };
  67. static int zd1211b_al7230b_finalize(struct zd_chip *chip)
  68. {
  69. int r;
  70. static const struct zd_ioreq16 ioreqs[] = {
  71. { ZD_CR80, 0x30 }, { ZD_CR81, 0x30 }, { ZD_CR79, 0x58 },
  72. { ZD_CR12, 0xf0 }, { ZD_CR77, 0x1b }, { ZD_CR78, 0x58 },
  73. { ZD_CR203, 0x04 },
  74. { },
  75. { ZD_CR240, 0x80 },
  76. };
  77. r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  78. if (r)
  79. return r;
  80. if (chip->new_phy_layout) {
  81. /* antenna selection? */
  82. r = zd_iowrite16_locked(chip, 0xe5, ZD_CR9);
  83. if (r)
  84. return r;
  85. }
  86. return zd_iowrite16_locked(chip, 0x04, ZD_CR203);
  87. }
  88. static int zd1211_al7230b_init_hw(struct zd_rf *rf)
  89. {
  90. int r;
  91. struct zd_chip *chip = zd_rf_to_chip(rf);
  92. /* All of these writes are identical to AL2230 unless otherwise
  93. * specified */
  94. static const struct zd_ioreq16 ioreqs_1[] = {
  95. /* This one is 7230-specific, and happens before the rest */
  96. { ZD_CR240, 0x57 },
  97. { },
  98. { ZD_CR15, 0x20 }, { ZD_CR23, 0x40 }, { ZD_CR24, 0x20 },
  99. { ZD_CR26, 0x11 }, { ZD_CR28, 0x3e }, { ZD_CR29, 0x00 },
  100. { ZD_CR44, 0x33 },
  101. /* This value is different for 7230 (was: 0x2a) */
  102. { ZD_CR106, 0x22 },
  103. { ZD_CR107, 0x1a }, { ZD_CR109, 0x09 }, { ZD_CR110, 0x27 },
  104. { ZD_CR111, 0x2b }, { ZD_CR112, 0x2b }, { ZD_CR119, 0x0a },
  105. /* This happened further down in AL2230,
  106. * and the value changed (was: 0xe0) */
  107. { ZD_CR122, 0xfc },
  108. { ZD_CR10, 0x89 },
  109. /* for newest (3rd cut) AL2300 */
  110. { ZD_CR17, 0x28 },
  111. { ZD_CR26, 0x93 }, { ZD_CR34, 0x30 },
  112. /* for newest (3rd cut) AL2300 */
  113. { ZD_CR35, 0x3e },
  114. { ZD_CR41, 0x24 }, { ZD_CR44, 0x32 },
  115. /* for newest (3rd cut) AL2300 */
  116. { ZD_CR46, 0x96 },
  117. { ZD_CR47, 0x1e }, { ZD_CR79, 0x58 }, { ZD_CR80, 0x30 },
  118. { ZD_CR81, 0x30 }, { ZD_CR87, 0x0a }, { ZD_CR89, 0x04 },
  119. { ZD_CR92, 0x0a }, { ZD_CR99, 0x28 },
  120. /* This value is different for 7230 (was: 0x00) */
  121. { ZD_CR100, 0x02 },
  122. { ZD_CR101, 0x13 }, { ZD_CR102, 0x27 },
  123. /* This value is different for 7230 (was: 0x24) */
  124. { ZD_CR106, 0x22 },
  125. /* This value is different for 7230 (was: 0x2a) */
  126. { ZD_CR107, 0x3f },
  127. { ZD_CR109, 0x09 },
  128. /* This value is different for 7230 (was: 0x13) */
  129. { ZD_CR110, 0x1f },
  130. { ZD_CR111, 0x1f }, { ZD_CR112, 0x1f }, { ZD_CR113, 0x27 },
  131. { ZD_CR114, 0x27 },
  132. /* for newest (3rd cut) AL2300 */
  133. { ZD_CR115, 0x24 },
  134. /* This value is different for 7230 (was: 0x24) */
  135. { ZD_CR116, 0x3f },
  136. /* This value is different for 7230 (was: 0xf4) */
  137. { ZD_CR117, 0xfa },
  138. { ZD_CR118, 0xfc }, { ZD_CR119, 0x10 }, { ZD_CR120, 0x4f },
  139. { ZD_CR121, 0x77 }, { ZD_CR137, 0x88 },
  140. /* This one is 7230-specific */
  141. { ZD_CR138, 0xa8 },
  142. /* This value is different for 7230 (was: 0xff) */
  143. { ZD_CR252, 0x34 },
  144. /* This value is different for 7230 (was: 0xff) */
  145. { ZD_CR253, 0x34 },
  146. /* PLL_OFF */
  147. { ZD_CR251, 0x2f },
  148. };
  149. static const struct zd_ioreq16 ioreqs_2[] = {
  150. { ZD_CR251, 0x3f }, /* PLL_ON */
  151. { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
  152. { ZD_CR38, 0x38 }, { ZD_CR136, 0xdf },
  153. };
  154. r = zd_iowrite16a_locked(chip, ioreqs_1, ARRAY_SIZE(ioreqs_1));
  155. if (r)
  156. return r;
  157. r = zd_rfwritev_cr_locked(chip, chan_rv[0], ARRAY_SIZE(chan_rv[0]));
  158. if (r)
  159. return r;
  160. r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv));
  161. if (r)
  162. return r;
  163. r = zd_rfwritev_cr_locked(chip, rv_init1, ARRAY_SIZE(rv_init1));
  164. if (r)
  165. return r;
  166. r = zd_iowrite16a_locked(chip, ioreqs_2, ARRAY_SIZE(ioreqs_2));
  167. if (r)
  168. return r;
  169. r = zd_rfwritev_cr_locked(chip, rv_init2, ARRAY_SIZE(rv_init2));
  170. if (r)
  171. return r;
  172. r = zd_iowrite16_locked(chip, 0x06, ZD_CR203);
  173. if (r)
  174. return r;
  175. r = zd_iowrite16_locked(chip, 0x80, ZD_CR240);
  176. if (r)
  177. return r;
  178. return 0;
  179. }
  180. static int zd1211b_al7230b_init_hw(struct zd_rf *rf)
  181. {
  182. int r;
  183. struct zd_chip *chip = zd_rf_to_chip(rf);
  184. static const struct zd_ioreq16 ioreqs_1[] = {
  185. { ZD_CR240, 0x57 }, { ZD_CR9, 0x9 },
  186. { },
  187. { ZD_CR10, 0x8b }, { ZD_CR15, 0x20 },
  188. { ZD_CR17, 0x2B }, /* for newest (3rd cut) AL2230 */
  189. { ZD_CR20, 0x10 }, /* 4N25->Stone Request */
  190. { ZD_CR23, 0x40 }, { ZD_CR24, 0x20 }, { ZD_CR26, 0x93 },
  191. { ZD_CR28, 0x3e }, { ZD_CR29, 0x00 },
  192. { ZD_CR33, 0x28 }, /* 5613 */
  193. { ZD_CR34, 0x30 },
  194. { ZD_CR35, 0x3e }, /* for newest (3rd cut) AL2230 */
  195. { ZD_CR41, 0x24 }, { ZD_CR44, 0x32 },
  196. { ZD_CR46, 0x99 }, /* for newest (3rd cut) AL2230 */
  197. { ZD_CR47, 0x1e },
  198. /* ZD1215 5610 */
  199. { ZD_CR48, 0x00 }, { ZD_CR49, 0x00 }, { ZD_CR51, 0x01 },
  200. { ZD_CR52, 0x80 }, { ZD_CR53, 0x7e }, { ZD_CR65, 0x00 },
  201. { ZD_CR66, 0x00 }, { ZD_CR67, 0x00 }, { ZD_CR68, 0x00 },
  202. { ZD_CR69, 0x28 },
  203. { ZD_CR79, 0x58 }, { ZD_CR80, 0x30 }, { ZD_CR81, 0x30 },
  204. { ZD_CR87, 0x0A }, { ZD_CR89, 0x04 },
  205. { ZD_CR90, 0x58 }, /* 5112 */
  206. { ZD_CR91, 0x00 }, /* 5613 */
  207. { ZD_CR92, 0x0a },
  208. { ZD_CR98, 0x8d }, /* 4804, for 1212 new algorithm */
  209. { ZD_CR99, 0x00 }, { ZD_CR100, 0x02 }, { ZD_CR101, 0x13 },
  210. { ZD_CR102, 0x27 },
  211. { ZD_CR106, 0x20 }, /* change to 0x24 for AL7230B */
  212. { ZD_CR109, 0x13 }, /* 4804, for 1212 new algorithm */
  213. { ZD_CR112, 0x1f },
  214. };
  215. static const struct zd_ioreq16 ioreqs_new_phy[] = {
  216. { ZD_CR107, 0x28 },
  217. { ZD_CR110, 0x1f }, /* 5127, 0x13->0x1f */
  218. { ZD_CR111, 0x1f }, /* 0x13 to 0x1f for AL7230B */
  219. { ZD_CR116, 0x2a }, { ZD_CR118, 0xfa }, { ZD_CR119, 0x12 },
  220. { ZD_CR121, 0x6c }, /* 5613 */
  221. };
  222. static const struct zd_ioreq16 ioreqs_old_phy[] = {
  223. { ZD_CR107, 0x24 },
  224. { ZD_CR110, 0x13 }, /* 5127, 0x13->0x1f */
  225. { ZD_CR111, 0x13 }, /* 0x13 to 0x1f for AL7230B */
  226. { ZD_CR116, 0x24 }, { ZD_CR118, 0xfc }, { ZD_CR119, 0x11 },
  227. { ZD_CR121, 0x6a }, /* 5613 */
  228. };
  229. static const struct zd_ioreq16 ioreqs_2[] = {
  230. { ZD_CR113, 0x27 }, { ZD_CR114, 0x27 }, { ZD_CR115, 0x24 },
  231. { ZD_CR117, 0xfa }, { ZD_CR120, 0x4f },
  232. { ZD_CR122, 0xfc }, /* E0->FCh at 4901 */
  233. { ZD_CR123, 0x57 }, /* 5613 */
  234. { ZD_CR125, 0xad }, /* 4804, for 1212 new algorithm */
  235. { ZD_CR126, 0x6c }, /* 5613 */
  236. { ZD_CR127, 0x03 }, /* 4804, for 1212 new algorithm */
  237. { ZD_CR130, 0x10 },
  238. { ZD_CR131, 0x00 }, /* 5112 */
  239. { ZD_CR137, 0x50 }, /* 5613 */
  240. { ZD_CR138, 0xa8 }, /* 5112 */
  241. { ZD_CR144, 0xac }, /* 5613 */
  242. { ZD_CR148, 0x40 }, /* 5112 */
  243. { ZD_CR149, 0x40 }, /* 4O07, 50->40 */
  244. { ZD_CR150, 0x1a }, /* 5112, 0C->1A */
  245. { ZD_CR252, 0x34 }, { ZD_CR253, 0x34 },
  246. { ZD_CR251, 0x2f }, /* PLL_OFF */
  247. };
  248. static const struct zd_ioreq16 ioreqs_3[] = {
  249. { ZD_CR251, 0x7f }, /* PLL_ON */
  250. { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 }, { ZD_CR130, 0x10 },
  251. { ZD_CR38, 0x38 }, { ZD_CR136, 0xdf },
  252. };
  253. r = zd_iowrite16a_locked(chip, ioreqs_1, ARRAY_SIZE(ioreqs_1));
  254. if (r)
  255. return r;
  256. if (chip->new_phy_layout)
  257. r = zd_iowrite16a_locked(chip, ioreqs_new_phy,
  258. ARRAY_SIZE(ioreqs_new_phy));
  259. else
  260. r = zd_iowrite16a_locked(chip, ioreqs_old_phy,
  261. ARRAY_SIZE(ioreqs_old_phy));
  262. if (r)
  263. return r;
  264. r = zd_iowrite16a_locked(chip, ioreqs_2, ARRAY_SIZE(ioreqs_2));
  265. if (r)
  266. return r;
  267. r = zd_rfwritev_cr_locked(chip, chan_rv[0], ARRAY_SIZE(chan_rv[0]));
  268. if (r)
  269. return r;
  270. r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv));
  271. if (r)
  272. return r;
  273. r = zd_rfwritev_cr_locked(chip, rv_init1, ARRAY_SIZE(rv_init1));
  274. if (r)
  275. return r;
  276. r = zd_iowrite16a_locked(chip, ioreqs_3, ARRAY_SIZE(ioreqs_3));
  277. if (r)
  278. return r;
  279. r = zd_rfwritev_cr_locked(chip, rv_init2, ARRAY_SIZE(rv_init2));
  280. if (r)
  281. return r;
  282. return zd1211b_al7230b_finalize(chip);
  283. }
  284. static int zd1211_al7230b_set_channel(struct zd_rf *rf, u8 channel)
  285. {
  286. int r;
  287. const u32 *rv = chan_rv[channel-1];
  288. struct zd_chip *chip = zd_rf_to_chip(rf);
  289. static const struct zd_ioreq16 ioreqs[] = {
  290. /* PLL_ON */
  291. { ZD_CR251, 0x3f },
  292. { ZD_CR203, 0x06 }, { ZD_CR240, 0x08 },
  293. };
  294. r = zd_iowrite16_locked(chip, 0x57, ZD_CR240);
  295. if (r)
  296. return r;
  297. /* PLL_OFF */
  298. r = zd_iowrite16_locked(chip, 0x2f, ZD_CR251);
  299. if (r)
  300. return r;
  301. r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv));
  302. if (r)
  303. return r;
  304. r = zd_rfwrite_cr_locked(chip, 0x3c9000);
  305. if (r)
  306. return r;
  307. r = zd_rfwrite_cr_locked(chip, 0xf15d58);
  308. if (r)
  309. return r;
  310. r = zd_iowrite16a_locked(chip, ioreqs_sw, ARRAY_SIZE(ioreqs_sw));
  311. if (r)
  312. return r;
  313. r = zd_rfwritev_cr_locked(chip, rv, 2);
  314. if (r)
  315. return r;
  316. r = zd_rfwrite_cr_locked(chip, 0x3c9000);
  317. if (r)
  318. return r;
  319. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  320. }
  321. static int zd1211b_al7230b_set_channel(struct zd_rf *rf, u8 channel)
  322. {
  323. int r;
  324. const u32 *rv = chan_rv[channel-1];
  325. struct zd_chip *chip = zd_rf_to_chip(rf);
  326. r = zd_iowrite16_locked(chip, 0x57, ZD_CR240);
  327. if (r)
  328. return r;
  329. r = zd_iowrite16_locked(chip, 0xe4, ZD_CR9);
  330. if (r)
  331. return r;
  332. /* PLL_OFF */
  333. r = zd_iowrite16_locked(chip, 0x2f, ZD_CR251);
  334. if (r)
  335. return r;
  336. r = zd_rfwritev_cr_locked(chip, std_rv, ARRAY_SIZE(std_rv));
  337. if (r)
  338. return r;
  339. r = zd_rfwrite_cr_locked(chip, 0x3c9000);
  340. if (r)
  341. return r;
  342. r = zd_rfwrite_cr_locked(chip, 0xf15d58);
  343. if (r)
  344. return r;
  345. r = zd_iowrite16a_locked(chip, ioreqs_sw, ARRAY_SIZE(ioreqs_sw));
  346. if (r)
  347. return r;
  348. r = zd_rfwritev_cr_locked(chip, rv, 2);
  349. if (r)
  350. return r;
  351. r = zd_rfwrite_cr_locked(chip, 0x3c9000);
  352. if (r)
  353. return r;
  354. r = zd_iowrite16_locked(chip, 0x7f, ZD_CR251);
  355. if (r)
  356. return r;
  357. return zd1211b_al7230b_finalize(chip);
  358. }
  359. static int zd1211_al7230b_switch_radio_on(struct zd_rf *rf)
  360. {
  361. struct zd_chip *chip = zd_rf_to_chip(rf);
  362. static const struct zd_ioreq16 ioreqs[] = {
  363. { ZD_CR11, 0x00 },
  364. { ZD_CR251, 0x3f },
  365. };
  366. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  367. }
  368. static int zd1211b_al7230b_switch_radio_on(struct zd_rf *rf)
  369. {
  370. struct zd_chip *chip = zd_rf_to_chip(rf);
  371. static const struct zd_ioreq16 ioreqs[] = {
  372. { ZD_CR11, 0x00 },
  373. { ZD_CR251, 0x7f },
  374. };
  375. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  376. }
  377. static int al7230b_switch_radio_off(struct zd_rf *rf)
  378. {
  379. struct zd_chip *chip = zd_rf_to_chip(rf);
  380. static const struct zd_ioreq16 ioreqs[] = {
  381. { ZD_CR11, 0x04 },
  382. { ZD_CR251, 0x2f },
  383. };
  384. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  385. }
  386. /* ZD1211B+AL7230B 6m band edge patching differs slightly from other
  387. * configurations */
  388. static int zd1211b_al7230b_patch_6m(struct zd_rf *rf, u8 channel)
  389. {
  390. struct zd_chip *chip = zd_rf_to_chip(rf);
  391. struct zd_ioreq16 ioreqs[] = {
  392. { ZD_CR128, 0x14 }, { ZD_CR129, 0x12 },
  393. };
  394. /* FIXME: Channel 11 is not the edge for all regulatory domains. */
  395. if (channel == 1) {
  396. ioreqs[0].value = 0x0e;
  397. ioreqs[1].value = 0x10;
  398. } else if (channel == 11) {
  399. ioreqs[0].value = 0x10;
  400. ioreqs[1].value = 0x10;
  401. }
  402. dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
  403. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  404. }
  405. int zd_rf_init_al7230b(struct zd_rf *rf)
  406. {
  407. struct zd_chip *chip = zd_rf_to_chip(rf);
  408. if (zd_chip_is_zd1211b(chip)) {
  409. rf->init_hw = zd1211b_al7230b_init_hw;
  410. rf->switch_radio_on = zd1211b_al7230b_switch_radio_on;
  411. rf->set_channel = zd1211b_al7230b_set_channel;
  412. rf->patch_6m_band_edge = zd1211b_al7230b_patch_6m;
  413. } else {
  414. rf->init_hw = zd1211_al7230b_init_hw;
  415. rf->switch_radio_on = zd1211_al7230b_switch_radio_on;
  416. rf->set_channel = zd1211_al7230b_set_channel;
  417. rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
  418. rf->patch_cck_gain = 1;
  419. }
  420. rf->switch_radio_off = al7230b_switch_radio_off;
  421. return 0;
  422. }