p54pci.c 16 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/slab.h>
  17. #include <linux/firmware.h>
  18. #include <linux/etherdevice.h>
  19. #include <linux/delay.h>
  20. #include <linux/completion.h>
  21. #include <linux/module.h>
  22. #include <net/mac80211.h>
  23. #include "p54.h"
  24. #include "lmac.h"
  25. #include "p54pci.h"
  26. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  27. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  28. MODULE_LICENSE("GPL");
  29. MODULE_ALIAS("prism54pci");
  30. MODULE_FIRMWARE("isl3886pci");
  31. static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
  32. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  33. { PCI_DEVICE(0x1260, 0x3890) },
  34. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  35. { PCI_DEVICE(0x10b7, 0x6001) },
  36. /* Intersil PRISM Indigo Wireless LAN adapter */
  37. { PCI_DEVICE(0x1260, 0x3877) },
  38. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  39. { PCI_DEVICE(0x1260, 0x3886) },
  40. /* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
  41. { PCI_DEVICE(0x1260, 0xffff) },
  42. { },
  43. };
  44. MODULE_DEVICE_TABLE(pci, p54p_table);
  45. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  46. {
  47. struct p54p_priv *priv = dev->priv;
  48. __le32 reg;
  49. int err;
  50. __le32 *data;
  51. u32 remains, left, device_addr;
  52. P54P_WRITE(int_enable, cpu_to_le32(0));
  53. P54P_READ(int_enable);
  54. udelay(10);
  55. reg = P54P_READ(ctrl_stat);
  56. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  57. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  58. P54P_WRITE(ctrl_stat, reg);
  59. P54P_READ(ctrl_stat);
  60. udelay(10);
  61. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  62. P54P_WRITE(ctrl_stat, reg);
  63. wmb();
  64. udelay(10);
  65. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  66. P54P_WRITE(ctrl_stat, reg);
  67. wmb();
  68. /* wait for the firmware to reset properly */
  69. mdelay(10);
  70. err = p54_parse_firmware(dev, priv->firmware);
  71. if (err)
  72. return err;
  73. if (priv->common.fw_interface != FW_LM86) {
  74. dev_err(&priv->pdev->dev, "wrong firmware, "
  75. "please get a LM86(PCI) firmware a try again.\n");
  76. return -EINVAL;
  77. }
  78. data = (__le32 *) priv->firmware->data;
  79. remains = priv->firmware->size;
  80. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  81. while (remains) {
  82. u32 i = 0;
  83. left = min((u32)0x1000, remains);
  84. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  85. P54P_READ(int_enable);
  86. device_addr += 0x1000;
  87. while (i < left) {
  88. P54P_WRITE(direct_mem_win[i], *data++);
  89. i += sizeof(u32);
  90. }
  91. remains -= left;
  92. P54P_READ(int_enable);
  93. }
  94. reg = P54P_READ(ctrl_stat);
  95. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  96. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  97. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  98. P54P_WRITE(ctrl_stat, reg);
  99. P54P_READ(ctrl_stat);
  100. udelay(10);
  101. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  102. P54P_WRITE(ctrl_stat, reg);
  103. wmb();
  104. udelay(10);
  105. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  106. P54P_WRITE(ctrl_stat, reg);
  107. wmb();
  108. udelay(10);
  109. /* wait for the firmware to boot properly */
  110. mdelay(100);
  111. return 0;
  112. }
  113. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  114. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  115. struct sk_buff **rx_buf, u32 index)
  116. {
  117. struct p54p_priv *priv = dev->priv;
  118. struct p54p_ring_control *ring_control = priv->ring_control;
  119. u32 limit, idx, i;
  120. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  121. limit = idx;
  122. limit -= index;
  123. limit = ring_limit - limit;
  124. i = idx % ring_limit;
  125. while (limit-- > 1) {
  126. struct p54p_desc *desc = &ring[i];
  127. if (!desc->host_addr) {
  128. struct sk_buff *skb;
  129. dma_addr_t mapping;
  130. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  131. if (!skb)
  132. break;
  133. mapping = pci_map_single(priv->pdev,
  134. skb_tail_pointer(skb),
  135. priv->common.rx_mtu + 32,
  136. PCI_DMA_FROMDEVICE);
  137. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  138. dev_kfree_skb_any(skb);
  139. dev_err(&priv->pdev->dev,
  140. "RX DMA Mapping error\n");
  141. break;
  142. }
  143. desc->host_addr = cpu_to_le32(mapping);
  144. desc->device_addr = 0; // FIXME: necessary?
  145. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  146. desc->flags = 0;
  147. rx_buf[i] = skb;
  148. }
  149. i++;
  150. idx++;
  151. i %= ring_limit;
  152. }
  153. wmb();
  154. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  155. }
  156. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  157. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  158. struct sk_buff **rx_buf)
  159. {
  160. struct p54p_priv *priv = dev->priv;
  161. struct p54p_ring_control *ring_control = priv->ring_control;
  162. struct p54p_desc *desc;
  163. u32 idx, i;
  164. i = (*index) % ring_limit;
  165. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  166. idx %= ring_limit;
  167. while (i != idx) {
  168. u16 len;
  169. struct sk_buff *skb;
  170. dma_addr_t dma_addr;
  171. desc = &ring[i];
  172. len = le16_to_cpu(desc->len);
  173. skb = rx_buf[i];
  174. if (!skb) {
  175. i++;
  176. i %= ring_limit;
  177. continue;
  178. }
  179. if (unlikely(len > priv->common.rx_mtu)) {
  180. if (net_ratelimit())
  181. dev_err(&priv->pdev->dev, "rx'd frame size "
  182. "exceeds length threshold.\n");
  183. len = priv->common.rx_mtu;
  184. }
  185. dma_addr = le32_to_cpu(desc->host_addr);
  186. pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
  187. priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
  188. skb_put(skb, len);
  189. if (p54_rx(dev, skb)) {
  190. pci_unmap_single(priv->pdev, dma_addr,
  191. priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
  192. rx_buf[i] = NULL;
  193. desc->host_addr = cpu_to_le32(0);
  194. } else {
  195. skb_trim(skb, 0);
  196. pci_dma_sync_single_for_device(priv->pdev, dma_addr,
  197. priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
  198. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  199. }
  200. i++;
  201. i %= ring_limit;
  202. }
  203. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
  204. }
  205. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  206. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  207. struct sk_buff **tx_buf)
  208. {
  209. struct p54p_priv *priv = dev->priv;
  210. struct p54p_ring_control *ring_control = priv->ring_control;
  211. struct p54p_desc *desc;
  212. struct sk_buff *skb;
  213. u32 idx, i;
  214. i = (*index) % ring_limit;
  215. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  216. idx %= ring_limit;
  217. while (i != idx) {
  218. desc = &ring[i];
  219. skb = tx_buf[i];
  220. tx_buf[i] = NULL;
  221. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  222. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  223. desc->host_addr = 0;
  224. desc->device_addr = 0;
  225. desc->len = 0;
  226. desc->flags = 0;
  227. if (skb && FREE_AFTER_TX(skb))
  228. p54_free_skb(dev, skb);
  229. i++;
  230. i %= ring_limit;
  231. }
  232. }
  233. static void p54p_tasklet(unsigned long dev_id)
  234. {
  235. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  236. struct p54p_priv *priv = dev->priv;
  237. struct p54p_ring_control *ring_control = priv->ring_control;
  238. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
  239. ARRAY_SIZE(ring_control->tx_mgmt),
  240. priv->tx_buf_mgmt);
  241. p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
  242. ARRAY_SIZE(ring_control->tx_data),
  243. priv->tx_buf_data);
  244. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  245. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  246. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  247. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  248. wmb();
  249. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  250. }
  251. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  252. {
  253. struct ieee80211_hw *dev = dev_id;
  254. struct p54p_priv *priv = dev->priv;
  255. __le32 reg;
  256. reg = P54P_READ(int_ident);
  257. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  258. goto out;
  259. }
  260. P54P_WRITE(int_ack, reg);
  261. reg &= P54P_READ(int_enable);
  262. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
  263. tasklet_schedule(&priv->tasklet);
  264. else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  265. complete(&priv->boot_comp);
  266. out:
  267. return reg ? IRQ_HANDLED : IRQ_NONE;
  268. }
  269. static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  270. {
  271. unsigned long flags;
  272. struct p54p_priv *priv = dev->priv;
  273. struct p54p_ring_control *ring_control = priv->ring_control;
  274. struct p54p_desc *desc;
  275. dma_addr_t mapping;
  276. u32 idx, i;
  277. spin_lock_irqsave(&priv->lock, flags);
  278. idx = le32_to_cpu(ring_control->host_idx[1]);
  279. i = idx % ARRAY_SIZE(ring_control->tx_data);
  280. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  281. PCI_DMA_TODEVICE);
  282. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  283. spin_unlock_irqrestore(&priv->lock, flags);
  284. p54_free_skb(dev, skb);
  285. dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
  286. return ;
  287. }
  288. priv->tx_buf_data[i] = skb;
  289. desc = &ring_control->tx_data[i];
  290. desc->host_addr = cpu_to_le32(mapping);
  291. desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
  292. desc->len = cpu_to_le16(skb->len);
  293. desc->flags = 0;
  294. wmb();
  295. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  296. spin_unlock_irqrestore(&priv->lock, flags);
  297. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  298. P54P_READ(dev_int);
  299. }
  300. static void p54p_stop(struct ieee80211_hw *dev)
  301. {
  302. struct p54p_priv *priv = dev->priv;
  303. struct p54p_ring_control *ring_control = priv->ring_control;
  304. unsigned int i;
  305. struct p54p_desc *desc;
  306. P54P_WRITE(int_enable, cpu_to_le32(0));
  307. P54P_READ(int_enable);
  308. udelay(10);
  309. free_irq(priv->pdev->irq, dev);
  310. tasklet_kill(&priv->tasklet);
  311. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  312. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  313. desc = &ring_control->rx_data[i];
  314. if (desc->host_addr)
  315. pci_unmap_single(priv->pdev,
  316. le32_to_cpu(desc->host_addr),
  317. priv->common.rx_mtu + 32,
  318. PCI_DMA_FROMDEVICE);
  319. kfree_skb(priv->rx_buf_data[i]);
  320. priv->rx_buf_data[i] = NULL;
  321. }
  322. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  323. desc = &ring_control->rx_mgmt[i];
  324. if (desc->host_addr)
  325. pci_unmap_single(priv->pdev,
  326. le32_to_cpu(desc->host_addr),
  327. priv->common.rx_mtu + 32,
  328. PCI_DMA_FROMDEVICE);
  329. kfree_skb(priv->rx_buf_mgmt[i]);
  330. priv->rx_buf_mgmt[i] = NULL;
  331. }
  332. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  333. desc = &ring_control->tx_data[i];
  334. if (desc->host_addr)
  335. pci_unmap_single(priv->pdev,
  336. le32_to_cpu(desc->host_addr),
  337. le16_to_cpu(desc->len),
  338. PCI_DMA_TODEVICE);
  339. p54_free_skb(dev, priv->tx_buf_data[i]);
  340. priv->tx_buf_data[i] = NULL;
  341. }
  342. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  343. desc = &ring_control->tx_mgmt[i];
  344. if (desc->host_addr)
  345. pci_unmap_single(priv->pdev,
  346. le32_to_cpu(desc->host_addr),
  347. le16_to_cpu(desc->len),
  348. PCI_DMA_TODEVICE);
  349. p54_free_skb(dev, priv->tx_buf_mgmt[i]);
  350. priv->tx_buf_mgmt[i] = NULL;
  351. }
  352. memset(ring_control, 0, sizeof(*ring_control));
  353. }
  354. static int p54p_open(struct ieee80211_hw *dev)
  355. {
  356. struct p54p_priv *priv = dev->priv;
  357. int err;
  358. init_completion(&priv->boot_comp);
  359. err = request_irq(priv->pdev->irq, p54p_interrupt,
  360. IRQF_SHARED, "p54pci", dev);
  361. if (err) {
  362. dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
  363. return err;
  364. }
  365. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  366. err = p54p_upload_firmware(dev);
  367. if (err) {
  368. free_irq(priv->pdev->irq, dev);
  369. return err;
  370. }
  371. priv->rx_idx_data = priv->tx_idx_data = 0;
  372. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  373. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  374. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
  375. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  376. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
  377. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  378. P54P_READ(ring_control_base);
  379. wmb();
  380. udelay(10);
  381. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  382. P54P_READ(int_enable);
  383. wmb();
  384. udelay(10);
  385. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  386. P54P_READ(dev_int);
  387. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  388. wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
  389. p54p_stop(dev);
  390. return -ETIMEDOUT;
  391. }
  392. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  393. P54P_READ(int_enable);
  394. wmb();
  395. udelay(10);
  396. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  397. P54P_READ(dev_int);
  398. wmb();
  399. udelay(10);
  400. return 0;
  401. }
  402. static int __devinit p54p_probe(struct pci_dev *pdev,
  403. const struct pci_device_id *id)
  404. {
  405. struct p54p_priv *priv;
  406. struct ieee80211_hw *dev;
  407. unsigned long mem_addr, mem_len;
  408. int err;
  409. err = pci_enable_device(pdev);
  410. if (err) {
  411. dev_err(&pdev->dev, "Cannot enable new PCI device\n");
  412. return err;
  413. }
  414. mem_addr = pci_resource_start(pdev, 0);
  415. mem_len = pci_resource_len(pdev, 0);
  416. if (mem_len < sizeof(struct p54p_csr)) {
  417. dev_err(&pdev->dev, "Too short PCI resources\n");
  418. goto err_disable_dev;
  419. }
  420. err = pci_request_regions(pdev, "p54pci");
  421. if (err) {
  422. dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
  423. goto err_disable_dev;
  424. }
  425. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
  426. pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  427. dev_err(&pdev->dev, "No suitable DMA available\n");
  428. goto err_free_reg;
  429. }
  430. pci_set_master(pdev);
  431. pci_try_set_mwi(pdev);
  432. pci_write_config_byte(pdev, 0x40, 0);
  433. pci_write_config_byte(pdev, 0x41, 0);
  434. dev = p54_init_common(sizeof(*priv));
  435. if (!dev) {
  436. dev_err(&pdev->dev, "ieee80211 alloc failed\n");
  437. err = -ENOMEM;
  438. goto err_free_reg;
  439. }
  440. priv = dev->priv;
  441. priv->pdev = pdev;
  442. SET_IEEE80211_DEV(dev, &pdev->dev);
  443. pci_set_drvdata(pdev, dev);
  444. priv->map = ioremap(mem_addr, mem_len);
  445. if (!priv->map) {
  446. dev_err(&pdev->dev, "Cannot map device memory\n");
  447. err = -ENOMEM;
  448. goto err_free_dev;
  449. }
  450. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  451. &priv->ring_control_dma);
  452. if (!priv->ring_control) {
  453. dev_err(&pdev->dev, "Cannot allocate rings\n");
  454. err = -ENOMEM;
  455. goto err_iounmap;
  456. }
  457. priv->common.open = p54p_open;
  458. priv->common.stop = p54p_stop;
  459. priv->common.tx = p54p_tx;
  460. spin_lock_init(&priv->lock);
  461. tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
  462. err = request_firmware(&priv->firmware, "isl3886pci",
  463. &priv->pdev->dev);
  464. if (err) {
  465. dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
  466. err = request_firmware(&priv->firmware, "isl3886",
  467. &priv->pdev->dev);
  468. if (err)
  469. goto err_free_common;
  470. }
  471. err = p54p_open(dev);
  472. if (err)
  473. goto err_free_common;
  474. err = p54_read_eeprom(dev);
  475. p54p_stop(dev);
  476. if (err)
  477. goto err_free_common;
  478. err = p54_register_common(dev, &pdev->dev);
  479. if (err)
  480. goto err_free_common;
  481. return 0;
  482. err_free_common:
  483. release_firmware(priv->firmware);
  484. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  485. priv->ring_control, priv->ring_control_dma);
  486. err_iounmap:
  487. iounmap(priv->map);
  488. err_free_dev:
  489. pci_set_drvdata(pdev, NULL);
  490. p54_free_common(dev);
  491. err_free_reg:
  492. pci_release_regions(pdev);
  493. err_disable_dev:
  494. pci_disable_device(pdev);
  495. return err;
  496. }
  497. static void __devexit p54p_remove(struct pci_dev *pdev)
  498. {
  499. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  500. struct p54p_priv *priv;
  501. if (!dev)
  502. return;
  503. p54_unregister_common(dev);
  504. priv = dev->priv;
  505. release_firmware(priv->firmware);
  506. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  507. priv->ring_control, priv->ring_control_dma);
  508. iounmap(priv->map);
  509. pci_release_regions(pdev);
  510. pci_disable_device(pdev);
  511. p54_free_common(dev);
  512. }
  513. #ifdef CONFIG_PM
  514. static int p54p_suspend(struct device *device)
  515. {
  516. struct pci_dev *pdev = to_pci_dev(device);
  517. pci_save_state(pdev);
  518. pci_set_power_state(pdev, PCI_D3hot);
  519. pci_disable_device(pdev);
  520. return 0;
  521. }
  522. static int p54p_resume(struct device *device)
  523. {
  524. struct pci_dev *pdev = to_pci_dev(device);
  525. int err;
  526. err = pci_reenable_device(pdev);
  527. if (err)
  528. return err;
  529. return pci_set_power_state(pdev, PCI_D0);
  530. }
  531. static const struct dev_pm_ops p54pci_pm_ops = {
  532. .suspend = p54p_suspend,
  533. .resume = p54p_resume,
  534. .freeze = p54p_suspend,
  535. .thaw = p54p_resume,
  536. .poweroff = p54p_suspend,
  537. .restore = p54p_resume,
  538. };
  539. #define P54P_PM_OPS (&p54pci_pm_ops)
  540. #else
  541. #define P54P_PM_OPS (NULL)
  542. #endif /* CONFIG_PM */
  543. static struct pci_driver p54p_driver = {
  544. .name = "p54pci",
  545. .id_table = p54p_table,
  546. .probe = p54p_probe,
  547. .remove = __devexit_p(p54p_remove),
  548. .driver.pm = P54P_PM_OPS,
  549. };
  550. static int __init p54p_init(void)
  551. {
  552. return pci_register_driver(&p54p_driver);
  553. }
  554. static void __exit p54p_exit(void)
  555. {
  556. pci_unregister_driver(&p54p_driver);
  557. }
  558. module_init(p54p_init);
  559. module_exit(p54p_exit);