3c359.c 58 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844
  1. /*
  2. * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
  3. *
  4. * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
  5. *
  6. * Base Driver Olympic:
  7. * Written 1999 Peter De Schrijver & Mike Phillips
  8. *
  9. * This software may be used and distributed according to the terms
  10. * of the GNU General Public License, incorporated herein by reference.
  11. *
  12. * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
  13. *
  14. * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
  15. * 3/05/01 - Last clean up stuff before submission.
  16. * 2/15/01 - Finally, update to new pci api.
  17. *
  18. * To Do:
  19. */
  20. /*
  21. * Technical Card Details
  22. *
  23. * All access to data is done with 16/8 bit transfers. The transfer
  24. * method really sucks. You can only read or write one location at a time.
  25. *
  26. * Also, the microcode for the card must be uploaded if the card does not have
  27. * the flashrom on board. This is a 28K bloat in the driver when compiled
  28. * as a module.
  29. *
  30. * Rx is very simple, status into a ring of descriptors, dma data transfer,
  31. * interrupts to tell us when a packet is received.
  32. *
  33. * Tx is a little more interesting. Similar scenario, descriptor and dma data
  34. * transfers, but we don't have to interrupt the card to tell it another packet
  35. * is ready for transmission, we are just doing simple memory writes, not io or mmio
  36. * writes. The card can be set up to simply poll on the next
  37. * descriptor pointer and when this value is non-zero will automatically download
  38. * the next packet. The card then interrupts us when the packet is done.
  39. *
  40. */
  41. #define XL_DEBUG 0
  42. #include <linux/jiffies.h>
  43. #include <linux/module.h>
  44. #include <linux/kernel.h>
  45. #include <linux/errno.h>
  46. #include <linux/timer.h>
  47. #include <linux/in.h>
  48. #include <linux/ioport.h>
  49. #include <linux/string.h>
  50. #include <linux/proc_fs.h>
  51. #include <linux/ptrace.h>
  52. #include <linux/skbuff.h>
  53. #include <linux/interrupt.h>
  54. #include <linux/delay.h>
  55. #include <linux/netdevice.h>
  56. #include <linux/trdevice.h>
  57. #include <linux/stddef.h>
  58. #include <linux/init.h>
  59. #include <linux/pci.h>
  60. #include <linux/spinlock.h>
  61. #include <linux/bitops.h>
  62. #include <linux/firmware.h>
  63. #include <linux/slab.h>
  64. #include <net/checksum.h>
  65. #include <asm/io.h>
  66. #include "3c359.h"
  67. static char version[] __devinitdata =
  68. "3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
  69. #define FW_NAME "3com/3C359.bin"
  70. MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
  71. MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver\n") ;
  72. MODULE_FIRMWARE(FW_NAME);
  73. /* Module parameters */
  74. /* Ring Speed 0,4,16
  75. * 0 = Autosense
  76. * 4,16 = Selected speed only, no autosense
  77. * This allows the card to be the first on the ring
  78. * and become the active monitor.
  79. *
  80. * WARNING: Some hubs will allow you to insert
  81. * at the wrong speed.
  82. *
  83. * The adapter will _not_ fail to open if there are no
  84. * active monitors on the ring, it will simply open up in
  85. * its last known ringspeed if no ringspeed is specified.
  86. */
  87. static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
  88. module_param_array(ringspeed, int, NULL, 0);
  89. MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
  90. /* Packet buffer size */
  91. static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
  92. module_param_array(pkt_buf_sz, int, NULL, 0) ;
  93. MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
  94. /* Message Level */
  95. static int message_level[XL_MAX_ADAPTERS] = {0,} ;
  96. module_param_array(message_level, int, NULL, 0) ;
  97. MODULE_PARM_DESC(message_level, "3c359: Level of reported messages") ;
  98. /*
  99. * This is a real nasty way of doing this, but otherwise you
  100. * will be stuck with 1555 lines of hex #'s in the code.
  101. */
  102. static DEFINE_PCI_DEVICE_TABLE(xl_pci_tbl) =
  103. {
  104. {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
  105. { } /* terminate list */
  106. };
  107. MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
  108. static int xl_init(struct net_device *dev);
  109. static int xl_open(struct net_device *dev);
  110. static int xl_open_hw(struct net_device *dev) ;
  111. static int xl_hw_reset(struct net_device *dev);
  112. static netdev_tx_t xl_xmit(struct sk_buff *skb, struct net_device *dev);
  113. static void xl_dn_comp(struct net_device *dev);
  114. static int xl_close(struct net_device *dev);
  115. static void xl_set_rx_mode(struct net_device *dev);
  116. static irqreturn_t xl_interrupt(int irq, void *dev_id);
  117. static int xl_set_mac_address(struct net_device *dev, void *addr) ;
  118. static void xl_arb_cmd(struct net_device *dev);
  119. static void xl_asb_cmd(struct net_device *dev) ;
  120. static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
  121. static void xl_wait_misr_flags(struct net_device *dev) ;
  122. static int xl_change_mtu(struct net_device *dev, int mtu);
  123. static void xl_srb_bh(struct net_device *dev) ;
  124. static void xl_asb_bh(struct net_device *dev) ;
  125. static void xl_reset(struct net_device *dev) ;
  126. static void xl_freemem(struct net_device *dev) ;
  127. /* EEProm Access Functions */
  128. static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
  129. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
  130. /* Debugging functions */
  131. #if XL_DEBUG
  132. static void print_tx_state(struct net_device *dev) ;
  133. static void print_rx_state(struct net_device *dev) ;
  134. static void print_tx_state(struct net_device *dev)
  135. {
  136. struct xl_private *xl_priv = netdev_priv(dev);
  137. struct xl_tx_desc *txd ;
  138. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  139. int i ;
  140. printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d\n",xl_priv->tx_ring_head,
  141. xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
  142. printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len\n");
  143. for (i = 0; i < 16; i++) {
  144. txd = &(xl_priv->xl_tx_ring[i]) ;
  145. printk("%d, %08lx, %08x, %08x, %08x, %08x\n", i, virt_to_bus(txd),
  146. txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
  147. }
  148. printk("DNLISTPTR = %04x\n", readl(xl_mmio + MMIO_DNLISTPTR) );
  149. printk("DmaCtl = %04x\n", readl(xl_mmio + MMIO_DMA_CTRL) );
  150. printk("Queue status = %0x\n",netif_running(dev) ) ;
  151. }
  152. static void print_rx_state(struct net_device *dev)
  153. {
  154. struct xl_private *xl_priv = netdev_priv(dev);
  155. struct xl_rx_desc *rxd ;
  156. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  157. int i ;
  158. printk("rx_ring_tail: %d\n", xl_priv->rx_ring_tail);
  159. printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len\n");
  160. for (i = 0; i < 16; i++) {
  161. /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
  162. rxd = &(xl_priv->xl_rx_ring[i]) ;
  163. printk("%d, %08lx, %08x, %08x, %08x, %08x\n", i, virt_to_bus(rxd),
  164. rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
  165. }
  166. printk("UPLISTPTR = %04x\n", readl(xl_mmio + MMIO_UPLISTPTR));
  167. printk("DmaCtl = %04x\n", readl(xl_mmio + MMIO_DMA_CTRL));
  168. printk("Queue status = %0x\n",netif_running(dev));
  169. }
  170. #endif
  171. /*
  172. * Read values from the on-board EEProm. This looks very strange
  173. * but you have to wait for the EEProm to get/set the value before
  174. * passing/getting the next value from the nic. As with all requests
  175. * on this nic it has to be done in two stages, a) tell the nic which
  176. * memory address you want to access and b) pass/get the value from the nic.
  177. * With the EEProm, you have to wait before and between access a) and b).
  178. * As this is only read at initialization time and the wait period is very
  179. * small we shouldn't have to worry about scheduling issues.
  180. */
  181. static u16 xl_ee_read(struct net_device *dev, int ee_addr)
  182. {
  183. struct xl_private *xl_priv = netdev_priv(dev);
  184. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  185. /* Wait for EEProm to not be busy */
  186. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  187. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  188. /* Tell EEProm what we want to do and where */
  189. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  190. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  191. /* Wait for EEProm to not be busy */
  192. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  193. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  194. /* Tell EEProm what we want to do and where */
  195. writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  196. writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
  197. /* Finally read the value from the EEProm */
  198. writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  199. return readw(xl_mmio + MMIO_MACDATA) ;
  200. }
  201. /*
  202. * Write values to the onboard eeprom. As with eeprom read you need to
  203. * set which location to write, wait, value to write, wait, with the
  204. * added twist of having to enable eeprom writes as well.
  205. */
  206. static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
  207. {
  208. struct xl_private *xl_priv = netdev_priv(dev);
  209. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  210. /* Wait for EEProm to not be busy */
  211. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  212. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  213. /* Enable write/erase */
  214. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  215. writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
  216. /* Wait for EEProm to not be busy */
  217. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  218. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  219. /* Put the value we want to write into EEDATA */
  220. writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  221. writew(ee_value, xl_mmio + MMIO_MACDATA) ;
  222. /* Tell EEProm to write eevalue into ee_addr */
  223. writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  224. writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
  225. /* Wait for EEProm to not be busy, to ensure write gets done */
  226. writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  227. while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
  228. return ;
  229. }
  230. static const struct net_device_ops xl_netdev_ops = {
  231. .ndo_open = xl_open,
  232. .ndo_stop = xl_close,
  233. .ndo_start_xmit = xl_xmit,
  234. .ndo_change_mtu = xl_change_mtu,
  235. .ndo_set_rx_mode = xl_set_rx_mode,
  236. .ndo_set_mac_address = xl_set_mac_address,
  237. };
  238. static int __devinit xl_probe(struct pci_dev *pdev,
  239. const struct pci_device_id *ent)
  240. {
  241. struct net_device *dev ;
  242. struct xl_private *xl_priv ;
  243. static int card_no = -1 ;
  244. int i ;
  245. card_no++ ;
  246. if (pci_enable_device(pdev)) {
  247. return -ENODEV ;
  248. }
  249. pci_set_master(pdev);
  250. if ((i = pci_request_regions(pdev,"3c359"))) {
  251. return i ;
  252. }
  253. /*
  254. * Allowing init_trdev to allocate the private data will align
  255. * xl_private on a 32 bytes boundary which we need for the rx/tx
  256. * descriptors
  257. */
  258. dev = alloc_trdev(sizeof(struct xl_private)) ;
  259. if (!dev) {
  260. pci_release_regions(pdev) ;
  261. return -ENOMEM ;
  262. }
  263. xl_priv = netdev_priv(dev);
  264. #if XL_DEBUG
  265. printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
  266. pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start);
  267. #endif
  268. dev->irq=pdev->irq;
  269. dev->base_addr=pci_resource_start(pdev,0) ;
  270. xl_priv->xl_card_name = pci_name(pdev);
  271. xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
  272. xl_priv->pdev = pdev ;
  273. if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
  274. xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
  275. else
  276. xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
  277. dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
  278. xl_priv->xl_ring_speed = ringspeed[card_no] ;
  279. xl_priv->xl_message_level = message_level[card_no] ;
  280. xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
  281. xl_priv->xl_copy_all_options = 0 ;
  282. if((i = xl_init(dev))) {
  283. iounmap(xl_priv->xl_mmio) ;
  284. free_netdev(dev) ;
  285. pci_release_regions(pdev) ;
  286. return i ;
  287. }
  288. dev->netdev_ops = &xl_netdev_ops;
  289. SET_NETDEV_DEV(dev, &pdev->dev);
  290. pci_set_drvdata(pdev,dev) ;
  291. if ((i = register_netdev(dev))) {
  292. printk(KERN_ERR "3C359, register netdev failed\n") ;
  293. pci_set_drvdata(pdev,NULL) ;
  294. iounmap(xl_priv->xl_mmio) ;
  295. free_netdev(dev) ;
  296. pci_release_regions(pdev) ;
  297. return i ;
  298. }
  299. printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
  300. return 0;
  301. }
  302. static int xl_init_firmware(struct xl_private *xl_priv)
  303. {
  304. int err;
  305. err = request_firmware(&xl_priv->fw, FW_NAME, &xl_priv->pdev->dev);
  306. if (err) {
  307. printk(KERN_ERR "Failed to load firmware \"%s\"\n", FW_NAME);
  308. return err;
  309. }
  310. if (xl_priv->fw->size < 16) {
  311. printk(KERN_ERR "Bogus length %zu in \"%s\"\n",
  312. xl_priv->fw->size, FW_NAME);
  313. release_firmware(xl_priv->fw);
  314. err = -EINVAL;
  315. }
  316. return err;
  317. }
  318. static int __devinit xl_init(struct net_device *dev)
  319. {
  320. struct xl_private *xl_priv = netdev_priv(dev);
  321. int err;
  322. printk(KERN_INFO "%s\n", version);
  323. printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
  324. xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
  325. spin_lock_init(&xl_priv->xl_lock) ;
  326. err = xl_init_firmware(xl_priv);
  327. if (err == 0)
  328. err = xl_hw_reset(dev);
  329. return err;
  330. }
  331. /*
  332. * Hardware reset. This needs to be a separate entity as we need to reset the card
  333. * when we change the EEProm settings.
  334. */
  335. static int xl_hw_reset(struct net_device *dev)
  336. {
  337. struct xl_private *xl_priv = netdev_priv(dev);
  338. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  339. unsigned long t ;
  340. u16 i ;
  341. u16 result_16 ;
  342. u8 result_8 ;
  343. u16 start ;
  344. int j ;
  345. if (xl_priv->fw == NULL)
  346. return -EINVAL;
  347. /*
  348. * Reset the card. If the card has got the microcode on board, we have
  349. * missed the initialization interrupt, so we must always do this.
  350. */
  351. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  352. /*
  353. * Must wait for cmdInProgress bit (12) to clear before continuing with
  354. * card configuration.
  355. */
  356. t=jiffies;
  357. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  358. schedule();
  359. if (time_after(jiffies, t + 40 * HZ)) {
  360. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
  361. return -ENODEV;
  362. }
  363. }
  364. /*
  365. * Enable pmbar by setting bit in CPAttention
  366. */
  367. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  368. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  369. result_8 = result_8 | CPA_PMBARVIS ;
  370. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  371. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  372. /*
  373. * Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
  374. * If not, we need to upload the microcode to the card
  375. */
  376. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  377. #if XL_DEBUG
  378. printk(KERN_INFO "Read from PMBAR = %04x\n", readw(xl_mmio + MMIO_MACDATA));
  379. #endif
  380. if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
  381. /* Set PmBar, privateMemoryBase bits (8:2) to 0 */
  382. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  383. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  384. result_16 = result_16 & ~((0x7F) << 2) ;
  385. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  386. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  387. /* Set CPAttention, memWrEn bit */
  388. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  389. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  390. result_8 = result_8 | CPA_MEMWREN ;
  391. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  392. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  393. /*
  394. * Now to write the microcode into the shared ram
  395. * The microcode must finish at position 0xFFFF,
  396. * so we must subtract to get the start position for the code
  397. *
  398. * Looks strange but ensures compiler only uses
  399. * 16 bit unsigned int
  400. */
  401. start = (0xFFFF - (xl_priv->fw->size) + 1) ;
  402. printk(KERN_INFO "3C359: Uploading Microcode: ");
  403. for (i = start, j = 0; j < xl_priv->fw->size; i++, j++) {
  404. writel(MEM_BYTE_WRITE | 0XD0000 | i,
  405. xl_mmio + MMIO_MAC_ACCESS_CMD);
  406. writeb(xl_priv->fw->data[j], xl_mmio + MMIO_MACDATA);
  407. if (j % 1024 == 0)
  408. printk(".");
  409. }
  410. printk("\n") ;
  411. for (i = 0; i < 16; i++) {
  412. writel((MEM_BYTE_WRITE | 0xDFFF0) + i,
  413. xl_mmio + MMIO_MAC_ACCESS_CMD);
  414. writeb(xl_priv->fw->data[xl_priv->fw->size - 16 + i],
  415. xl_mmio + MMIO_MACDATA);
  416. }
  417. /*
  418. * Have to write the start address of the upload to FFF4, but
  419. * the address must be >> 4. You do not want to know how long
  420. * it took me to discover this.
  421. */
  422. writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  423. writew(start >> 4, xl_mmio + MMIO_MACDATA);
  424. /* Clear the CPAttention, memWrEn Bit */
  425. writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  426. result_8 = readb(xl_mmio + MMIO_MACDATA) ;
  427. result_8 = result_8 & ~CPA_MEMWREN ;
  428. writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  429. writeb(result_8, xl_mmio + MMIO_MACDATA) ;
  430. /* Clear the cpHold bit in pmbar */
  431. writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
  432. result_16 = readw(xl_mmio + MMIO_MACDATA) ;
  433. result_16 = result_16 & ~PMB_CPHOLD ;
  434. writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  435. writew(result_16,xl_mmio + MMIO_MACDATA) ;
  436. } /* If microcode upload required */
  437. /*
  438. * The card should now go though a self test procedure and get itself ready
  439. * to be opened, we must wait for an srb response with the initialization
  440. * information.
  441. */
  442. #if XL_DEBUG
  443. printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
  444. #endif
  445. writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
  446. t=jiffies;
  447. while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
  448. schedule();
  449. if (time_after(jiffies, t + 15 * HZ)) {
  450. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  451. return -ENODEV;
  452. }
  453. }
  454. /*
  455. * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
  456. * DnPriReqThresh, read the tech docs if you want to know what
  457. * values they need to be.
  458. */
  459. writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  460. writew(0xD000, xl_mmio + MMIO_MACDATA) ;
  461. writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  462. writew(0X0020, xl_mmio + MMIO_MACDATA) ;
  463. writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
  464. writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
  465. writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
  466. /*
  467. * Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
  468. * Tech docs have this wrong !!!!
  469. */
  470. writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  471. xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  472. writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  473. xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
  474. #if XL_DEBUG
  475. writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  476. if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
  477. printk(KERN_INFO "Default ring speed 4 mbps\n");
  478. } else {
  479. printk(KERN_INFO "Default ring speed 16 mbps\n");
  480. }
  481. printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
  482. #endif
  483. return 0;
  484. }
  485. static int xl_open(struct net_device *dev)
  486. {
  487. struct xl_private *xl_priv=netdev_priv(dev);
  488. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  489. u8 i ;
  490. __le16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
  491. int open_err ;
  492. u16 switchsettings, switchsettings_eeprom ;
  493. if (request_irq(dev->irq, xl_interrupt, IRQF_SHARED , "3c359", dev))
  494. return -EAGAIN;
  495. /*
  496. * Read the information from the EEPROM that we need.
  497. */
  498. hwaddr[0] = cpu_to_le16(xl_ee_read(dev,0x10));
  499. hwaddr[1] = cpu_to_le16(xl_ee_read(dev,0x11));
  500. hwaddr[2] = cpu_to_le16(xl_ee_read(dev,0x12));
  501. /* Ring speed */
  502. switchsettings_eeprom = xl_ee_read(dev,0x08) ;
  503. switchsettings = switchsettings_eeprom ;
  504. if (xl_priv->xl_ring_speed != 0) {
  505. if (xl_priv->xl_ring_speed == 4)
  506. switchsettings = switchsettings | 0x02 ;
  507. else
  508. switchsettings = switchsettings & ~0x02 ;
  509. }
  510. /* Only write EEProm if there has been a change */
  511. if (switchsettings != switchsettings_eeprom) {
  512. xl_ee_write(dev,0x08,switchsettings) ;
  513. /* Hardware reset after changing EEProm */
  514. xl_hw_reset(dev) ;
  515. }
  516. memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
  517. open_err = xl_open_hw(dev) ;
  518. /*
  519. * This really needs to be cleaned up with better error reporting.
  520. */
  521. if (open_err != 0) { /* Something went wrong with the open command */
  522. if (open_err & 0x07) { /* Wrong speed, retry at different speed */
  523. printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed\n", dev->name);
  524. switchsettings = switchsettings ^ 2 ;
  525. xl_ee_write(dev,0x08,switchsettings) ;
  526. xl_hw_reset(dev) ;
  527. open_err = xl_open_hw(dev) ;
  528. if (open_err != 0) {
  529. printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
  530. free_irq(dev->irq,dev) ;
  531. return -ENODEV ;
  532. }
  533. } else {
  534. printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
  535. free_irq(dev->irq,dev) ;
  536. return -ENODEV ;
  537. }
  538. }
  539. /*
  540. * Now to set up the Rx and Tx buffer structures
  541. */
  542. /* These MUST be on 8 byte boundaries */
  543. xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL);
  544. if (xl_priv->xl_tx_ring == NULL) {
  545. free_irq(dev->irq,dev);
  546. return -ENOMEM;
  547. }
  548. xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL);
  549. if (xl_priv->xl_rx_ring == NULL) {
  550. free_irq(dev->irq,dev);
  551. kfree(xl_priv->xl_tx_ring);
  552. return -ENOMEM;
  553. }
  554. /* Setup Rx Ring */
  555. for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
  556. struct sk_buff *skb ;
  557. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  558. if (skb==NULL)
  559. break ;
  560. skb->dev = dev ;
  561. xl_priv->xl_rx_ring[i].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
  562. xl_priv->xl_rx_ring[i].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
  563. xl_priv->rx_ring_skb[i] = skb ;
  564. }
  565. if (i==0) {
  566. printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled\n",dev->name);
  567. free_irq(dev->irq,dev) ;
  568. kfree(xl_priv->xl_tx_ring);
  569. kfree(xl_priv->xl_rx_ring);
  570. return -EIO ;
  571. }
  572. xl_priv->rx_ring_no = i ;
  573. xl_priv->rx_ring_tail = 0 ;
  574. xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
  575. for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
  576. xl_priv->xl_rx_ring[i].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)));
  577. }
  578. xl_priv->xl_rx_ring[i].upnextptr = 0 ;
  579. writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
  580. /* Setup Tx Ring */
  581. xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
  582. xl_priv->tx_ring_head = 1 ;
  583. xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
  584. xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
  585. /*
  586. * Setup the first dummy DPD entry for polling to start working.
  587. */
  588. xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY;
  589. xl_priv->xl_tx_ring[0].buffer = 0 ;
  590. xl_priv->xl_tx_ring[0].buffer_length = 0 ;
  591. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  592. writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
  593. writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
  594. writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
  595. writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
  596. writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
  597. /*
  598. * Enable interrupts on the card
  599. */
  600. writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  601. writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  602. netif_start_queue(dev) ;
  603. return 0;
  604. }
  605. static int xl_open_hw(struct net_device *dev)
  606. {
  607. struct xl_private *xl_priv=netdev_priv(dev);
  608. u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
  609. u16 vsoff ;
  610. char ver_str[33];
  611. int open_err ;
  612. int i ;
  613. unsigned long t ;
  614. /*
  615. * Okay, let's build up the Open.NIC srb command
  616. *
  617. */
  618. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  619. writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
  620. /*
  621. * Use this as a test byte, if it comes back with the same value, the command didn't work
  622. */
  623. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  624. writeb(0xff,xl_mmio + MMIO_MACDATA) ;
  625. /* Open options */
  626. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  627. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  628. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  629. writeb(0x00, xl_mmio + MMIO_MACDATA) ;
  630. /*
  631. * Node address, be careful here, the docs say you can just put zeros here and it will use
  632. * the hardware address, it doesn't, you must include the node address in the open command.
  633. */
  634. if (xl_priv->xl_laa[0]) { /* If using a LAA address */
  635. for (i=10;i<16;i++) {
  636. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  637. writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ;
  638. }
  639. memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
  640. } else { /* Regular hardware address */
  641. for (i=10;i<16;i++) {
  642. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  643. writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
  644. }
  645. }
  646. /* Default everything else to 0 */
  647. for (i = 16; i < 34; i++) {
  648. writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  649. writeb(0x00,xl_mmio + MMIO_MACDATA) ;
  650. }
  651. /*
  652. * Set the csrb bit in the MISR register
  653. */
  654. xl_wait_misr_flags(dev) ;
  655. writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  656. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  657. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  658. writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
  659. /*
  660. * Now wait for the command to run
  661. */
  662. t=jiffies;
  663. while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  664. schedule();
  665. if (time_after(jiffies, t + 40 * HZ)) {
  666. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  667. break ;
  668. }
  669. }
  670. /*
  671. * Let's interpret the open response
  672. */
  673. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  674. if (readb(xl_mmio + MMIO_MACDATA)!=0) {
  675. open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
  676. writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  677. open_err |= readb(xl_mmio + MMIO_MACDATA) ;
  678. return open_err ;
  679. } else {
  680. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  681. xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  682. printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
  683. printk("ASB: %04x",xl_priv->asb ) ;
  684. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  685. printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ;
  686. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  687. xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  688. printk(", ARB: %04x\n",xl_priv->arb );
  689. writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  690. vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  691. /*
  692. * Interesting, sending the individual characters directly to printk was causing klogd to use
  693. * use 100% of processor time, so we build up the string and print that instead.
  694. */
  695. for (i=0;i<0x20;i++) {
  696. writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  697. ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
  698. }
  699. ver_str[i] = '\0' ;
  700. printk(KERN_INFO "%s: Microcode version String: %s\n",dev->name,ver_str);
  701. }
  702. /*
  703. * Issue the AckInterrupt
  704. */
  705. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  706. return 0 ;
  707. }
  708. /*
  709. * There are two ways of implementing rx on the 359 NIC, either
  710. * interrupt driven or polling. We are going to uses interrupts,
  711. * it is the easier way of doing things.
  712. *
  713. * The Rx works with a ring of Rx descriptors. At initialise time the ring
  714. * entries point to the next entry except for the last entry in the ring
  715. * which points to 0. The card is programmed with the location of the first
  716. * available descriptor and keeps reading the next_ptr until next_ptr is set
  717. * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
  718. * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
  719. * and then point the end of the ring to our current position and point our current
  720. * position to 0, therefore making the current position the last position on the ring.
  721. * The last position on the ring therefore loops continually loops around the rx ring.
  722. *
  723. * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
  724. * expands as the card adds new packets and we go around eating the tail processing the
  725. * packets.)
  726. *
  727. * Undoubtably it could be streamlined and improved upon, but at the moment it works
  728. * and the fast path through the routine is fine.
  729. *
  730. * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
  731. * in xl_rx so would increase the size of the function significantly.
  732. */
  733. static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
  734. {
  735. struct xl_private *xl_priv=netdev_priv(dev);
  736. int n = xl_priv->rx_ring_tail;
  737. int prev_ring_loc;
  738. prev_ring_loc = (n + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
  739. xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * n));
  740. xl_priv->xl_rx_ring[n].framestatus = 0;
  741. xl_priv->xl_rx_ring[n].upnextptr = 0;
  742. xl_priv->rx_ring_tail++;
  743. xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1);
  744. }
  745. static void xl_rx(struct net_device *dev)
  746. {
  747. struct xl_private *xl_priv=netdev_priv(dev);
  748. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  749. struct sk_buff *skb, *skb2 ;
  750. int frame_length = 0, copy_len = 0 ;
  751. int temp_ring_loc ;
  752. /*
  753. * Receive the next frame, loop around the ring until all frames
  754. * have been received.
  755. */
  756. while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
  757. if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
  758. /*
  759. * This is a pain, you need to go through all the descriptors until the last one
  760. * for this frame to find the framelength
  761. */
  762. temp_ring_loc = xl_priv->rx_ring_tail ;
  763. while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
  764. temp_ring_loc++ ;
  765. temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
  766. }
  767. frame_length = le32_to_cpu(xl_priv->xl_rx_ring[temp_ring_loc].framestatus) & 0x7FFF;
  768. skb = dev_alloc_skb(frame_length) ;
  769. if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
  770. printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
  771. while (xl_priv->rx_ring_tail != temp_ring_loc)
  772. adv_rx_ring(dev) ;
  773. adv_rx_ring(dev) ; /* One more time just for luck :) */
  774. dev->stats.rx_dropped++ ;
  775. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  776. return ;
  777. }
  778. while (xl_priv->rx_ring_tail != temp_ring_loc) {
  779. copy_len = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen) & 0x7FFF;
  780. frame_length -= copy_len ;
  781. pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  782. skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
  783. skb_put(skb, copy_len),
  784. copy_len);
  785. pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  786. adv_rx_ring(dev) ;
  787. }
  788. /* Now we have found the last fragment */
  789. pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  790. skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
  791. skb_put(skb,copy_len), frame_length);
  792. /* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
  793. pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
  794. adv_rx_ring(dev) ;
  795. skb->protocol = tr_type_trans(skb,dev) ;
  796. netif_rx(skb) ;
  797. } else { /* Single Descriptor Used, simply swap buffers over, fast path */
  798. frame_length = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus) & 0x7FFF;
  799. skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
  800. if (skb==NULL) { /* Still need to fix the rx ring */
  801. printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer\n",dev->name);
  802. adv_rx_ring(dev) ;
  803. dev->stats.rx_dropped++ ;
  804. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  805. return ;
  806. }
  807. skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
  808. pci_unmap_single(xl_priv->pdev, le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
  809. skb_put(skb2, frame_length) ;
  810. skb2->protocol = tr_type_trans(skb2,dev) ;
  811. xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
  812. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
  813. xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
  814. adv_rx_ring(dev) ;
  815. dev->stats.rx_packets++ ;
  816. dev->stats.rx_bytes += frame_length ;
  817. netif_rx(skb2) ;
  818. } /* if multiple buffers */
  819. } /* while packet to do */
  820. /* Clear the updComplete interrupt */
  821. writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  822. return ;
  823. }
  824. /*
  825. * This is ruthless, it doesn't care what state the card is in it will
  826. * completely reset the adapter.
  827. */
  828. static void xl_reset(struct net_device *dev)
  829. {
  830. struct xl_private *xl_priv=netdev_priv(dev);
  831. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  832. unsigned long t;
  833. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  834. /*
  835. * Must wait for cmdInProgress bit (12) to clear before continuing with
  836. * card configuration.
  837. */
  838. t=jiffies;
  839. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  840. if (time_after(jiffies, t + 40 * HZ)) {
  841. printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
  842. break ;
  843. }
  844. }
  845. }
  846. static void xl_freemem(struct net_device *dev)
  847. {
  848. struct xl_private *xl_priv=netdev_priv(dev);
  849. int i ;
  850. for (i=0;i<XL_RX_RING_SIZE;i++) {
  851. dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
  852. pci_unmap_single(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE);
  853. xl_priv->rx_ring_tail++ ;
  854. xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
  855. }
  856. /* unmap ring */
  857. pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
  858. pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
  859. kfree(xl_priv->xl_rx_ring) ;
  860. kfree(xl_priv->xl_tx_ring) ;
  861. return ;
  862. }
  863. static irqreturn_t xl_interrupt(int irq, void *dev_id)
  864. {
  865. struct net_device *dev = (struct net_device *)dev_id;
  866. struct xl_private *xl_priv =netdev_priv(dev);
  867. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  868. u16 intstatus, macstatus ;
  869. intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
  870. if (!(intstatus & 1)) /* We didn't generate the interrupt */
  871. return IRQ_NONE;
  872. spin_lock(&xl_priv->xl_lock) ;
  873. /*
  874. * Process the interrupt
  875. */
  876. /*
  877. * Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
  878. */
  879. if (intstatus == 0x0001) {
  880. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  881. printk(KERN_INFO "%s: 00001 int received\n",dev->name);
  882. } else {
  883. if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
  884. /*
  885. * Host Error.
  886. * It may be possible to recover from this, but usually it means something
  887. * is seriously fubar, so we just close the adapter.
  888. */
  889. if (intstatus & HOSTERRINT) {
  890. printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x\n",dev->name,intstatus);
  891. writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
  892. printk(KERN_WARNING "%s: Resetting hardware:\n", dev->name);
  893. netif_stop_queue(dev) ;
  894. xl_freemem(dev) ;
  895. free_irq(dev->irq,dev);
  896. xl_reset(dev) ;
  897. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  898. spin_unlock(&xl_priv->xl_lock) ;
  899. return IRQ_HANDLED;
  900. } /* Host Error */
  901. if (intstatus & SRBRINT ) { /* Srbc interrupt */
  902. writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  903. if (xl_priv->srb_queued)
  904. xl_srb_bh(dev) ;
  905. } /* SRBR Interrupt */
  906. if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
  907. writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  908. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
  909. /* !!! FIX-ME !!!!
  910. Must put a timeout check here ! */
  911. /* Empty Loop */
  912. }
  913. printk(KERN_WARNING "%s: TX Underrun received\n",dev->name);
  914. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  915. } /* TxUnderRun */
  916. if (intstatus & ARBCINT ) { /* Arbc interrupt */
  917. xl_arb_cmd(dev) ;
  918. } /* Arbc */
  919. if (intstatus & ASBFINT) {
  920. if (xl_priv->asb_queued == 1) {
  921. xl_asb_cmd(dev) ;
  922. } else if (xl_priv->asb_queued == 2) {
  923. xl_asb_bh(dev) ;
  924. } else {
  925. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  926. }
  927. } /* Asbf */
  928. if (intstatus & UPCOMPINT ) /* UpComplete */
  929. xl_rx(dev) ;
  930. if (intstatus & DNCOMPINT ) /* DnComplete */
  931. xl_dn_comp(dev) ;
  932. if (intstatus & HARDERRINT ) { /* Hardware error */
  933. writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  934. macstatus = readw(xl_mmio + MMIO_MACDATA) ;
  935. printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
  936. if (macstatus & (1<<14))
  937. printk(KERN_WARNING "tchk error: Unrecoverable error\n");
  938. if (macstatus & (1<<3))
  939. printk(KERN_WARNING "eint error: Internal watchdog timer expired\n");
  940. if (macstatus & (1<<2))
  941. printk(KERN_WARNING "aint error: Host tried to perform invalid operation\n");
  942. printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
  943. printk(KERN_WARNING "%s: Resetting hardware:\n", dev->name);
  944. netif_stop_queue(dev) ;
  945. xl_freemem(dev) ;
  946. free_irq(dev->irq,dev);
  947. unregister_netdev(dev) ;
  948. free_netdev(dev) ;
  949. xl_reset(dev) ;
  950. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  951. spin_unlock(&xl_priv->xl_lock) ;
  952. return IRQ_HANDLED;
  953. }
  954. } else {
  955. printk(KERN_WARNING "%s: Received Unknown interrupt : %04x\n", dev->name, intstatus);
  956. writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  957. }
  958. }
  959. /* Turn interrupts back on */
  960. writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  961. writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
  962. spin_unlock(&xl_priv->xl_lock) ;
  963. return IRQ_HANDLED;
  964. }
  965. /*
  966. * Tx - Polling configuration
  967. */
  968. static netdev_tx_t xl_xmit(struct sk_buff *skb, struct net_device *dev)
  969. {
  970. struct xl_private *xl_priv=netdev_priv(dev);
  971. struct xl_tx_desc *txd ;
  972. int tx_head, tx_tail, tx_prev ;
  973. unsigned long flags ;
  974. spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
  975. netif_stop_queue(dev) ;
  976. if (xl_priv->free_ring_entries > 1 ) {
  977. /*
  978. * Set up the descriptor for the packet
  979. */
  980. tx_head = xl_priv->tx_ring_head ;
  981. tx_tail = xl_priv->tx_ring_tail ;
  982. txd = &(xl_priv->xl_tx_ring[tx_head]) ;
  983. txd->dnnextptr = 0 ;
  984. txd->framestartheader = cpu_to_le32(skb->len) | TXDNINDICATE;
  985. txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE));
  986. txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST;
  987. xl_priv->tx_ring_skb[tx_head] = skb ;
  988. dev->stats.tx_packets++ ;
  989. dev->stats.tx_bytes += skb->len ;
  990. /*
  991. * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
  992. * to ensure no negative numbers in unsigned locations.
  993. */
  994. tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
  995. xl_priv->tx_ring_head++ ;
  996. xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
  997. xl_priv->free_ring_entries-- ;
  998. xl_priv->xl_tx_ring[tx_prev].dnnextptr = cpu_to_le32(xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head));
  999. /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
  1000. /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
  1001. netif_wake_queue(dev) ;
  1002. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  1003. return NETDEV_TX_OK;
  1004. } else {
  1005. spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
  1006. return NETDEV_TX_BUSY;
  1007. }
  1008. }
  1009. /*
  1010. * The NIC has told us that a packet has been downloaded onto the card, we must
  1011. * find out which packet it has done, clear the skb and information for the packet
  1012. * then advance around the ring for all transmitted packets
  1013. */
  1014. static void xl_dn_comp(struct net_device *dev)
  1015. {
  1016. struct xl_private *xl_priv=netdev_priv(dev);
  1017. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1018. struct xl_tx_desc *txd ;
  1019. if (xl_priv->tx_ring_tail == 255) {/* First time */
  1020. xl_priv->xl_tx_ring[0].framestartheader = 0 ;
  1021. xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
  1022. xl_priv->tx_ring_tail = 1 ;
  1023. }
  1024. while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
  1025. txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
  1026. pci_unmap_single(xl_priv->pdev, le32_to_cpu(txd->buffer), xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE);
  1027. txd->framestartheader = 0 ;
  1028. txd->buffer = cpu_to_le32(0xdeadbeef);
  1029. txd->buffer_length = 0 ;
  1030. dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
  1031. xl_priv->tx_ring_tail++ ;
  1032. xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
  1033. xl_priv->free_ring_entries++ ;
  1034. }
  1035. netif_wake_queue(dev) ;
  1036. writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1037. }
  1038. /*
  1039. * Close the adapter properly.
  1040. * This srb reply cannot be handled from interrupt context as we have
  1041. * to free the interrupt from the driver.
  1042. */
  1043. static int xl_close(struct net_device *dev)
  1044. {
  1045. struct xl_private *xl_priv = netdev_priv(dev);
  1046. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1047. unsigned long t ;
  1048. netif_stop_queue(dev) ;
  1049. /*
  1050. * Close the adapter, need to stall the rx and tx queues.
  1051. */
  1052. writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
  1053. t=jiffies;
  1054. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1055. schedule();
  1056. if (time_after(jiffies, t + 10 * HZ)) {
  1057. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
  1058. break ;
  1059. }
  1060. }
  1061. writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
  1062. t=jiffies;
  1063. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1064. schedule();
  1065. if (time_after(jiffies, t + 10 * HZ)) {
  1066. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
  1067. break ;
  1068. }
  1069. }
  1070. writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
  1071. t=jiffies;
  1072. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1073. schedule();
  1074. if (time_after(jiffies, t + 10 * HZ)) {
  1075. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
  1076. break ;
  1077. }
  1078. }
  1079. /* Turn off interrupts, we will still get the indication though
  1080. * so we can trap it
  1081. */
  1082. writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
  1083. xl_srb_cmd(dev,CLOSE_NIC) ;
  1084. t=jiffies;
  1085. while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
  1086. schedule();
  1087. if (time_after(jiffies, t + 10 * HZ)) {
  1088. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
  1089. break ;
  1090. }
  1091. }
  1092. /* Read the srb response from the adapter */
  1093. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1094. if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
  1095. printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response\n",dev->name);
  1096. } else {
  1097. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1098. if (readb(xl_mmio + MMIO_MACDATA)==0) {
  1099. printk(KERN_INFO "%s: Adapter has been closed\n",dev->name);
  1100. writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1101. xl_freemem(dev) ;
  1102. free_irq(dev->irq,dev) ;
  1103. } else {
  1104. printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
  1105. }
  1106. }
  1107. /* Reset the upload and download logic */
  1108. writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
  1109. t=jiffies;
  1110. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1111. schedule();
  1112. if (time_after(jiffies, t + 10 * HZ)) {
  1113. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
  1114. break ;
  1115. }
  1116. }
  1117. writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
  1118. t=jiffies;
  1119. while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
  1120. schedule();
  1121. if (time_after(jiffies, t + 10 * HZ)) {
  1122. printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
  1123. break ;
  1124. }
  1125. }
  1126. xl_hw_reset(dev) ;
  1127. return 0 ;
  1128. }
  1129. static void xl_set_rx_mode(struct net_device *dev)
  1130. {
  1131. struct xl_private *xl_priv = netdev_priv(dev);
  1132. struct netdev_hw_addr *ha;
  1133. unsigned char dev_mc_address[4] ;
  1134. u16 options ;
  1135. if (dev->flags & IFF_PROMISC)
  1136. options = 0x0004 ;
  1137. else
  1138. options = 0x0000 ;
  1139. if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
  1140. xl_priv->xl_copy_all_options = options ;
  1141. xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
  1142. return ;
  1143. }
  1144. dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
  1145. netdev_for_each_mc_addr(ha, dev) {
  1146. dev_mc_address[0] |= ha->addr[2];
  1147. dev_mc_address[1] |= ha->addr[3];
  1148. dev_mc_address[2] |= ha->addr[4];
  1149. dev_mc_address[3] |= ha->addr[5];
  1150. }
  1151. if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
  1152. memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
  1153. xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
  1154. }
  1155. return ;
  1156. }
  1157. /*
  1158. * We issued an srb command and now we must read
  1159. * the response from the completed command.
  1160. */
  1161. static void xl_srb_bh(struct net_device *dev)
  1162. {
  1163. struct xl_private *xl_priv = netdev_priv(dev);
  1164. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1165. u8 srb_cmd, ret_code ;
  1166. int i ;
  1167. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1168. srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1169. writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1170. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1171. /* Ret_code is standard across all commands */
  1172. switch (ret_code) {
  1173. case 1:
  1174. printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
  1175. break ;
  1176. case 4:
  1177. printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command\n",dev->name,srb_cmd);
  1178. break ;
  1179. case 6:
  1180. printk(KERN_INFO "%s: Command: %d - Options Invalid for command\n",dev->name,srb_cmd);
  1181. break ;
  1182. case 0: /* Successful command execution */
  1183. switch (srb_cmd) {
  1184. case READ_LOG: /* Returns 14 bytes of data from the NIC */
  1185. if(xl_priv->xl_message_level)
  1186. printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
  1187. /*
  1188. * We still have to read the log even if message_level = 0 and we don't want
  1189. * to see it
  1190. */
  1191. for (i=0;i<14;i++) {
  1192. writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1193. if(xl_priv->xl_message_level)
  1194. printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
  1195. }
  1196. printk("\n") ;
  1197. break ;
  1198. case SET_FUNC_ADDRESS:
  1199. if(xl_priv->xl_message_level)
  1200. printk(KERN_INFO "%s: Functional Address Set\n",dev->name);
  1201. break ;
  1202. case CLOSE_NIC:
  1203. if(xl_priv->xl_message_level)
  1204. printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler\n",dev->name);
  1205. break ;
  1206. case SET_MULTICAST_MODE:
  1207. if(xl_priv->xl_message_level)
  1208. printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
  1209. break ;
  1210. case SET_RECEIVE_MODE:
  1211. if(xl_priv->xl_message_level) {
  1212. if (xl_priv->xl_copy_all_options == 0x0004)
  1213. printk(KERN_INFO "%s: Entering promiscuous mode\n", dev->name);
  1214. else
  1215. printk(KERN_INFO "%s: Entering normal receive mode\n",dev->name);
  1216. }
  1217. break ;
  1218. } /* switch */
  1219. break ;
  1220. } /* switch */
  1221. return ;
  1222. }
  1223. static int xl_set_mac_address (struct net_device *dev, void *addr)
  1224. {
  1225. struct sockaddr *saddr = addr ;
  1226. struct xl_private *xl_priv = netdev_priv(dev);
  1227. if (netif_running(dev)) {
  1228. printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
  1229. return -EIO ;
  1230. }
  1231. memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
  1232. if (xl_priv->xl_message_level) {
  1233. printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
  1234. xl_priv->xl_laa[1], xl_priv->xl_laa[2],
  1235. xl_priv->xl_laa[3], xl_priv->xl_laa[4],
  1236. xl_priv->xl_laa[5]);
  1237. }
  1238. return 0 ;
  1239. }
  1240. static void xl_arb_cmd(struct net_device *dev)
  1241. {
  1242. struct xl_private *xl_priv = netdev_priv(dev);
  1243. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1244. u8 arb_cmd ;
  1245. u16 lan_status, lan_status_diff ;
  1246. writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1247. arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
  1248. if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
  1249. writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1250. printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ;
  1251. lan_status = swab16(readw(xl_mmio + MMIO_MACDATA));
  1252. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1253. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1254. lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
  1255. if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
  1256. if (lan_status_diff & LSC_LWF)
  1257. printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
  1258. if (lan_status_diff & LSC_ARW)
  1259. printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
  1260. if (lan_status_diff & LSC_FPE)
  1261. printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
  1262. if (lan_status_diff & LSC_RR)
  1263. printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
  1264. /* Adapter has been closed by the hardware */
  1265. netif_stop_queue(dev);
  1266. xl_freemem(dev) ;
  1267. free_irq(dev->irq,dev);
  1268. printk(KERN_WARNING "%s: Adapter has been closed\n", dev->name);
  1269. } /* If serious error */
  1270. if (xl_priv->xl_message_level) {
  1271. if (lan_status_diff & LSC_SIG_LOSS)
  1272. printk(KERN_WARNING "%s: No receive signal detected\n", dev->name);
  1273. if (lan_status_diff & LSC_HARD_ERR)
  1274. printk(KERN_INFO "%s: Beaconing\n",dev->name);
  1275. if (lan_status_diff & LSC_SOFT_ERR)
  1276. printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame\n",dev->name);
  1277. if (lan_status_diff & LSC_TRAN_BCN)
  1278. printk(KERN_INFO "%s: We are transmitting the beacon, aaah\n",dev->name);
  1279. if (lan_status_diff & LSC_SS)
  1280. printk(KERN_INFO "%s: Single Station on the ring\n", dev->name);
  1281. if (lan_status_diff & LSC_RING_REC)
  1282. printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
  1283. if (lan_status_diff & LSC_FDX_MODE)
  1284. printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
  1285. }
  1286. if (lan_status_diff & LSC_CO) {
  1287. if (xl_priv->xl_message_level)
  1288. printk(KERN_INFO "%s: Counter Overflow\n", dev->name);
  1289. /* Issue READ.LOG command */
  1290. xl_srb_cmd(dev, READ_LOG) ;
  1291. }
  1292. /* There is no command in the tech docs to issue the read_sr_counters */
  1293. if (lan_status_diff & LSC_SR_CO) {
  1294. if (xl_priv->xl_message_level)
  1295. printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
  1296. }
  1297. xl_priv->xl_lan_status = lan_status ;
  1298. } /* Lan.change.status */
  1299. else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
  1300. #if XL_DEBUG
  1301. printk(KERN_INFO "Received.Data\n");
  1302. #endif
  1303. writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1304. xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
  1305. /* Now we are going to be really basic here and not do anything
  1306. * with the data at all. The tech docs do not give me enough
  1307. * information to calculate the buffers properly so we're
  1308. * just going to tell the nic that we've dealt with the frame
  1309. * anyway.
  1310. */
  1311. /* Acknowledge interrupt, this tells nic we are done with the arb */
  1312. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
  1313. /* Is the ASB free ? */
  1314. xl_priv->asb_queued = 0 ;
  1315. writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1316. if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
  1317. xl_priv->asb_queued = 1 ;
  1318. xl_wait_misr_flags(dev) ;
  1319. writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1320. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1321. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1322. writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
  1323. return ;
  1324. /* Drop out and wait for the bottom half to be run */
  1325. }
  1326. xl_asb_cmd(dev) ;
  1327. } else {
  1328. printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x\n",dev->name,arb_cmd);
  1329. }
  1330. /* Acknowledge the arb interrupt */
  1331. writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
  1332. return ;
  1333. }
  1334. /*
  1335. * There is only one asb command, but we can get called from different
  1336. * places.
  1337. */
  1338. static void xl_asb_cmd(struct net_device *dev)
  1339. {
  1340. struct xl_private *xl_priv = netdev_priv(dev);
  1341. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1342. if (xl_priv->asb_queued == 1)
  1343. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1344. writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1345. writeb(0x81, xl_mmio + MMIO_MACDATA) ;
  1346. writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1347. writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
  1348. xl_wait_misr_flags(dev) ;
  1349. writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
  1350. writeb(0xff, xl_mmio + MMIO_MACDATA) ;
  1351. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1352. writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
  1353. xl_priv->asb_queued = 2 ;
  1354. return ;
  1355. }
  1356. /*
  1357. * This will only get called if there was an error
  1358. * from the asb cmd.
  1359. */
  1360. static void xl_asb_bh(struct net_device *dev)
  1361. {
  1362. struct xl_private *xl_priv = netdev_priv(dev);
  1363. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1364. u8 ret_code ;
  1365. writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1366. ret_code = readb(xl_mmio + MMIO_MACDATA) ;
  1367. switch (ret_code) {
  1368. case 0x01:
  1369. printk(KERN_INFO "%s: ASB Command, unrecognized command code\n",dev->name);
  1370. break ;
  1371. case 0x26:
  1372. printk(KERN_INFO "%s: ASB Command, unexpected receive buffer\n", dev->name);
  1373. break ;
  1374. case 0x40:
  1375. printk(KERN_INFO "%s: ASB Command, Invalid Station ID\n", dev->name);
  1376. break ;
  1377. }
  1378. xl_priv->asb_queued = 0 ;
  1379. writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
  1380. return ;
  1381. }
  1382. /*
  1383. * Issue srb commands to the nic
  1384. */
  1385. static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
  1386. {
  1387. struct xl_private *xl_priv = netdev_priv(dev);
  1388. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1389. switch (srb_cmd) {
  1390. case READ_LOG:
  1391. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1392. writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
  1393. break;
  1394. case CLOSE_NIC:
  1395. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1396. writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
  1397. break ;
  1398. case SET_RECEIVE_MODE:
  1399. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1400. writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
  1401. writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1402. writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
  1403. break ;
  1404. case SET_FUNC_ADDRESS:
  1405. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1406. writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
  1407. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1408. writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
  1409. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1410. writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
  1411. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1412. writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
  1413. writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1414. writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
  1415. break ;
  1416. } /* switch */
  1417. xl_wait_misr_flags(dev) ;
  1418. /* Write 0xff to the CSRB flag */
  1419. writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1420. writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
  1421. /* Set csrb bit in MISR register to process command */
  1422. writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1423. writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
  1424. xl_priv->srb_queued = 1 ;
  1425. return ;
  1426. }
  1427. /*
  1428. * This is nasty, to use the MISR command you have to wait for 6 memory locations
  1429. * to be zero. This is the way the driver does on other OS'es so we should be ok with
  1430. * the empty loop.
  1431. */
  1432. static void xl_wait_misr_flags(struct net_device *dev)
  1433. {
  1434. struct xl_private *xl_priv = netdev_priv(dev);
  1435. u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
  1436. int i ;
  1437. writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1438. if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
  1439. for (i=0; i<6; i++) {
  1440. writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1441. while (readb(xl_mmio + MMIO_MACDATA) != 0) {
  1442. ; /* Empty Loop */
  1443. }
  1444. }
  1445. }
  1446. writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
  1447. writeb(0x80, xl_mmio + MMIO_MACDATA) ;
  1448. return ;
  1449. }
  1450. /*
  1451. * Change mtu size, this should work the same as olympic
  1452. */
  1453. static int xl_change_mtu(struct net_device *dev, int mtu)
  1454. {
  1455. struct xl_private *xl_priv = netdev_priv(dev);
  1456. u16 max_mtu ;
  1457. if (xl_priv->xl_ring_speed == 4)
  1458. max_mtu = 4500 ;
  1459. else
  1460. max_mtu = 18000 ;
  1461. if (mtu > max_mtu)
  1462. return -EINVAL ;
  1463. if (mtu < 100)
  1464. return -EINVAL ;
  1465. dev->mtu = mtu ;
  1466. xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
  1467. return 0 ;
  1468. }
  1469. static void __devexit xl_remove_one (struct pci_dev *pdev)
  1470. {
  1471. struct net_device *dev = pci_get_drvdata(pdev);
  1472. struct xl_private *xl_priv=netdev_priv(dev);
  1473. release_firmware(xl_priv->fw);
  1474. unregister_netdev(dev);
  1475. iounmap(xl_priv->xl_mmio) ;
  1476. pci_release_regions(pdev) ;
  1477. pci_set_drvdata(pdev,NULL) ;
  1478. free_netdev(dev);
  1479. return ;
  1480. }
  1481. static struct pci_driver xl_3c359_driver = {
  1482. .name = "3c359",
  1483. .id_table = xl_pci_tbl,
  1484. .probe = xl_probe,
  1485. .remove = __devexit_p(xl_remove_one),
  1486. };
  1487. static int __init xl_pci_init (void)
  1488. {
  1489. return pci_register_driver(&xl_3c359_driver);
  1490. }
  1491. static void __exit xl_pci_cleanup (void)
  1492. {
  1493. pci_unregister_driver (&xl_3c359_driver);
  1494. }
  1495. module_init(xl_pci_init);
  1496. module_exit(xl_pci_cleanup);
  1497. MODULE_LICENSE("GPL") ;