cpsw.c 26 KB

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  1. /*
  2. * Texas Instruments Ethernet Switch Driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/io.h>
  17. #include <linux/clk.h>
  18. #include <linux/timer.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/irqreturn.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/if_ether.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/phy.h>
  27. #include <linux/workqueue.h>
  28. #include <linux/delay.h>
  29. #include <linux/platform_data/cpsw.h>
  30. #include "cpsw_ale.h"
  31. #include "davinci_cpdma.h"
  32. #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
  33. NETIF_MSG_DRV | NETIF_MSG_LINK | \
  34. NETIF_MSG_IFUP | NETIF_MSG_INTR | \
  35. NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
  36. NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
  37. NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
  38. NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
  39. NETIF_MSG_RX_STATUS)
  40. #define cpsw_info(priv, type, format, ...) \
  41. do { \
  42. if (netif_msg_##type(priv) && net_ratelimit()) \
  43. dev_info(priv->dev, format, ## __VA_ARGS__); \
  44. } while (0)
  45. #define cpsw_err(priv, type, format, ...) \
  46. do { \
  47. if (netif_msg_##type(priv) && net_ratelimit()) \
  48. dev_err(priv->dev, format, ## __VA_ARGS__); \
  49. } while (0)
  50. #define cpsw_dbg(priv, type, format, ...) \
  51. do { \
  52. if (netif_msg_##type(priv) && net_ratelimit()) \
  53. dev_dbg(priv->dev, format, ## __VA_ARGS__); \
  54. } while (0)
  55. #define cpsw_notice(priv, type, format, ...) \
  56. do { \
  57. if (netif_msg_##type(priv) && net_ratelimit()) \
  58. dev_notice(priv->dev, format, ## __VA_ARGS__); \
  59. } while (0)
  60. #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
  61. #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
  62. #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
  63. #define CPDMA_RXTHRESH 0x0c0
  64. #define CPDMA_RXFREE 0x0e0
  65. #define CPDMA_TXHDP 0x00
  66. #define CPDMA_RXHDP 0x20
  67. #define CPDMA_TXCP 0x40
  68. #define CPDMA_RXCP 0x60
  69. #define cpsw_dma_regs(base, offset) \
  70. (void __iomem *)((base) + (offset))
  71. #define cpsw_dma_rxthresh(base, offset) \
  72. (void __iomem *)((base) + (offset) + CPDMA_RXTHRESH)
  73. #define cpsw_dma_rxfree(base, offset) \
  74. (void __iomem *)((base) + (offset) + CPDMA_RXFREE)
  75. #define cpsw_dma_txhdp(base, offset) \
  76. (void __iomem *)((base) + (offset) + CPDMA_TXHDP)
  77. #define cpsw_dma_rxhdp(base, offset) \
  78. (void __iomem *)((base) + (offset) + CPDMA_RXHDP)
  79. #define cpsw_dma_txcp(base, offset) \
  80. (void __iomem *)((base) + (offset) + CPDMA_TXCP)
  81. #define cpsw_dma_rxcp(base, offset) \
  82. (void __iomem *)((base) + (offset) + CPDMA_RXCP)
  83. #define CPSW_POLL_WEIGHT 64
  84. #define CPSW_MIN_PACKET_SIZE 60
  85. #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
  86. #define RX_PRIORITY_MAPPING 0x76543210
  87. #define TX_PRIORITY_MAPPING 0x33221100
  88. #define CPDMA_TX_PRIORITY_MAP 0x76543210
  89. #define cpsw_enable_irq(priv) \
  90. do { \
  91. u32 i; \
  92. for (i = 0; i < priv->num_irqs; i++) \
  93. enable_irq(priv->irqs_table[i]); \
  94. } while (0);
  95. #define cpsw_disable_irq(priv) \
  96. do { \
  97. u32 i; \
  98. for (i = 0; i < priv->num_irqs; i++) \
  99. disable_irq_nosync(priv->irqs_table[i]); \
  100. } while (0);
  101. static int debug_level;
  102. module_param(debug_level, int, 0);
  103. MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
  104. static int ale_ageout = 10;
  105. module_param(ale_ageout, int, 0);
  106. MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
  107. static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
  108. module_param(rx_packet_max, int, 0);
  109. MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
  110. struct cpsw_ss_regs {
  111. u32 id_ver;
  112. u32 soft_reset;
  113. u32 control;
  114. u32 int_control;
  115. u32 rx_thresh_en;
  116. u32 rx_en;
  117. u32 tx_en;
  118. u32 misc_en;
  119. };
  120. struct cpsw_regs {
  121. u32 id_ver;
  122. u32 control;
  123. u32 soft_reset;
  124. u32 stat_port_en;
  125. u32 ptype;
  126. };
  127. struct cpsw_slave_regs {
  128. u32 max_blks;
  129. u32 blk_cnt;
  130. u32 flow_thresh;
  131. u32 port_vlan;
  132. u32 tx_pri_map;
  133. u32 ts_ctl;
  134. u32 ts_seq_ltype;
  135. u32 ts_vlan;
  136. u32 sa_lo;
  137. u32 sa_hi;
  138. };
  139. struct cpsw_host_regs {
  140. u32 max_blks;
  141. u32 blk_cnt;
  142. u32 flow_thresh;
  143. u32 port_vlan;
  144. u32 tx_pri_map;
  145. u32 cpdma_tx_pri_map;
  146. u32 cpdma_rx_chan_map;
  147. };
  148. struct cpsw_sliver_regs {
  149. u32 id_ver;
  150. u32 mac_control;
  151. u32 mac_status;
  152. u32 soft_reset;
  153. u32 rx_maxlen;
  154. u32 __reserved_0;
  155. u32 rx_pause;
  156. u32 tx_pause;
  157. u32 __reserved_1;
  158. u32 rx_pri_map;
  159. };
  160. struct cpsw_slave {
  161. struct cpsw_slave_regs __iomem *regs;
  162. struct cpsw_sliver_regs __iomem *sliver;
  163. int slave_num;
  164. u32 mac_control;
  165. struct cpsw_slave_data *data;
  166. struct phy_device *phy;
  167. };
  168. struct cpsw_priv {
  169. spinlock_t lock;
  170. struct platform_device *pdev;
  171. struct net_device *ndev;
  172. struct resource *cpsw_res;
  173. struct resource *cpsw_ss_res;
  174. struct napi_struct napi;
  175. struct device *dev;
  176. struct cpsw_platform_data data;
  177. struct cpsw_regs __iomem *regs;
  178. struct cpsw_ss_regs __iomem *ss_regs;
  179. struct cpsw_host_regs __iomem *host_port_regs;
  180. u32 msg_enable;
  181. struct net_device_stats stats;
  182. int rx_packet_max;
  183. int host_port;
  184. struct clk *clk;
  185. u8 mac_addr[ETH_ALEN];
  186. struct cpsw_slave *slaves;
  187. struct cpdma_ctlr *dma;
  188. struct cpdma_chan *txch, *rxch;
  189. struct cpsw_ale *ale;
  190. /* snapshot of IRQ numbers */
  191. u32 irqs_table[4];
  192. u32 num_irqs;
  193. };
  194. #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
  195. #define for_each_slave(priv, func, arg...) \
  196. do { \
  197. int idx; \
  198. for (idx = 0; idx < (priv)->data.slaves; idx++) \
  199. (func)((priv)->slaves + idx, ##arg); \
  200. } while (0)
  201. static void cpsw_intr_enable(struct cpsw_priv *priv)
  202. {
  203. __raw_writel(0xFF, &priv->ss_regs->tx_en);
  204. __raw_writel(0xFF, &priv->ss_regs->rx_en);
  205. cpdma_ctlr_int_ctrl(priv->dma, true);
  206. return;
  207. }
  208. static void cpsw_intr_disable(struct cpsw_priv *priv)
  209. {
  210. __raw_writel(0, &priv->ss_regs->tx_en);
  211. __raw_writel(0, &priv->ss_regs->rx_en);
  212. cpdma_ctlr_int_ctrl(priv->dma, false);
  213. return;
  214. }
  215. void cpsw_tx_handler(void *token, int len, int status)
  216. {
  217. struct sk_buff *skb = token;
  218. struct net_device *ndev = skb->dev;
  219. struct cpsw_priv *priv = netdev_priv(ndev);
  220. if (unlikely(netif_queue_stopped(ndev)))
  221. netif_wake_queue(ndev);
  222. priv->stats.tx_packets++;
  223. priv->stats.tx_bytes += len;
  224. dev_kfree_skb_any(skb);
  225. }
  226. void cpsw_rx_handler(void *token, int len, int status)
  227. {
  228. struct sk_buff *skb = token;
  229. struct net_device *ndev = skb->dev;
  230. struct cpsw_priv *priv = netdev_priv(ndev);
  231. int ret = 0;
  232. /* free and bail if we are shutting down */
  233. if (unlikely(!netif_running(ndev)) ||
  234. unlikely(!netif_carrier_ok(ndev))) {
  235. dev_kfree_skb_any(skb);
  236. return;
  237. }
  238. if (likely(status >= 0)) {
  239. skb_put(skb, len);
  240. skb->protocol = eth_type_trans(skb, ndev);
  241. netif_receive_skb(skb);
  242. priv->stats.rx_bytes += len;
  243. priv->stats.rx_packets++;
  244. skb = NULL;
  245. }
  246. if (unlikely(!netif_running(ndev))) {
  247. if (skb)
  248. dev_kfree_skb_any(skb);
  249. return;
  250. }
  251. if (likely(!skb)) {
  252. skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
  253. if (WARN_ON(!skb))
  254. return;
  255. ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
  256. skb_tailroom(skb), GFP_KERNEL);
  257. }
  258. WARN_ON(ret < 0);
  259. }
  260. static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
  261. {
  262. struct cpsw_priv *priv = dev_id;
  263. if (likely(netif_running(priv->ndev))) {
  264. cpsw_intr_disable(priv);
  265. cpsw_disable_irq(priv);
  266. napi_schedule(&priv->napi);
  267. }
  268. return IRQ_HANDLED;
  269. }
  270. static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
  271. {
  272. if (priv->host_port == 0)
  273. return slave_num + 1;
  274. else
  275. return slave_num;
  276. }
  277. static int cpsw_poll(struct napi_struct *napi, int budget)
  278. {
  279. struct cpsw_priv *priv = napi_to_priv(napi);
  280. int num_tx, num_rx;
  281. num_tx = cpdma_chan_process(priv->txch, 128);
  282. num_rx = cpdma_chan_process(priv->rxch, budget);
  283. if (num_rx || num_tx)
  284. cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
  285. num_rx, num_tx);
  286. if (num_rx < budget) {
  287. napi_complete(napi);
  288. cpsw_intr_enable(priv);
  289. cpdma_ctlr_eoi(priv->dma);
  290. cpsw_enable_irq(priv);
  291. }
  292. return num_rx;
  293. }
  294. static inline void soft_reset(const char *module, void __iomem *reg)
  295. {
  296. unsigned long timeout = jiffies + HZ;
  297. __raw_writel(1, reg);
  298. do {
  299. cpu_relax();
  300. } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
  301. WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
  302. }
  303. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  304. ((mac)[2] << 16) | ((mac)[3] << 24))
  305. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  306. static void cpsw_set_slave_mac(struct cpsw_slave *slave,
  307. struct cpsw_priv *priv)
  308. {
  309. __raw_writel(mac_hi(priv->mac_addr), &slave->regs->sa_hi);
  310. __raw_writel(mac_lo(priv->mac_addr), &slave->regs->sa_lo);
  311. }
  312. static void _cpsw_adjust_link(struct cpsw_slave *slave,
  313. struct cpsw_priv *priv, bool *link)
  314. {
  315. struct phy_device *phy = slave->phy;
  316. u32 mac_control = 0;
  317. u32 slave_port;
  318. if (!phy)
  319. return;
  320. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  321. if (phy->link) {
  322. mac_control = priv->data.mac_control;
  323. /* enable forwarding */
  324. cpsw_ale_control_set(priv->ale, slave_port,
  325. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  326. if (phy->speed == 1000)
  327. mac_control |= BIT(7); /* GIGABITEN */
  328. if (phy->duplex)
  329. mac_control |= BIT(0); /* FULLDUPLEXEN */
  330. *link = true;
  331. } else {
  332. mac_control = 0;
  333. /* disable forwarding */
  334. cpsw_ale_control_set(priv->ale, slave_port,
  335. ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
  336. }
  337. if (mac_control != slave->mac_control) {
  338. phy_print_status(phy);
  339. __raw_writel(mac_control, &slave->sliver->mac_control);
  340. }
  341. slave->mac_control = mac_control;
  342. }
  343. static void cpsw_adjust_link(struct net_device *ndev)
  344. {
  345. struct cpsw_priv *priv = netdev_priv(ndev);
  346. bool link = false;
  347. for_each_slave(priv, _cpsw_adjust_link, priv, &link);
  348. if (link) {
  349. netif_carrier_on(ndev);
  350. if (netif_running(ndev))
  351. netif_wake_queue(ndev);
  352. } else {
  353. netif_carrier_off(ndev);
  354. netif_stop_queue(ndev);
  355. }
  356. }
  357. static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
  358. {
  359. static char *leader = "........................................";
  360. if (!val)
  361. return 0;
  362. else
  363. return snprintf(buf, maxlen, "%s %s %10d\n", name,
  364. leader + strlen(name), val);
  365. }
  366. static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
  367. {
  368. char name[32];
  369. u32 slave_port;
  370. sprintf(name, "slave-%d", slave->slave_num);
  371. soft_reset(name, &slave->sliver->soft_reset);
  372. /* setup priority mapping */
  373. __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
  374. __raw_writel(TX_PRIORITY_MAPPING, &slave->regs->tx_pri_map);
  375. /* setup max packet size, and mac address */
  376. __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
  377. cpsw_set_slave_mac(slave, priv);
  378. slave->mac_control = 0; /* no link yet */
  379. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  380. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  381. 1 << slave_port, 0, ALE_MCAST_FWD_2);
  382. slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
  383. &cpsw_adjust_link, 0, slave->data->phy_if);
  384. if (IS_ERR(slave->phy)) {
  385. dev_err(priv->dev, "phy %s not found on slave %d\n",
  386. slave->data->phy_id, slave->slave_num);
  387. slave->phy = NULL;
  388. } else {
  389. dev_info(priv->dev, "phy found : id is : 0x%x\n",
  390. slave->phy->phy_id);
  391. phy_start(slave->phy);
  392. }
  393. }
  394. static void cpsw_init_host_port(struct cpsw_priv *priv)
  395. {
  396. /* soft reset the controller and initialize ale */
  397. soft_reset("cpsw", &priv->regs->soft_reset);
  398. cpsw_ale_start(priv->ale);
  399. /* switch to vlan unaware mode */
  400. cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0);
  401. /* setup host port priority mapping */
  402. __raw_writel(CPDMA_TX_PRIORITY_MAP,
  403. &priv->host_port_regs->cpdma_tx_pri_map);
  404. __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
  405. cpsw_ale_control_set(priv->ale, priv->host_port,
  406. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  407. cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0);
  408. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  409. 1 << priv->host_port, 0, ALE_MCAST_FWD_2);
  410. }
  411. static int cpsw_ndo_open(struct net_device *ndev)
  412. {
  413. struct cpsw_priv *priv = netdev_priv(ndev);
  414. int i, ret;
  415. u32 reg;
  416. cpsw_intr_disable(priv);
  417. netif_carrier_off(ndev);
  418. ret = clk_enable(priv->clk);
  419. if (ret < 0) {
  420. dev_err(priv->dev, "unable to turn on device clock\n");
  421. return ret;
  422. }
  423. reg = __raw_readl(&priv->regs->id_ver);
  424. dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
  425. CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
  426. CPSW_RTL_VERSION(reg));
  427. /* initialize host and slave ports */
  428. cpsw_init_host_port(priv);
  429. for_each_slave(priv, cpsw_slave_open, priv);
  430. /* setup tx dma to fixed prio and zero offset */
  431. cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
  432. cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
  433. /* disable priority elevation and enable statistics on all ports */
  434. __raw_writel(0, &priv->regs->ptype);
  435. /* enable statistics collection only on the host port */
  436. __raw_writel(0x7, &priv->regs->stat_port_en);
  437. if (WARN_ON(!priv->data.rx_descs))
  438. priv->data.rx_descs = 128;
  439. for (i = 0; i < priv->data.rx_descs; i++) {
  440. struct sk_buff *skb;
  441. ret = -ENOMEM;
  442. skb = netdev_alloc_skb_ip_align(priv->ndev,
  443. priv->rx_packet_max);
  444. if (!skb)
  445. break;
  446. ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
  447. skb_tailroom(skb), GFP_KERNEL);
  448. if (WARN_ON(ret < 0))
  449. break;
  450. }
  451. /* continue even if we didn't manage to submit all receive descs */
  452. cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
  453. cpdma_ctlr_start(priv->dma);
  454. cpsw_intr_enable(priv);
  455. napi_enable(&priv->napi);
  456. cpdma_ctlr_eoi(priv->dma);
  457. return 0;
  458. }
  459. static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
  460. {
  461. if (!slave->phy)
  462. return;
  463. phy_stop(slave->phy);
  464. phy_disconnect(slave->phy);
  465. slave->phy = NULL;
  466. }
  467. static int cpsw_ndo_stop(struct net_device *ndev)
  468. {
  469. struct cpsw_priv *priv = netdev_priv(ndev);
  470. cpsw_info(priv, ifdown, "shutting down cpsw device\n");
  471. cpsw_intr_disable(priv);
  472. cpdma_ctlr_int_ctrl(priv->dma, false);
  473. cpdma_ctlr_stop(priv->dma);
  474. netif_stop_queue(priv->ndev);
  475. napi_disable(&priv->napi);
  476. netif_carrier_off(priv->ndev);
  477. cpsw_ale_stop(priv->ale);
  478. for_each_slave(priv, cpsw_slave_stop, priv);
  479. clk_disable(priv->clk);
  480. return 0;
  481. }
  482. static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
  483. struct net_device *ndev)
  484. {
  485. struct cpsw_priv *priv = netdev_priv(ndev);
  486. int ret;
  487. ndev->trans_start = jiffies;
  488. if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
  489. cpsw_err(priv, tx_err, "packet pad failed\n");
  490. priv->stats.tx_dropped++;
  491. return NETDEV_TX_OK;
  492. }
  493. ret = cpdma_chan_submit(priv->txch, skb, skb->data,
  494. skb->len, GFP_KERNEL);
  495. if (unlikely(ret != 0)) {
  496. cpsw_err(priv, tx_err, "desc submit failed\n");
  497. goto fail;
  498. }
  499. return NETDEV_TX_OK;
  500. fail:
  501. priv->stats.tx_dropped++;
  502. netif_stop_queue(ndev);
  503. return NETDEV_TX_BUSY;
  504. }
  505. static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
  506. {
  507. /*
  508. * The switch cannot operate in promiscuous mode without substantial
  509. * headache. For promiscuous mode to work, we would need to put the
  510. * ALE in bypass mode and route all traffic to the host port.
  511. * Subsequently, the host will need to operate as a "bridge", learn,
  512. * and flood as needed. For now, we simply complain here and
  513. * do nothing about it :-)
  514. */
  515. if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
  516. dev_err(&ndev->dev, "promiscuity ignored!\n");
  517. /*
  518. * The switch cannot filter multicast traffic unless it is configured
  519. * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
  520. * whole bunch of additional logic that this driver does not implement
  521. * at present.
  522. */
  523. if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
  524. dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
  525. }
  526. static void cpsw_ndo_tx_timeout(struct net_device *ndev)
  527. {
  528. struct cpsw_priv *priv = netdev_priv(ndev);
  529. cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
  530. priv->stats.tx_errors++;
  531. cpsw_intr_disable(priv);
  532. cpdma_ctlr_int_ctrl(priv->dma, false);
  533. cpdma_chan_stop(priv->txch);
  534. cpdma_chan_start(priv->txch);
  535. cpdma_ctlr_int_ctrl(priv->dma, true);
  536. cpsw_intr_enable(priv);
  537. cpdma_ctlr_eoi(priv->dma);
  538. }
  539. static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
  540. {
  541. struct cpsw_priv *priv = netdev_priv(ndev);
  542. return &priv->stats;
  543. }
  544. #ifdef CONFIG_NET_POLL_CONTROLLER
  545. static void cpsw_ndo_poll_controller(struct net_device *ndev)
  546. {
  547. struct cpsw_priv *priv = netdev_priv(ndev);
  548. cpsw_intr_disable(priv);
  549. cpdma_ctlr_int_ctrl(priv->dma, false);
  550. cpsw_interrupt(ndev->irq, priv);
  551. cpdma_ctlr_int_ctrl(priv->dma, true);
  552. cpsw_intr_enable(priv);
  553. cpdma_ctlr_eoi(priv->dma);
  554. }
  555. #endif
  556. static const struct net_device_ops cpsw_netdev_ops = {
  557. .ndo_open = cpsw_ndo_open,
  558. .ndo_stop = cpsw_ndo_stop,
  559. .ndo_start_xmit = cpsw_ndo_start_xmit,
  560. .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
  561. .ndo_validate_addr = eth_validate_addr,
  562. .ndo_change_mtu = eth_change_mtu,
  563. .ndo_tx_timeout = cpsw_ndo_tx_timeout,
  564. .ndo_get_stats = cpsw_ndo_get_stats,
  565. #ifdef CONFIG_NET_POLL_CONTROLLER
  566. .ndo_poll_controller = cpsw_ndo_poll_controller,
  567. #endif
  568. };
  569. static void cpsw_get_drvinfo(struct net_device *ndev,
  570. struct ethtool_drvinfo *info)
  571. {
  572. struct cpsw_priv *priv = netdev_priv(ndev);
  573. strcpy(info->driver, "TI CPSW Driver v1.0");
  574. strcpy(info->version, "1.0");
  575. strcpy(info->bus_info, priv->pdev->name);
  576. }
  577. static u32 cpsw_get_msglevel(struct net_device *ndev)
  578. {
  579. struct cpsw_priv *priv = netdev_priv(ndev);
  580. return priv->msg_enable;
  581. }
  582. static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
  583. {
  584. struct cpsw_priv *priv = netdev_priv(ndev);
  585. priv->msg_enable = value;
  586. }
  587. static const struct ethtool_ops cpsw_ethtool_ops = {
  588. .get_drvinfo = cpsw_get_drvinfo,
  589. .get_msglevel = cpsw_get_msglevel,
  590. .set_msglevel = cpsw_set_msglevel,
  591. .get_link = ethtool_op_get_link,
  592. };
  593. static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
  594. {
  595. void __iomem *regs = priv->regs;
  596. int slave_num = slave->slave_num;
  597. struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
  598. slave->data = data;
  599. slave->regs = regs + data->slave_reg_ofs;
  600. slave->sliver = regs + data->sliver_reg_ofs;
  601. }
  602. static int __devinit cpsw_probe(struct platform_device *pdev)
  603. {
  604. struct cpsw_platform_data *data = pdev->dev.platform_data;
  605. struct net_device *ndev;
  606. struct cpsw_priv *priv;
  607. struct cpdma_params dma_params;
  608. struct cpsw_ale_params ale_params;
  609. void __iomem *regs;
  610. struct resource *res;
  611. int ret = 0, i, k = 0;
  612. if (!data) {
  613. pr_err("platform data missing\n");
  614. return -ENODEV;
  615. }
  616. ndev = alloc_etherdev(sizeof(struct cpsw_priv));
  617. if (!ndev) {
  618. pr_err("error allocating net_device\n");
  619. return -ENOMEM;
  620. }
  621. platform_set_drvdata(pdev, ndev);
  622. priv = netdev_priv(ndev);
  623. spin_lock_init(&priv->lock);
  624. priv->data = *data;
  625. priv->pdev = pdev;
  626. priv->ndev = ndev;
  627. priv->dev = &ndev->dev;
  628. priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
  629. priv->rx_packet_max = max(rx_packet_max, 128);
  630. if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
  631. memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
  632. pr_info("Detected MACID = %pM", priv->mac_addr);
  633. } else {
  634. random_ether_addr(priv->mac_addr);
  635. pr_info("Random MACID = %pM", priv->mac_addr);
  636. }
  637. memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
  638. priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
  639. GFP_KERNEL);
  640. if (!priv->slaves) {
  641. ret = -EBUSY;
  642. goto clean_ndev_ret;
  643. }
  644. for (i = 0; i < data->slaves; i++)
  645. priv->slaves[i].slave_num = i;
  646. priv->clk = clk_get(&pdev->dev, NULL);
  647. if (IS_ERR(priv->clk)) {
  648. dev_err(priv->dev, "failed to get device clock)\n");
  649. ret = -EBUSY;
  650. }
  651. priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  652. if (!priv->cpsw_res) {
  653. dev_err(priv->dev, "error getting i/o resource\n");
  654. ret = -ENOENT;
  655. goto clean_clk_ret;
  656. }
  657. if (!request_mem_region(priv->cpsw_res->start,
  658. resource_size(priv->cpsw_res), ndev->name)) {
  659. dev_err(priv->dev, "failed request i/o region\n");
  660. ret = -ENXIO;
  661. goto clean_clk_ret;
  662. }
  663. regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
  664. if (!regs) {
  665. dev_err(priv->dev, "unable to map i/o region\n");
  666. goto clean_cpsw_iores_ret;
  667. }
  668. priv->regs = regs;
  669. priv->host_port = data->host_port_num;
  670. priv->host_port_regs = regs + data->host_port_reg_ofs;
  671. priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  672. if (!priv->cpsw_ss_res) {
  673. dev_err(priv->dev, "error getting i/o resource\n");
  674. ret = -ENOENT;
  675. goto clean_clk_ret;
  676. }
  677. if (!request_mem_region(priv->cpsw_ss_res->start,
  678. resource_size(priv->cpsw_ss_res), ndev->name)) {
  679. dev_err(priv->dev, "failed request i/o region\n");
  680. ret = -ENXIO;
  681. goto clean_clk_ret;
  682. }
  683. regs = ioremap(priv->cpsw_ss_res->start,
  684. resource_size(priv->cpsw_ss_res));
  685. if (!regs) {
  686. dev_err(priv->dev, "unable to map i/o region\n");
  687. goto clean_cpsw_ss_iores_ret;
  688. }
  689. priv->ss_regs = regs;
  690. for_each_slave(priv, cpsw_slave_init, priv);
  691. memset(&dma_params, 0, sizeof(dma_params));
  692. dma_params.dev = &pdev->dev;
  693. dma_params.dmaregs = cpsw_dma_regs((u32)priv->regs,
  694. data->cpdma_reg_ofs);
  695. dma_params.rxthresh = cpsw_dma_rxthresh((u32)priv->regs,
  696. data->cpdma_reg_ofs);
  697. dma_params.rxfree = cpsw_dma_rxfree((u32)priv->regs,
  698. data->cpdma_reg_ofs);
  699. dma_params.txhdp = cpsw_dma_txhdp((u32)priv->regs,
  700. data->cpdma_sram_ofs);
  701. dma_params.rxhdp = cpsw_dma_rxhdp((u32)priv->regs,
  702. data->cpdma_sram_ofs);
  703. dma_params.txcp = cpsw_dma_txcp((u32)priv->regs,
  704. data->cpdma_sram_ofs);
  705. dma_params.rxcp = cpsw_dma_rxcp((u32)priv->regs,
  706. data->cpdma_sram_ofs);
  707. dma_params.num_chan = data->channels;
  708. dma_params.has_soft_reset = true;
  709. dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
  710. dma_params.desc_mem_size = data->bd_ram_size;
  711. dma_params.desc_align = 16;
  712. dma_params.has_ext_regs = true;
  713. dma_params.desc_mem_phys = data->no_bd_ram ? 0 :
  714. (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
  715. dma_params.desc_hw_addr = data->hw_ram_addr ?
  716. data->hw_ram_addr : dma_params.desc_mem_phys ;
  717. priv->dma = cpdma_ctlr_create(&dma_params);
  718. if (!priv->dma) {
  719. dev_err(priv->dev, "error initializing dma\n");
  720. ret = -ENOMEM;
  721. goto clean_iomap_ret;
  722. }
  723. priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
  724. cpsw_tx_handler);
  725. priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
  726. cpsw_rx_handler);
  727. if (WARN_ON(!priv->txch || !priv->rxch)) {
  728. dev_err(priv->dev, "error initializing dma channels\n");
  729. ret = -ENOMEM;
  730. goto clean_dma_ret;
  731. }
  732. memset(&ale_params, 0, sizeof(ale_params));
  733. ale_params.dev = &ndev->dev;
  734. ale_params.ale_regs = (void *)((u32)priv->regs) +
  735. ((u32)data->ale_reg_ofs);
  736. ale_params.ale_ageout = ale_ageout;
  737. ale_params.ale_entries = data->ale_entries;
  738. ale_params.ale_ports = data->slaves;
  739. priv->ale = cpsw_ale_create(&ale_params);
  740. if (!priv->ale) {
  741. dev_err(priv->dev, "error initializing ale engine\n");
  742. ret = -ENODEV;
  743. goto clean_dma_ret;
  744. }
  745. ndev->irq = platform_get_irq(pdev, 0);
  746. if (ndev->irq < 0) {
  747. dev_err(priv->dev, "error getting irq resource\n");
  748. ret = -ENOENT;
  749. goto clean_ale_ret;
  750. }
  751. while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
  752. for (i = res->start; i <= res->end; i++) {
  753. if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
  754. dev_name(&pdev->dev), priv)) {
  755. dev_err(priv->dev, "error attaching irq\n");
  756. goto clean_ale_ret;
  757. }
  758. priv->irqs_table[k] = i;
  759. priv->num_irqs = k;
  760. }
  761. k++;
  762. }
  763. ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */
  764. ndev->netdev_ops = &cpsw_netdev_ops;
  765. SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
  766. netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
  767. /* register the network device */
  768. SET_NETDEV_DEV(ndev, &pdev->dev);
  769. ret = register_netdev(ndev);
  770. if (ret) {
  771. dev_err(priv->dev, "error registering net device\n");
  772. ret = -ENODEV;
  773. goto clean_irq_ret;
  774. }
  775. cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
  776. priv->cpsw_res->start, ndev->irq);
  777. return 0;
  778. clean_irq_ret:
  779. free_irq(ndev->irq, priv);
  780. clean_ale_ret:
  781. cpsw_ale_destroy(priv->ale);
  782. clean_dma_ret:
  783. cpdma_chan_destroy(priv->txch);
  784. cpdma_chan_destroy(priv->rxch);
  785. cpdma_ctlr_destroy(priv->dma);
  786. clean_iomap_ret:
  787. iounmap(priv->regs);
  788. clean_cpsw_ss_iores_ret:
  789. release_mem_region(priv->cpsw_ss_res->start,
  790. resource_size(priv->cpsw_ss_res));
  791. clean_cpsw_iores_ret:
  792. release_mem_region(priv->cpsw_res->start,
  793. resource_size(priv->cpsw_res));
  794. clean_clk_ret:
  795. clk_put(priv->clk);
  796. kfree(priv->slaves);
  797. clean_ndev_ret:
  798. free_netdev(ndev);
  799. return ret;
  800. }
  801. static int __devexit cpsw_remove(struct platform_device *pdev)
  802. {
  803. struct net_device *ndev = platform_get_drvdata(pdev);
  804. struct cpsw_priv *priv = netdev_priv(ndev);
  805. pr_info("removing device");
  806. platform_set_drvdata(pdev, NULL);
  807. free_irq(ndev->irq, priv);
  808. cpsw_ale_destroy(priv->ale);
  809. cpdma_chan_destroy(priv->txch);
  810. cpdma_chan_destroy(priv->rxch);
  811. cpdma_ctlr_destroy(priv->dma);
  812. iounmap(priv->regs);
  813. release_mem_region(priv->cpsw_res->start,
  814. resource_size(priv->cpsw_res));
  815. release_mem_region(priv->cpsw_ss_res->start,
  816. resource_size(priv->cpsw_ss_res));
  817. clk_put(priv->clk);
  818. kfree(priv->slaves);
  819. free_netdev(ndev);
  820. return 0;
  821. }
  822. static int cpsw_suspend(struct device *dev)
  823. {
  824. struct platform_device *pdev = to_platform_device(dev);
  825. struct net_device *ndev = platform_get_drvdata(pdev);
  826. if (netif_running(ndev))
  827. cpsw_ndo_stop(ndev);
  828. return 0;
  829. }
  830. static int cpsw_resume(struct device *dev)
  831. {
  832. struct platform_device *pdev = to_platform_device(dev);
  833. struct net_device *ndev = platform_get_drvdata(pdev);
  834. if (netif_running(ndev))
  835. cpsw_ndo_open(ndev);
  836. return 0;
  837. }
  838. static const struct dev_pm_ops cpsw_pm_ops = {
  839. .suspend = cpsw_suspend,
  840. .resume = cpsw_resume,
  841. };
  842. static struct platform_driver cpsw_driver = {
  843. .driver = {
  844. .name = "cpsw",
  845. .owner = THIS_MODULE,
  846. .pm = &cpsw_pm_ops,
  847. },
  848. .probe = cpsw_probe,
  849. .remove = __devexit_p(cpsw_remove),
  850. };
  851. static int __init cpsw_init(void)
  852. {
  853. return platform_driver_register(&cpsw_driver);
  854. }
  855. late_initcall(cpsw_init);
  856. static void __exit cpsw_exit(void)
  857. {
  858. platform_driver_unregister(&cpsw_driver);
  859. }
  860. module_exit(cpsw_exit);
  861. MODULE_LICENSE("GPL");
  862. MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
  863. MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
  864. MODULE_DESCRIPTION("TI CPSW Ethernet driver");