ftmac100.c 31 KB

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  1. /*
  2. * Faraday FTMAC100 10/100 Ethernet
  3. *
  4. * (C) Copyright 2009-2011 Faraday Technology
  5. * Po-Yu Chuang <ratbert@faraday-tech.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22. #include <linux/dma-mapping.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/init.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/io.h>
  28. #include <linux/mii.h>
  29. #include <linux/module.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/platform_device.h>
  32. #include "ftmac100.h"
  33. #define DRV_NAME "ftmac100"
  34. #define DRV_VERSION "0.2"
  35. #define RX_QUEUE_ENTRIES 128 /* must be power of 2 */
  36. #define TX_QUEUE_ENTRIES 16 /* must be power of 2 */
  37. #define MAX_PKT_SIZE 1518
  38. #define RX_BUF_SIZE 2044 /* must be smaller than 0x7ff */
  39. #if MAX_PKT_SIZE > 0x7ff
  40. #error invalid MAX_PKT_SIZE
  41. #endif
  42. #if RX_BUF_SIZE > 0x7ff || RX_BUF_SIZE > PAGE_SIZE
  43. #error invalid RX_BUF_SIZE
  44. #endif
  45. /******************************************************************************
  46. * private data
  47. *****************************************************************************/
  48. struct ftmac100_descs {
  49. struct ftmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
  50. struct ftmac100_txdes txdes[TX_QUEUE_ENTRIES];
  51. };
  52. struct ftmac100 {
  53. struct resource *res;
  54. void __iomem *base;
  55. int irq;
  56. struct ftmac100_descs *descs;
  57. dma_addr_t descs_dma_addr;
  58. unsigned int rx_pointer;
  59. unsigned int tx_clean_pointer;
  60. unsigned int tx_pointer;
  61. unsigned int tx_pending;
  62. spinlock_t tx_lock;
  63. struct net_device *netdev;
  64. struct device *dev;
  65. struct napi_struct napi;
  66. struct mii_if_info mii;
  67. };
  68. static int ftmac100_alloc_rx_page(struct ftmac100 *priv,
  69. struct ftmac100_rxdes *rxdes, gfp_t gfp);
  70. /******************************************************************************
  71. * internal functions (hardware register access)
  72. *****************************************************************************/
  73. #define INT_MASK_ALL_ENABLED (FTMAC100_INT_RPKT_FINISH | \
  74. FTMAC100_INT_NORXBUF | \
  75. FTMAC100_INT_XPKT_OK | \
  76. FTMAC100_INT_XPKT_LOST | \
  77. FTMAC100_INT_RPKT_LOST | \
  78. FTMAC100_INT_AHB_ERR | \
  79. FTMAC100_INT_PHYSTS_CHG)
  80. #define INT_MASK_ALL_DISABLED 0
  81. static void ftmac100_enable_all_int(struct ftmac100 *priv)
  82. {
  83. iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTMAC100_OFFSET_IMR);
  84. }
  85. static void ftmac100_disable_all_int(struct ftmac100 *priv)
  86. {
  87. iowrite32(INT_MASK_ALL_DISABLED, priv->base + FTMAC100_OFFSET_IMR);
  88. }
  89. static void ftmac100_set_rx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
  90. {
  91. iowrite32(addr, priv->base + FTMAC100_OFFSET_RXR_BADR);
  92. }
  93. static void ftmac100_set_tx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
  94. {
  95. iowrite32(addr, priv->base + FTMAC100_OFFSET_TXR_BADR);
  96. }
  97. static void ftmac100_txdma_start_polling(struct ftmac100 *priv)
  98. {
  99. iowrite32(1, priv->base + FTMAC100_OFFSET_TXPD);
  100. }
  101. static int ftmac100_reset(struct ftmac100 *priv)
  102. {
  103. struct net_device *netdev = priv->netdev;
  104. int i;
  105. /* NOTE: reset clears all registers */
  106. iowrite32(FTMAC100_MACCR_SW_RST, priv->base + FTMAC100_OFFSET_MACCR);
  107. for (i = 0; i < 5; i++) {
  108. unsigned int maccr;
  109. maccr = ioread32(priv->base + FTMAC100_OFFSET_MACCR);
  110. if (!(maccr & FTMAC100_MACCR_SW_RST)) {
  111. /*
  112. * FTMAC100_MACCR_SW_RST cleared does not indicate
  113. * that hardware reset completed (what the f*ck).
  114. * We still need to wait for a while.
  115. */
  116. udelay(500);
  117. return 0;
  118. }
  119. udelay(1000);
  120. }
  121. netdev_err(netdev, "software reset failed\n");
  122. return -EIO;
  123. }
  124. static void ftmac100_set_mac(struct ftmac100 *priv, const unsigned char *mac)
  125. {
  126. unsigned int maddr = mac[0] << 8 | mac[1];
  127. unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
  128. iowrite32(maddr, priv->base + FTMAC100_OFFSET_MAC_MADR);
  129. iowrite32(laddr, priv->base + FTMAC100_OFFSET_MAC_LADR);
  130. }
  131. #define MACCR_ENABLE_ALL (FTMAC100_MACCR_XMT_EN | \
  132. FTMAC100_MACCR_RCV_EN | \
  133. FTMAC100_MACCR_XDMA_EN | \
  134. FTMAC100_MACCR_RDMA_EN | \
  135. FTMAC100_MACCR_CRC_APD | \
  136. FTMAC100_MACCR_FULLDUP | \
  137. FTMAC100_MACCR_RX_RUNT | \
  138. FTMAC100_MACCR_RX_BROADPKT)
  139. static int ftmac100_start_hw(struct ftmac100 *priv)
  140. {
  141. struct net_device *netdev = priv->netdev;
  142. if (ftmac100_reset(priv))
  143. return -EIO;
  144. /* setup ring buffer base registers */
  145. ftmac100_set_rx_ring_base(priv,
  146. priv->descs_dma_addr +
  147. offsetof(struct ftmac100_descs, rxdes));
  148. ftmac100_set_tx_ring_base(priv,
  149. priv->descs_dma_addr +
  150. offsetof(struct ftmac100_descs, txdes));
  151. iowrite32(FTMAC100_APTC_RXPOLL_CNT(1), priv->base + FTMAC100_OFFSET_APTC);
  152. ftmac100_set_mac(priv, netdev->dev_addr);
  153. iowrite32(MACCR_ENABLE_ALL, priv->base + FTMAC100_OFFSET_MACCR);
  154. return 0;
  155. }
  156. static void ftmac100_stop_hw(struct ftmac100 *priv)
  157. {
  158. iowrite32(0, priv->base + FTMAC100_OFFSET_MACCR);
  159. }
  160. /******************************************************************************
  161. * internal functions (receive descriptor)
  162. *****************************************************************************/
  163. static bool ftmac100_rxdes_first_segment(struct ftmac100_rxdes *rxdes)
  164. {
  165. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FRS);
  166. }
  167. static bool ftmac100_rxdes_last_segment(struct ftmac100_rxdes *rxdes)
  168. {
  169. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_LRS);
  170. }
  171. static bool ftmac100_rxdes_owned_by_dma(struct ftmac100_rxdes *rxdes)
  172. {
  173. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
  174. }
  175. static void ftmac100_rxdes_set_dma_own(struct ftmac100_rxdes *rxdes)
  176. {
  177. /* clear status bits */
  178. rxdes->rxdes0 = cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
  179. }
  180. static bool ftmac100_rxdes_rx_error(struct ftmac100_rxdes *rxdes)
  181. {
  182. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ERR);
  183. }
  184. static bool ftmac100_rxdes_crc_error(struct ftmac100_rxdes *rxdes)
  185. {
  186. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_CRC_ERR);
  187. }
  188. static bool ftmac100_rxdes_frame_too_long(struct ftmac100_rxdes *rxdes)
  189. {
  190. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FTL);
  191. }
  192. static bool ftmac100_rxdes_runt(struct ftmac100_rxdes *rxdes)
  193. {
  194. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RUNT);
  195. }
  196. static bool ftmac100_rxdes_odd_nibble(struct ftmac100_rxdes *rxdes)
  197. {
  198. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ODD_NB);
  199. }
  200. static unsigned int ftmac100_rxdes_frame_length(struct ftmac100_rxdes *rxdes)
  201. {
  202. return le32_to_cpu(rxdes->rxdes0) & FTMAC100_RXDES0_RFL;
  203. }
  204. static bool ftmac100_rxdes_multicast(struct ftmac100_rxdes *rxdes)
  205. {
  206. return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_MULTICAST);
  207. }
  208. static void ftmac100_rxdes_set_buffer_size(struct ftmac100_rxdes *rxdes,
  209. unsigned int size)
  210. {
  211. rxdes->rxdes1 &= cpu_to_le32(FTMAC100_RXDES1_EDORR);
  212. rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_RXBUF_SIZE(size));
  213. }
  214. static void ftmac100_rxdes_set_end_of_ring(struct ftmac100_rxdes *rxdes)
  215. {
  216. rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_EDORR);
  217. }
  218. static void ftmac100_rxdes_set_dma_addr(struct ftmac100_rxdes *rxdes,
  219. dma_addr_t addr)
  220. {
  221. rxdes->rxdes2 = cpu_to_le32(addr);
  222. }
  223. static dma_addr_t ftmac100_rxdes_get_dma_addr(struct ftmac100_rxdes *rxdes)
  224. {
  225. return le32_to_cpu(rxdes->rxdes2);
  226. }
  227. /*
  228. * rxdes3 is not used by hardware. We use it to keep track of page.
  229. * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
  230. */
  231. static void ftmac100_rxdes_set_page(struct ftmac100_rxdes *rxdes, struct page *page)
  232. {
  233. rxdes->rxdes3 = (unsigned int)page;
  234. }
  235. static struct page *ftmac100_rxdes_get_page(struct ftmac100_rxdes *rxdes)
  236. {
  237. return (struct page *)rxdes->rxdes3;
  238. }
  239. /******************************************************************************
  240. * internal functions (receive)
  241. *****************************************************************************/
  242. static int ftmac100_next_rx_pointer(int pointer)
  243. {
  244. return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
  245. }
  246. static void ftmac100_rx_pointer_advance(struct ftmac100 *priv)
  247. {
  248. priv->rx_pointer = ftmac100_next_rx_pointer(priv->rx_pointer);
  249. }
  250. static struct ftmac100_rxdes *ftmac100_current_rxdes(struct ftmac100 *priv)
  251. {
  252. return &priv->descs->rxdes[priv->rx_pointer];
  253. }
  254. static struct ftmac100_rxdes *
  255. ftmac100_rx_locate_first_segment(struct ftmac100 *priv)
  256. {
  257. struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
  258. while (!ftmac100_rxdes_owned_by_dma(rxdes)) {
  259. if (ftmac100_rxdes_first_segment(rxdes))
  260. return rxdes;
  261. ftmac100_rxdes_set_dma_own(rxdes);
  262. ftmac100_rx_pointer_advance(priv);
  263. rxdes = ftmac100_current_rxdes(priv);
  264. }
  265. return NULL;
  266. }
  267. static bool ftmac100_rx_packet_error(struct ftmac100 *priv,
  268. struct ftmac100_rxdes *rxdes)
  269. {
  270. struct net_device *netdev = priv->netdev;
  271. bool error = false;
  272. if (unlikely(ftmac100_rxdes_rx_error(rxdes))) {
  273. if (net_ratelimit())
  274. netdev_info(netdev, "rx err\n");
  275. netdev->stats.rx_errors++;
  276. error = true;
  277. }
  278. if (unlikely(ftmac100_rxdes_crc_error(rxdes))) {
  279. if (net_ratelimit())
  280. netdev_info(netdev, "rx crc err\n");
  281. netdev->stats.rx_crc_errors++;
  282. error = true;
  283. }
  284. if (unlikely(ftmac100_rxdes_frame_too_long(rxdes))) {
  285. if (net_ratelimit())
  286. netdev_info(netdev, "rx frame too long\n");
  287. netdev->stats.rx_length_errors++;
  288. error = true;
  289. } else if (unlikely(ftmac100_rxdes_runt(rxdes))) {
  290. if (net_ratelimit())
  291. netdev_info(netdev, "rx runt\n");
  292. netdev->stats.rx_length_errors++;
  293. error = true;
  294. } else if (unlikely(ftmac100_rxdes_odd_nibble(rxdes))) {
  295. if (net_ratelimit())
  296. netdev_info(netdev, "rx odd nibble\n");
  297. netdev->stats.rx_length_errors++;
  298. error = true;
  299. }
  300. return error;
  301. }
  302. static void ftmac100_rx_drop_packet(struct ftmac100 *priv)
  303. {
  304. struct net_device *netdev = priv->netdev;
  305. struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
  306. bool done = false;
  307. if (net_ratelimit())
  308. netdev_dbg(netdev, "drop packet %p\n", rxdes);
  309. do {
  310. if (ftmac100_rxdes_last_segment(rxdes))
  311. done = true;
  312. ftmac100_rxdes_set_dma_own(rxdes);
  313. ftmac100_rx_pointer_advance(priv);
  314. rxdes = ftmac100_current_rxdes(priv);
  315. } while (!done && !ftmac100_rxdes_owned_by_dma(rxdes));
  316. netdev->stats.rx_dropped++;
  317. }
  318. static bool ftmac100_rx_packet(struct ftmac100 *priv, int *processed)
  319. {
  320. struct net_device *netdev = priv->netdev;
  321. struct ftmac100_rxdes *rxdes;
  322. struct sk_buff *skb;
  323. struct page *page;
  324. dma_addr_t map;
  325. int length;
  326. rxdes = ftmac100_rx_locate_first_segment(priv);
  327. if (!rxdes)
  328. return false;
  329. if (unlikely(ftmac100_rx_packet_error(priv, rxdes))) {
  330. ftmac100_rx_drop_packet(priv);
  331. return true;
  332. }
  333. /*
  334. * It is impossible to get multi-segment packets
  335. * because we always provide big enough receive buffers.
  336. */
  337. if (unlikely(!ftmac100_rxdes_last_segment(rxdes)))
  338. BUG();
  339. /* start processing */
  340. skb = netdev_alloc_skb_ip_align(netdev, 128);
  341. if (unlikely(!skb)) {
  342. if (net_ratelimit())
  343. netdev_err(netdev, "rx skb alloc failed\n");
  344. ftmac100_rx_drop_packet(priv);
  345. return true;
  346. }
  347. if (unlikely(ftmac100_rxdes_multicast(rxdes)))
  348. netdev->stats.multicast++;
  349. map = ftmac100_rxdes_get_dma_addr(rxdes);
  350. dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
  351. length = ftmac100_rxdes_frame_length(rxdes);
  352. page = ftmac100_rxdes_get_page(rxdes);
  353. skb_fill_page_desc(skb, 0, page, 0, length);
  354. skb->len += length;
  355. skb->data_len += length;
  356. /* page might be freed in __pskb_pull_tail() */
  357. if (length > 64)
  358. skb->truesize += PAGE_SIZE;
  359. __pskb_pull_tail(skb, min(length, 64));
  360. ftmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
  361. ftmac100_rx_pointer_advance(priv);
  362. skb->protocol = eth_type_trans(skb, netdev);
  363. netdev->stats.rx_packets++;
  364. netdev->stats.rx_bytes += skb->len;
  365. /* push packet to protocol stack */
  366. netif_receive_skb(skb);
  367. (*processed)++;
  368. return true;
  369. }
  370. /******************************************************************************
  371. * internal functions (transmit descriptor)
  372. *****************************************************************************/
  373. static void ftmac100_txdes_reset(struct ftmac100_txdes *txdes)
  374. {
  375. /* clear all except end of ring bit */
  376. txdes->txdes0 = 0;
  377. txdes->txdes1 &= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
  378. txdes->txdes2 = 0;
  379. txdes->txdes3 = 0;
  380. }
  381. static bool ftmac100_txdes_owned_by_dma(struct ftmac100_txdes *txdes)
  382. {
  383. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
  384. }
  385. static void ftmac100_txdes_set_dma_own(struct ftmac100_txdes *txdes)
  386. {
  387. /*
  388. * Make sure dma own bit will not be set before any other
  389. * descriptor fields.
  390. */
  391. wmb();
  392. txdes->txdes0 |= cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
  393. }
  394. static bool ftmac100_txdes_excessive_collision(struct ftmac100_txdes *txdes)
  395. {
  396. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_EXSCOL);
  397. }
  398. static bool ftmac100_txdes_late_collision(struct ftmac100_txdes *txdes)
  399. {
  400. return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_LATECOL);
  401. }
  402. static void ftmac100_txdes_set_end_of_ring(struct ftmac100_txdes *txdes)
  403. {
  404. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
  405. }
  406. static void ftmac100_txdes_set_first_segment(struct ftmac100_txdes *txdes)
  407. {
  408. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_FTS);
  409. }
  410. static void ftmac100_txdes_set_last_segment(struct ftmac100_txdes *txdes)
  411. {
  412. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_LTS);
  413. }
  414. static void ftmac100_txdes_set_txint(struct ftmac100_txdes *txdes)
  415. {
  416. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXIC);
  417. }
  418. static void ftmac100_txdes_set_buffer_size(struct ftmac100_txdes *txdes,
  419. unsigned int len)
  420. {
  421. txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXBUF_SIZE(len));
  422. }
  423. static void ftmac100_txdes_set_dma_addr(struct ftmac100_txdes *txdes,
  424. dma_addr_t addr)
  425. {
  426. txdes->txdes2 = cpu_to_le32(addr);
  427. }
  428. static dma_addr_t ftmac100_txdes_get_dma_addr(struct ftmac100_txdes *txdes)
  429. {
  430. return le32_to_cpu(txdes->txdes2);
  431. }
  432. /*
  433. * txdes3 is not used by hardware. We use it to keep track of socket buffer.
  434. * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
  435. */
  436. static void ftmac100_txdes_set_skb(struct ftmac100_txdes *txdes, struct sk_buff *skb)
  437. {
  438. txdes->txdes3 = (unsigned int)skb;
  439. }
  440. static struct sk_buff *ftmac100_txdes_get_skb(struct ftmac100_txdes *txdes)
  441. {
  442. return (struct sk_buff *)txdes->txdes3;
  443. }
  444. /******************************************************************************
  445. * internal functions (transmit)
  446. *****************************************************************************/
  447. static int ftmac100_next_tx_pointer(int pointer)
  448. {
  449. return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
  450. }
  451. static void ftmac100_tx_pointer_advance(struct ftmac100 *priv)
  452. {
  453. priv->tx_pointer = ftmac100_next_tx_pointer(priv->tx_pointer);
  454. }
  455. static void ftmac100_tx_clean_pointer_advance(struct ftmac100 *priv)
  456. {
  457. priv->tx_clean_pointer = ftmac100_next_tx_pointer(priv->tx_clean_pointer);
  458. }
  459. static struct ftmac100_txdes *ftmac100_current_txdes(struct ftmac100 *priv)
  460. {
  461. return &priv->descs->txdes[priv->tx_pointer];
  462. }
  463. static struct ftmac100_txdes *ftmac100_current_clean_txdes(struct ftmac100 *priv)
  464. {
  465. return &priv->descs->txdes[priv->tx_clean_pointer];
  466. }
  467. static bool ftmac100_tx_complete_packet(struct ftmac100 *priv)
  468. {
  469. struct net_device *netdev = priv->netdev;
  470. struct ftmac100_txdes *txdes;
  471. struct sk_buff *skb;
  472. dma_addr_t map;
  473. if (priv->tx_pending == 0)
  474. return false;
  475. txdes = ftmac100_current_clean_txdes(priv);
  476. if (ftmac100_txdes_owned_by_dma(txdes))
  477. return false;
  478. skb = ftmac100_txdes_get_skb(txdes);
  479. map = ftmac100_txdes_get_dma_addr(txdes);
  480. if (unlikely(ftmac100_txdes_excessive_collision(txdes) ||
  481. ftmac100_txdes_late_collision(txdes))) {
  482. /*
  483. * packet transmitted to ethernet lost due to late collision
  484. * or excessive collision
  485. */
  486. netdev->stats.tx_aborted_errors++;
  487. } else {
  488. netdev->stats.tx_packets++;
  489. netdev->stats.tx_bytes += skb->len;
  490. }
  491. dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
  492. dev_kfree_skb(skb);
  493. ftmac100_txdes_reset(txdes);
  494. ftmac100_tx_clean_pointer_advance(priv);
  495. spin_lock(&priv->tx_lock);
  496. priv->tx_pending--;
  497. spin_unlock(&priv->tx_lock);
  498. netif_wake_queue(netdev);
  499. return true;
  500. }
  501. static void ftmac100_tx_complete(struct ftmac100 *priv)
  502. {
  503. while (ftmac100_tx_complete_packet(priv))
  504. ;
  505. }
  506. static int ftmac100_xmit(struct ftmac100 *priv, struct sk_buff *skb,
  507. dma_addr_t map)
  508. {
  509. struct net_device *netdev = priv->netdev;
  510. struct ftmac100_txdes *txdes;
  511. unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
  512. txdes = ftmac100_current_txdes(priv);
  513. ftmac100_tx_pointer_advance(priv);
  514. /* setup TX descriptor */
  515. ftmac100_txdes_set_skb(txdes, skb);
  516. ftmac100_txdes_set_dma_addr(txdes, map);
  517. ftmac100_txdes_set_first_segment(txdes);
  518. ftmac100_txdes_set_last_segment(txdes);
  519. ftmac100_txdes_set_txint(txdes);
  520. ftmac100_txdes_set_buffer_size(txdes, len);
  521. spin_lock(&priv->tx_lock);
  522. priv->tx_pending++;
  523. if (priv->tx_pending == TX_QUEUE_ENTRIES)
  524. netif_stop_queue(netdev);
  525. /* start transmit */
  526. ftmac100_txdes_set_dma_own(txdes);
  527. spin_unlock(&priv->tx_lock);
  528. ftmac100_txdma_start_polling(priv);
  529. return NETDEV_TX_OK;
  530. }
  531. /******************************************************************************
  532. * internal functions (buffer)
  533. *****************************************************************************/
  534. static int ftmac100_alloc_rx_page(struct ftmac100 *priv,
  535. struct ftmac100_rxdes *rxdes, gfp_t gfp)
  536. {
  537. struct net_device *netdev = priv->netdev;
  538. struct page *page;
  539. dma_addr_t map;
  540. page = alloc_page(gfp);
  541. if (!page) {
  542. if (net_ratelimit())
  543. netdev_err(netdev, "failed to allocate rx page\n");
  544. return -ENOMEM;
  545. }
  546. map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
  547. if (unlikely(dma_mapping_error(priv->dev, map))) {
  548. if (net_ratelimit())
  549. netdev_err(netdev, "failed to map rx page\n");
  550. __free_page(page);
  551. return -ENOMEM;
  552. }
  553. ftmac100_rxdes_set_page(rxdes, page);
  554. ftmac100_rxdes_set_dma_addr(rxdes, map);
  555. ftmac100_rxdes_set_buffer_size(rxdes, RX_BUF_SIZE);
  556. ftmac100_rxdes_set_dma_own(rxdes);
  557. return 0;
  558. }
  559. static void ftmac100_free_buffers(struct ftmac100 *priv)
  560. {
  561. int i;
  562. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  563. struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
  564. struct page *page = ftmac100_rxdes_get_page(rxdes);
  565. dma_addr_t map = ftmac100_rxdes_get_dma_addr(rxdes);
  566. if (!page)
  567. continue;
  568. dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
  569. __free_page(page);
  570. }
  571. for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
  572. struct ftmac100_txdes *txdes = &priv->descs->txdes[i];
  573. struct sk_buff *skb = ftmac100_txdes_get_skb(txdes);
  574. dma_addr_t map = ftmac100_txdes_get_dma_addr(txdes);
  575. if (!skb)
  576. continue;
  577. dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
  578. dev_kfree_skb(skb);
  579. }
  580. dma_free_coherent(priv->dev, sizeof(struct ftmac100_descs),
  581. priv->descs, priv->descs_dma_addr);
  582. }
  583. static int ftmac100_alloc_buffers(struct ftmac100 *priv)
  584. {
  585. int i;
  586. priv->descs = dma_alloc_coherent(priv->dev, sizeof(struct ftmac100_descs),
  587. &priv->descs_dma_addr, GFP_KERNEL);
  588. if (!priv->descs)
  589. return -ENOMEM;
  590. memset(priv->descs, 0, sizeof(struct ftmac100_descs));
  591. /* initialize RX ring */
  592. ftmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
  593. for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
  594. struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
  595. if (ftmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
  596. goto err;
  597. }
  598. /* initialize TX ring */
  599. ftmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
  600. return 0;
  601. err:
  602. ftmac100_free_buffers(priv);
  603. return -ENOMEM;
  604. }
  605. /******************************************************************************
  606. * struct mii_if_info functions
  607. *****************************************************************************/
  608. static int ftmac100_mdio_read(struct net_device *netdev, int phy_id, int reg)
  609. {
  610. struct ftmac100 *priv = netdev_priv(netdev);
  611. unsigned int phycr;
  612. int i;
  613. phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
  614. FTMAC100_PHYCR_REGAD(reg) |
  615. FTMAC100_PHYCR_MIIRD;
  616. iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
  617. for (i = 0; i < 10; i++) {
  618. phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
  619. if ((phycr & FTMAC100_PHYCR_MIIRD) == 0)
  620. return phycr & FTMAC100_PHYCR_MIIRDATA;
  621. udelay(100);
  622. }
  623. netdev_err(netdev, "mdio read timed out\n");
  624. return 0;
  625. }
  626. static void ftmac100_mdio_write(struct net_device *netdev, int phy_id, int reg,
  627. int data)
  628. {
  629. struct ftmac100 *priv = netdev_priv(netdev);
  630. unsigned int phycr;
  631. int i;
  632. phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
  633. FTMAC100_PHYCR_REGAD(reg) |
  634. FTMAC100_PHYCR_MIIWR;
  635. data = FTMAC100_PHYWDATA_MIIWDATA(data);
  636. iowrite32(data, priv->base + FTMAC100_OFFSET_PHYWDATA);
  637. iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
  638. for (i = 0; i < 10; i++) {
  639. phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
  640. if ((phycr & FTMAC100_PHYCR_MIIWR) == 0)
  641. return;
  642. udelay(100);
  643. }
  644. netdev_err(netdev, "mdio write timed out\n");
  645. }
  646. /******************************************************************************
  647. * struct ethtool_ops functions
  648. *****************************************************************************/
  649. static void ftmac100_get_drvinfo(struct net_device *netdev,
  650. struct ethtool_drvinfo *info)
  651. {
  652. strcpy(info->driver, DRV_NAME);
  653. strcpy(info->version, DRV_VERSION);
  654. strcpy(info->bus_info, dev_name(&netdev->dev));
  655. }
  656. static int ftmac100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  657. {
  658. struct ftmac100 *priv = netdev_priv(netdev);
  659. return mii_ethtool_gset(&priv->mii, cmd);
  660. }
  661. static int ftmac100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  662. {
  663. struct ftmac100 *priv = netdev_priv(netdev);
  664. return mii_ethtool_sset(&priv->mii, cmd);
  665. }
  666. static int ftmac100_nway_reset(struct net_device *netdev)
  667. {
  668. struct ftmac100 *priv = netdev_priv(netdev);
  669. return mii_nway_restart(&priv->mii);
  670. }
  671. static u32 ftmac100_get_link(struct net_device *netdev)
  672. {
  673. struct ftmac100 *priv = netdev_priv(netdev);
  674. return mii_link_ok(&priv->mii);
  675. }
  676. static const struct ethtool_ops ftmac100_ethtool_ops = {
  677. .set_settings = ftmac100_set_settings,
  678. .get_settings = ftmac100_get_settings,
  679. .get_drvinfo = ftmac100_get_drvinfo,
  680. .nway_reset = ftmac100_nway_reset,
  681. .get_link = ftmac100_get_link,
  682. };
  683. /******************************************************************************
  684. * interrupt handler
  685. *****************************************************************************/
  686. static irqreturn_t ftmac100_interrupt(int irq, void *dev_id)
  687. {
  688. struct net_device *netdev = dev_id;
  689. struct ftmac100 *priv = netdev_priv(netdev);
  690. if (likely(netif_running(netdev))) {
  691. /* Disable interrupts for polling */
  692. ftmac100_disable_all_int(priv);
  693. napi_schedule(&priv->napi);
  694. }
  695. return IRQ_HANDLED;
  696. }
  697. /******************************************************************************
  698. * struct napi_struct functions
  699. *****************************************************************************/
  700. static int ftmac100_poll(struct napi_struct *napi, int budget)
  701. {
  702. struct ftmac100 *priv = container_of(napi, struct ftmac100, napi);
  703. struct net_device *netdev = priv->netdev;
  704. unsigned int status;
  705. bool completed = true;
  706. int rx = 0;
  707. status = ioread32(priv->base + FTMAC100_OFFSET_ISR);
  708. if (status & (FTMAC100_INT_RPKT_FINISH | FTMAC100_INT_NORXBUF)) {
  709. /*
  710. * FTMAC100_INT_RPKT_FINISH:
  711. * RX DMA has received packets into RX buffer successfully
  712. *
  713. * FTMAC100_INT_NORXBUF:
  714. * RX buffer unavailable
  715. */
  716. bool retry;
  717. do {
  718. retry = ftmac100_rx_packet(priv, &rx);
  719. } while (retry && rx < budget);
  720. if (retry && rx == budget)
  721. completed = false;
  722. }
  723. if (status & (FTMAC100_INT_XPKT_OK | FTMAC100_INT_XPKT_LOST)) {
  724. /*
  725. * FTMAC100_INT_XPKT_OK:
  726. * packet transmitted to ethernet successfully
  727. *
  728. * FTMAC100_INT_XPKT_LOST:
  729. * packet transmitted to ethernet lost due to late
  730. * collision or excessive collision
  731. */
  732. ftmac100_tx_complete(priv);
  733. }
  734. if (status & (FTMAC100_INT_NORXBUF | FTMAC100_INT_RPKT_LOST |
  735. FTMAC100_INT_AHB_ERR | FTMAC100_INT_PHYSTS_CHG)) {
  736. if (net_ratelimit())
  737. netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
  738. status & FTMAC100_INT_NORXBUF ? "NORXBUF " : "",
  739. status & FTMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
  740. status & FTMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
  741. status & FTMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
  742. if (status & FTMAC100_INT_NORXBUF) {
  743. /* RX buffer unavailable */
  744. netdev->stats.rx_over_errors++;
  745. }
  746. if (status & FTMAC100_INT_RPKT_LOST) {
  747. /* received packet lost due to RX FIFO full */
  748. netdev->stats.rx_fifo_errors++;
  749. }
  750. if (status & FTMAC100_INT_PHYSTS_CHG) {
  751. /* PHY link status change */
  752. mii_check_link(&priv->mii);
  753. }
  754. }
  755. if (completed) {
  756. /* stop polling */
  757. napi_complete(napi);
  758. ftmac100_enable_all_int(priv);
  759. }
  760. return rx;
  761. }
  762. /******************************************************************************
  763. * struct net_device_ops functions
  764. *****************************************************************************/
  765. static int ftmac100_open(struct net_device *netdev)
  766. {
  767. struct ftmac100 *priv = netdev_priv(netdev);
  768. int err;
  769. err = ftmac100_alloc_buffers(priv);
  770. if (err) {
  771. netdev_err(netdev, "failed to allocate buffers\n");
  772. goto err_alloc;
  773. }
  774. err = request_irq(priv->irq, ftmac100_interrupt, 0, netdev->name, netdev);
  775. if (err) {
  776. netdev_err(netdev, "failed to request irq %d\n", priv->irq);
  777. goto err_irq;
  778. }
  779. priv->rx_pointer = 0;
  780. priv->tx_clean_pointer = 0;
  781. priv->tx_pointer = 0;
  782. priv->tx_pending = 0;
  783. err = ftmac100_start_hw(priv);
  784. if (err)
  785. goto err_hw;
  786. napi_enable(&priv->napi);
  787. netif_start_queue(netdev);
  788. ftmac100_enable_all_int(priv);
  789. return 0;
  790. err_hw:
  791. free_irq(priv->irq, netdev);
  792. err_irq:
  793. ftmac100_free_buffers(priv);
  794. err_alloc:
  795. return err;
  796. }
  797. static int ftmac100_stop(struct net_device *netdev)
  798. {
  799. struct ftmac100 *priv = netdev_priv(netdev);
  800. ftmac100_disable_all_int(priv);
  801. netif_stop_queue(netdev);
  802. napi_disable(&priv->napi);
  803. ftmac100_stop_hw(priv);
  804. free_irq(priv->irq, netdev);
  805. ftmac100_free_buffers(priv);
  806. return 0;
  807. }
  808. static int ftmac100_hard_start_xmit(struct sk_buff *skb, struct net_device *netdev)
  809. {
  810. struct ftmac100 *priv = netdev_priv(netdev);
  811. dma_addr_t map;
  812. if (unlikely(skb->len > MAX_PKT_SIZE)) {
  813. if (net_ratelimit())
  814. netdev_dbg(netdev, "tx packet too big\n");
  815. netdev->stats.tx_dropped++;
  816. dev_kfree_skb(skb);
  817. return NETDEV_TX_OK;
  818. }
  819. map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
  820. if (unlikely(dma_mapping_error(priv->dev, map))) {
  821. /* drop packet */
  822. if (net_ratelimit())
  823. netdev_err(netdev, "map socket buffer failed\n");
  824. netdev->stats.tx_dropped++;
  825. dev_kfree_skb(skb);
  826. return NETDEV_TX_OK;
  827. }
  828. return ftmac100_xmit(priv, skb, map);
  829. }
  830. /* optional */
  831. static int ftmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  832. {
  833. struct ftmac100 *priv = netdev_priv(netdev);
  834. struct mii_ioctl_data *data = if_mii(ifr);
  835. return generic_mii_ioctl(&priv->mii, data, cmd, NULL);
  836. }
  837. static const struct net_device_ops ftmac100_netdev_ops = {
  838. .ndo_open = ftmac100_open,
  839. .ndo_stop = ftmac100_stop,
  840. .ndo_start_xmit = ftmac100_hard_start_xmit,
  841. .ndo_set_mac_address = eth_mac_addr,
  842. .ndo_validate_addr = eth_validate_addr,
  843. .ndo_do_ioctl = ftmac100_do_ioctl,
  844. };
  845. /******************************************************************************
  846. * struct platform_driver functions
  847. *****************************************************************************/
  848. static int ftmac100_probe(struct platform_device *pdev)
  849. {
  850. struct resource *res;
  851. int irq;
  852. struct net_device *netdev;
  853. struct ftmac100 *priv;
  854. int err;
  855. if (!pdev)
  856. return -ENODEV;
  857. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  858. if (!res)
  859. return -ENXIO;
  860. irq = platform_get_irq(pdev, 0);
  861. if (irq < 0)
  862. return irq;
  863. /* setup net_device */
  864. netdev = alloc_etherdev(sizeof(*priv));
  865. if (!netdev) {
  866. err = -ENOMEM;
  867. goto err_alloc_etherdev;
  868. }
  869. SET_NETDEV_DEV(netdev, &pdev->dev);
  870. SET_ETHTOOL_OPS(netdev, &ftmac100_ethtool_ops);
  871. netdev->netdev_ops = &ftmac100_netdev_ops;
  872. platform_set_drvdata(pdev, netdev);
  873. /* setup private data */
  874. priv = netdev_priv(netdev);
  875. priv->netdev = netdev;
  876. priv->dev = &pdev->dev;
  877. spin_lock_init(&priv->tx_lock);
  878. /* initialize NAPI */
  879. netif_napi_add(netdev, &priv->napi, ftmac100_poll, 64);
  880. /* map io memory */
  881. priv->res = request_mem_region(res->start, resource_size(res),
  882. dev_name(&pdev->dev));
  883. if (!priv->res) {
  884. dev_err(&pdev->dev, "Could not reserve memory region\n");
  885. err = -ENOMEM;
  886. goto err_req_mem;
  887. }
  888. priv->base = ioremap(res->start, resource_size(res));
  889. if (!priv->base) {
  890. dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
  891. err = -EIO;
  892. goto err_ioremap;
  893. }
  894. priv->irq = irq;
  895. /* initialize struct mii_if_info */
  896. priv->mii.phy_id = 0;
  897. priv->mii.phy_id_mask = 0x1f;
  898. priv->mii.reg_num_mask = 0x1f;
  899. priv->mii.dev = netdev;
  900. priv->mii.mdio_read = ftmac100_mdio_read;
  901. priv->mii.mdio_write = ftmac100_mdio_write;
  902. /* register network device */
  903. err = register_netdev(netdev);
  904. if (err) {
  905. dev_err(&pdev->dev, "Failed to register netdev\n");
  906. goto err_register_netdev;
  907. }
  908. netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
  909. if (!is_valid_ether_addr(netdev->dev_addr)) {
  910. eth_hw_addr_random(netdev);
  911. netdev_info(netdev, "generated random MAC address %pM\n",
  912. netdev->dev_addr);
  913. }
  914. return 0;
  915. err_register_netdev:
  916. iounmap(priv->base);
  917. err_ioremap:
  918. release_resource(priv->res);
  919. err_req_mem:
  920. netif_napi_del(&priv->napi);
  921. platform_set_drvdata(pdev, NULL);
  922. free_netdev(netdev);
  923. err_alloc_etherdev:
  924. return err;
  925. }
  926. static int __exit ftmac100_remove(struct platform_device *pdev)
  927. {
  928. struct net_device *netdev;
  929. struct ftmac100 *priv;
  930. netdev = platform_get_drvdata(pdev);
  931. priv = netdev_priv(netdev);
  932. unregister_netdev(netdev);
  933. iounmap(priv->base);
  934. release_resource(priv->res);
  935. netif_napi_del(&priv->napi);
  936. platform_set_drvdata(pdev, NULL);
  937. free_netdev(netdev);
  938. return 0;
  939. }
  940. static struct platform_driver ftmac100_driver = {
  941. .probe = ftmac100_probe,
  942. .remove = __exit_p(ftmac100_remove),
  943. .driver = {
  944. .name = DRV_NAME,
  945. .owner = THIS_MODULE,
  946. },
  947. };
  948. /******************************************************************************
  949. * initialization / finalization
  950. *****************************************************************************/
  951. static int __init ftmac100_init(void)
  952. {
  953. pr_info("Loading version " DRV_VERSION " ...\n");
  954. return platform_driver_register(&ftmac100_driver);
  955. }
  956. static void __exit ftmac100_exit(void)
  957. {
  958. platform_driver_unregister(&ftmac100_driver);
  959. }
  960. module_init(ftmac100_init);
  961. module_exit(ftmac100_exit);
  962. MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
  963. MODULE_DESCRIPTION("FTMAC100 driver");
  964. MODULE_LICENSE("GPL");