r592.c 22 KB

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  1. /*
  2. * Copyright (C) 2010 - Maxim Levitsky
  3. * driver for Ricoh memstick readers
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/freezer.h>
  12. #include <linux/jiffies.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/pci.h>
  15. #include <linux/pci_ids.h>
  16. #include <linux/delay.h>
  17. #include <linux/slab.h>
  18. #include <linux/kthread.h>
  19. #include <linux/sched.h>
  20. #include <linux/highmem.h>
  21. #include <asm/byteorder.h>
  22. #include <linux/swab.h>
  23. #include "r592.h"
  24. static bool r592_enable_dma = 1;
  25. static int debug;
  26. static const char *tpc_names[] = {
  27. "MS_TPC_READ_MG_STATUS",
  28. "MS_TPC_READ_LONG_DATA",
  29. "MS_TPC_READ_SHORT_DATA",
  30. "MS_TPC_READ_REG",
  31. "MS_TPC_READ_QUAD_DATA",
  32. "INVALID",
  33. "MS_TPC_GET_INT",
  34. "MS_TPC_SET_RW_REG_ADRS",
  35. "MS_TPC_EX_SET_CMD",
  36. "MS_TPC_WRITE_QUAD_DATA",
  37. "MS_TPC_WRITE_REG",
  38. "MS_TPC_WRITE_SHORT_DATA",
  39. "MS_TPC_WRITE_LONG_DATA",
  40. "MS_TPC_SET_CMD",
  41. };
  42. /**
  43. * memstick_debug_get_tpc_name - debug helper that returns string for
  44. * a TPC number
  45. */
  46. const char *memstick_debug_get_tpc_name(int tpc)
  47. {
  48. return tpc_names[tpc-1];
  49. }
  50. EXPORT_SYMBOL(memstick_debug_get_tpc_name);
  51. /* Read a register*/
  52. static inline u32 r592_read_reg(struct r592_device *dev, int address)
  53. {
  54. u32 value = readl(dev->mmio + address);
  55. dbg_reg("reg #%02d == 0x%08x", address, value);
  56. return value;
  57. }
  58. /* Write a register */
  59. static inline void r592_write_reg(struct r592_device *dev,
  60. int address, u32 value)
  61. {
  62. dbg_reg("reg #%02d <- 0x%08x", address, value);
  63. writel(value, dev->mmio + address);
  64. }
  65. /* Reads a big endian DWORD register */
  66. static inline u32 r592_read_reg_raw_be(struct r592_device *dev, int address)
  67. {
  68. u32 value = __raw_readl(dev->mmio + address);
  69. dbg_reg("reg #%02d == 0x%08x", address, value);
  70. return be32_to_cpu(value);
  71. }
  72. /* Writes a big endian DWORD register */
  73. static inline void r592_write_reg_raw_be(struct r592_device *dev,
  74. int address, u32 value)
  75. {
  76. dbg_reg("reg #%02d <- 0x%08x", address, value);
  77. __raw_writel(cpu_to_be32(value), dev->mmio + address);
  78. }
  79. /* Set specific bits in a register (little endian) */
  80. static inline void r592_set_reg_mask(struct r592_device *dev,
  81. int address, u32 mask)
  82. {
  83. u32 reg = readl(dev->mmio + address);
  84. dbg_reg("reg #%02d |= 0x%08x (old =0x%08x)", address, mask, reg);
  85. writel(reg | mask , dev->mmio + address);
  86. }
  87. /* Clear specific bits in a register (little endian) */
  88. static inline void r592_clear_reg_mask(struct r592_device *dev,
  89. int address, u32 mask)
  90. {
  91. u32 reg = readl(dev->mmio + address);
  92. dbg_reg("reg #%02d &= 0x%08x (old = 0x%08x, mask = 0x%08x)",
  93. address, ~mask, reg, mask);
  94. writel(reg & ~mask, dev->mmio + address);
  95. }
  96. /* Wait for status bits while checking for errors */
  97. static int r592_wait_status(struct r592_device *dev, u32 mask, u32 wanted_mask)
  98. {
  99. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  100. u32 reg = r592_read_reg(dev, R592_STATUS);
  101. if ((reg & mask) == wanted_mask)
  102. return 0;
  103. while (time_before(jiffies, timeout)) {
  104. reg = r592_read_reg(dev, R592_STATUS);
  105. if ((reg & mask) == wanted_mask)
  106. return 0;
  107. if (reg & (R592_STATUS_SEND_ERR | R592_STATUS_RECV_ERR))
  108. return -EIO;
  109. cpu_relax();
  110. }
  111. return -ETIME;
  112. }
  113. /* Enable/disable device */
  114. static int r592_enable_device(struct r592_device *dev, bool enable)
  115. {
  116. dbg("%sabling the device", enable ? "en" : "dis");
  117. if (enable) {
  118. /* Power up the card */
  119. r592_write_reg(dev, R592_POWER, R592_POWER_0 | R592_POWER_1);
  120. /* Perform a reset */
  121. r592_set_reg_mask(dev, R592_IO, R592_IO_RESET);
  122. msleep(100);
  123. } else
  124. /* Power down the card */
  125. r592_write_reg(dev, R592_POWER, 0);
  126. return 0;
  127. }
  128. /* Set serial/parallel mode */
  129. static int r592_set_mode(struct r592_device *dev, bool parallel_mode)
  130. {
  131. if (!parallel_mode) {
  132. dbg("switching to serial mode");
  133. /* Set serial mode */
  134. r592_write_reg(dev, R592_IO_MODE, R592_IO_MODE_SERIAL);
  135. r592_clear_reg_mask(dev, R592_POWER, R592_POWER_20);
  136. } else {
  137. dbg("switching to parallel mode");
  138. /* This setting should be set _before_ switch TPC */
  139. r592_set_reg_mask(dev, R592_POWER, R592_POWER_20);
  140. r592_clear_reg_mask(dev, R592_IO,
  141. R592_IO_SERIAL1 | R592_IO_SERIAL2);
  142. /* Set the parallel mode now */
  143. r592_write_reg(dev, R592_IO_MODE, R592_IO_MODE_PARALLEL);
  144. }
  145. dev->parallel_mode = parallel_mode;
  146. return 0;
  147. }
  148. /* Perform a controller reset without powering down the card */
  149. static void r592_host_reset(struct r592_device *dev)
  150. {
  151. r592_set_reg_mask(dev, R592_IO, R592_IO_RESET);
  152. msleep(100);
  153. r592_set_mode(dev, dev->parallel_mode);
  154. }
  155. /* Disable all hardware interrupts */
  156. static void r592_clear_interrupts(struct r592_device *dev)
  157. {
  158. /* Disable & ACK all interrupts */
  159. r592_clear_reg_mask(dev, R592_REG_MSC, IRQ_ALL_ACK_MASK);
  160. r592_clear_reg_mask(dev, R592_REG_MSC, IRQ_ALL_EN_MASK);
  161. }
  162. /* Tests if there is an CRC error */
  163. static int r592_test_io_error(struct r592_device *dev)
  164. {
  165. if (!(r592_read_reg(dev, R592_STATUS) &
  166. (R592_STATUS_SEND_ERR | R592_STATUS_RECV_ERR)))
  167. return 0;
  168. return -EIO;
  169. }
  170. /* Ensure that FIFO is ready for use */
  171. static int r592_test_fifo_empty(struct r592_device *dev)
  172. {
  173. if (r592_read_reg(dev, R592_REG_MSC) & R592_REG_MSC_FIFO_EMPTY)
  174. return 0;
  175. dbg("FIFO not ready, trying to reset the device");
  176. r592_host_reset(dev);
  177. if (r592_read_reg(dev, R592_REG_MSC) & R592_REG_MSC_FIFO_EMPTY)
  178. return 0;
  179. message("FIFO still not ready, giving up");
  180. return -EIO;
  181. }
  182. /* Activates the DMA transfer from to FIFO */
  183. static void r592_start_dma(struct r592_device *dev, bool is_write)
  184. {
  185. unsigned long flags;
  186. u32 reg;
  187. spin_lock_irqsave(&dev->irq_lock, flags);
  188. /* Ack interrupts (just in case) + enable them */
  189. r592_clear_reg_mask(dev, R592_REG_MSC, DMA_IRQ_ACK_MASK);
  190. r592_set_reg_mask(dev, R592_REG_MSC, DMA_IRQ_EN_MASK);
  191. /* Set DMA address */
  192. r592_write_reg(dev, R592_FIFO_DMA, sg_dma_address(&dev->req->sg));
  193. /* Enable the DMA */
  194. reg = r592_read_reg(dev, R592_FIFO_DMA_SETTINGS);
  195. reg |= R592_FIFO_DMA_SETTINGS_EN;
  196. if (!is_write)
  197. reg |= R592_FIFO_DMA_SETTINGS_DIR;
  198. else
  199. reg &= ~R592_FIFO_DMA_SETTINGS_DIR;
  200. r592_write_reg(dev, R592_FIFO_DMA_SETTINGS, reg);
  201. spin_unlock_irqrestore(&dev->irq_lock, flags);
  202. }
  203. /* Cleanups DMA related settings */
  204. static void r592_stop_dma(struct r592_device *dev, int error)
  205. {
  206. r592_clear_reg_mask(dev, R592_FIFO_DMA_SETTINGS,
  207. R592_FIFO_DMA_SETTINGS_EN);
  208. /* This is only a precation */
  209. r592_write_reg(dev, R592_FIFO_DMA,
  210. dev->dummy_dma_page_physical_address);
  211. r592_clear_reg_mask(dev, R592_REG_MSC, DMA_IRQ_EN_MASK);
  212. r592_clear_reg_mask(dev, R592_REG_MSC, DMA_IRQ_ACK_MASK);
  213. dev->dma_error = error;
  214. }
  215. /* Test if hardware supports DMA */
  216. static void r592_check_dma(struct r592_device *dev)
  217. {
  218. dev->dma_capable = r592_enable_dma &&
  219. (r592_read_reg(dev, R592_FIFO_DMA_SETTINGS) &
  220. R592_FIFO_DMA_SETTINGS_CAP);
  221. }
  222. /* Transfers fifo contents in/out using DMA */
  223. static int r592_transfer_fifo_dma(struct r592_device *dev)
  224. {
  225. int len, sg_count;
  226. bool is_write;
  227. if (!dev->dma_capable || !dev->req->long_data)
  228. return -EINVAL;
  229. len = dev->req->sg.length;
  230. is_write = dev->req->data_dir == WRITE;
  231. if (len != R592_LFIFO_SIZE)
  232. return -EINVAL;
  233. dbg_verbose("doing dma transfer");
  234. dev->dma_error = 0;
  235. INIT_COMPLETION(dev->dma_done);
  236. /* TODO: hidden assumption about nenth beeing always 1 */
  237. sg_count = dma_map_sg(&dev->pci_dev->dev, &dev->req->sg, 1, is_write ?
  238. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  239. if (sg_count != 1 ||
  240. (sg_dma_len(&dev->req->sg) < dev->req->sg.length)) {
  241. message("problem in dma_map_sg");
  242. return -EIO;
  243. }
  244. r592_start_dma(dev, is_write);
  245. /* Wait for DMA completion */
  246. if (!wait_for_completion_timeout(
  247. &dev->dma_done, msecs_to_jiffies(1000))) {
  248. message("DMA timeout");
  249. r592_stop_dma(dev, -ETIMEDOUT);
  250. }
  251. dma_unmap_sg(&dev->pci_dev->dev, &dev->req->sg, 1, is_write ?
  252. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  253. return dev->dma_error;
  254. }
  255. /*
  256. * Writes the FIFO in 4 byte chunks.
  257. * If length isn't 4 byte aligned, rest of the data if put to a fifo
  258. * to be written later
  259. * Use r592_flush_fifo_write to flush that fifo when writing for the
  260. * last time
  261. */
  262. static void r592_write_fifo_pio(struct r592_device *dev,
  263. unsigned char *buffer, int len)
  264. {
  265. /* flush spill from former write */
  266. if (!kfifo_is_empty(&dev->pio_fifo)) {
  267. u8 tmp[4] = {0};
  268. int copy_len = kfifo_in(&dev->pio_fifo, buffer, len);
  269. if (!kfifo_is_full(&dev->pio_fifo))
  270. return;
  271. len -= copy_len;
  272. buffer += copy_len;
  273. copy_len = kfifo_out(&dev->pio_fifo, tmp, 4);
  274. WARN_ON(copy_len != 4);
  275. r592_write_reg_raw_be(dev, R592_FIFO_PIO, *(u32 *)tmp);
  276. }
  277. WARN_ON(!kfifo_is_empty(&dev->pio_fifo));
  278. /* write full dwords */
  279. while (len >= 4) {
  280. r592_write_reg_raw_be(dev, R592_FIFO_PIO, *(u32 *)buffer);
  281. buffer += 4;
  282. len -= 4;
  283. }
  284. /* put remaining bytes to the spill */
  285. if (len)
  286. kfifo_in(&dev->pio_fifo, buffer, len);
  287. }
  288. /* Flushes the temporary FIFO used to make aligned DWORD writes */
  289. static void r592_flush_fifo_write(struct r592_device *dev)
  290. {
  291. u8 buffer[4] = { 0 };
  292. int len;
  293. if (kfifo_is_empty(&dev->pio_fifo))
  294. return;
  295. len = kfifo_out(&dev->pio_fifo, buffer, 4);
  296. r592_write_reg_raw_be(dev, R592_FIFO_PIO, *(u32 *)buffer);
  297. }
  298. /*
  299. * Read a fifo in 4 bytes chunks.
  300. * If input doesn't fit the buffer, it places bytes of last dword in spill
  301. * buffer, so that they don't get lost on last read, just throw these away.
  302. */
  303. static void r592_read_fifo_pio(struct r592_device *dev,
  304. unsigned char *buffer, int len)
  305. {
  306. u8 tmp[4];
  307. /* Read from last spill */
  308. if (!kfifo_is_empty(&dev->pio_fifo)) {
  309. int bytes_copied =
  310. kfifo_out(&dev->pio_fifo, buffer, min(4, len));
  311. buffer += bytes_copied;
  312. len -= bytes_copied;
  313. if (!kfifo_is_empty(&dev->pio_fifo))
  314. return;
  315. }
  316. /* Reads dwords from FIFO */
  317. while (len >= 4) {
  318. *(u32 *)buffer = r592_read_reg_raw_be(dev, R592_FIFO_PIO);
  319. buffer += 4;
  320. len -= 4;
  321. }
  322. if (len) {
  323. *(u32 *)tmp = r592_read_reg_raw_be(dev, R592_FIFO_PIO);
  324. kfifo_in(&dev->pio_fifo, tmp, 4);
  325. len -= kfifo_out(&dev->pio_fifo, buffer, len);
  326. }
  327. WARN_ON(len);
  328. return;
  329. }
  330. /* Transfers actual data using PIO. */
  331. static int r592_transfer_fifo_pio(struct r592_device *dev)
  332. {
  333. unsigned long flags;
  334. bool is_write = dev->req->tpc >= MS_TPC_SET_RW_REG_ADRS;
  335. struct sg_mapping_iter miter;
  336. kfifo_reset(&dev->pio_fifo);
  337. if (!dev->req->long_data) {
  338. if (is_write) {
  339. r592_write_fifo_pio(dev, dev->req->data,
  340. dev->req->data_len);
  341. r592_flush_fifo_write(dev);
  342. } else
  343. r592_read_fifo_pio(dev, dev->req->data,
  344. dev->req->data_len);
  345. return 0;
  346. }
  347. local_irq_save(flags);
  348. sg_miter_start(&miter, &dev->req->sg, 1, SG_MITER_ATOMIC |
  349. (is_write ? SG_MITER_FROM_SG : SG_MITER_TO_SG));
  350. /* Do the transfer fifo<->memory*/
  351. while (sg_miter_next(&miter))
  352. if (is_write)
  353. r592_write_fifo_pio(dev, miter.addr, miter.length);
  354. else
  355. r592_read_fifo_pio(dev, miter.addr, miter.length);
  356. /* Write last few non aligned bytes*/
  357. if (is_write)
  358. r592_flush_fifo_write(dev);
  359. sg_miter_stop(&miter);
  360. local_irq_restore(flags);
  361. return 0;
  362. }
  363. /* Executes one TPC (data is read/written from small or large fifo) */
  364. static void r592_execute_tpc(struct r592_device *dev)
  365. {
  366. bool is_write = dev->req->tpc >= MS_TPC_SET_RW_REG_ADRS;
  367. int len, error;
  368. u32 status, reg;
  369. if (!dev->req) {
  370. message("BUG: tpc execution without request!");
  371. return;
  372. }
  373. len = dev->req->long_data ?
  374. dev->req->sg.length : dev->req->data_len;
  375. /* Ensure that FIFO can hold the input data */
  376. if (len > R592_LFIFO_SIZE) {
  377. message("IO: hardware doesn't support TPCs longer that 512");
  378. error = -ENOSYS;
  379. goto out;
  380. }
  381. if (!(r592_read_reg(dev, R592_REG_MSC) & R592_REG_MSC_PRSNT)) {
  382. dbg("IO: refusing to send TPC because card is absent");
  383. error = -ENODEV;
  384. goto out;
  385. }
  386. dbg("IO: executing %s LEN=%d",
  387. memstick_debug_get_tpc_name(dev->req->tpc), len);
  388. /* Set IO direction */
  389. if (is_write)
  390. r592_set_reg_mask(dev, R592_IO, R592_IO_DIRECTION);
  391. else
  392. r592_clear_reg_mask(dev, R592_IO, R592_IO_DIRECTION);
  393. error = r592_test_fifo_empty(dev);
  394. if (error)
  395. goto out;
  396. /* Transfer write data */
  397. if (is_write) {
  398. error = r592_transfer_fifo_dma(dev);
  399. if (error == -EINVAL)
  400. error = r592_transfer_fifo_pio(dev);
  401. }
  402. if (error)
  403. goto out;
  404. /* Trigger the TPC */
  405. reg = (len << R592_TPC_EXEC_LEN_SHIFT) |
  406. (dev->req->tpc << R592_TPC_EXEC_TPC_SHIFT) |
  407. R592_TPC_EXEC_BIG_FIFO;
  408. r592_write_reg(dev, R592_TPC_EXEC, reg);
  409. /* Wait for TPC completion */
  410. status = R592_STATUS_RDY;
  411. if (dev->req->need_card_int)
  412. status |= R592_STATUS_CED;
  413. error = r592_wait_status(dev, status, status);
  414. if (error) {
  415. message("card didn't respond");
  416. goto out;
  417. }
  418. /* Test IO errors */
  419. error = r592_test_io_error(dev);
  420. if (error) {
  421. dbg("IO error");
  422. goto out;
  423. }
  424. /* Read data from FIFO */
  425. if (!is_write) {
  426. error = r592_transfer_fifo_dma(dev);
  427. if (error == -EINVAL)
  428. error = r592_transfer_fifo_pio(dev);
  429. }
  430. /* read INT reg. This can be shortened with shifts, but that way
  431. its more readable */
  432. if (dev->parallel_mode && dev->req->need_card_int) {
  433. dev->req->int_reg = 0;
  434. status = r592_read_reg(dev, R592_STATUS);
  435. if (status & R592_STATUS_P_CMDNACK)
  436. dev->req->int_reg |= MEMSTICK_INT_CMDNAK;
  437. if (status & R592_STATUS_P_BREQ)
  438. dev->req->int_reg |= MEMSTICK_INT_BREQ;
  439. if (status & R592_STATUS_P_INTERR)
  440. dev->req->int_reg |= MEMSTICK_INT_ERR;
  441. if (status & R592_STATUS_P_CED)
  442. dev->req->int_reg |= MEMSTICK_INT_CED;
  443. }
  444. if (error)
  445. dbg("FIFO read error");
  446. out:
  447. dev->req->error = error;
  448. r592_clear_reg_mask(dev, R592_REG_MSC, R592_REG_MSC_LED);
  449. return;
  450. }
  451. /* Main request processing thread */
  452. static int r592_process_thread(void *data)
  453. {
  454. int error;
  455. struct r592_device *dev = (struct r592_device *)data;
  456. unsigned long flags;
  457. while (!kthread_should_stop()) {
  458. spin_lock_irqsave(&dev->io_thread_lock, flags);
  459. set_current_state(TASK_INTERRUPTIBLE);
  460. error = memstick_next_req(dev->host, &dev->req);
  461. spin_unlock_irqrestore(&dev->io_thread_lock, flags);
  462. if (error) {
  463. if (error == -ENXIO || error == -EAGAIN) {
  464. dbg_verbose("IO: done IO, sleeping");
  465. } else {
  466. dbg("IO: unknown error from "
  467. "memstick_next_req %d", error);
  468. }
  469. if (kthread_should_stop())
  470. set_current_state(TASK_RUNNING);
  471. schedule();
  472. } else {
  473. set_current_state(TASK_RUNNING);
  474. r592_execute_tpc(dev);
  475. }
  476. }
  477. return 0;
  478. }
  479. /* Reprogram chip to detect change in card state */
  480. /* eg, if card is detected, arm it to detect removal, and vice versa */
  481. static void r592_update_card_detect(struct r592_device *dev)
  482. {
  483. u32 reg = r592_read_reg(dev, R592_REG_MSC);
  484. bool card_detected = reg & R592_REG_MSC_PRSNT;
  485. dbg("update card detect. card state: %s", card_detected ?
  486. "present" : "absent");
  487. reg &= ~((R592_REG_MSC_IRQ_REMOVE | R592_REG_MSC_IRQ_INSERT) << 16);
  488. if (card_detected)
  489. reg |= (R592_REG_MSC_IRQ_REMOVE << 16);
  490. else
  491. reg |= (R592_REG_MSC_IRQ_INSERT << 16);
  492. r592_write_reg(dev, R592_REG_MSC, reg);
  493. }
  494. /* Timer routine that fires 1 second after last card detection event, */
  495. static void r592_detect_timer(long unsigned int data)
  496. {
  497. struct r592_device *dev = (struct r592_device *)data;
  498. r592_update_card_detect(dev);
  499. memstick_detect_change(dev->host);
  500. }
  501. /* Interrupt handler */
  502. static irqreturn_t r592_irq(int irq, void *data)
  503. {
  504. struct r592_device *dev = (struct r592_device *)data;
  505. irqreturn_t ret = IRQ_NONE;
  506. u32 reg;
  507. u16 irq_enable, irq_status;
  508. unsigned long flags;
  509. int error;
  510. spin_lock_irqsave(&dev->irq_lock, flags);
  511. reg = r592_read_reg(dev, R592_REG_MSC);
  512. irq_enable = reg >> 16;
  513. irq_status = reg & 0xFFFF;
  514. /* Ack the interrupts */
  515. reg &= ~irq_status;
  516. r592_write_reg(dev, R592_REG_MSC, reg);
  517. /* Get the IRQ status minus bits that aren't enabled */
  518. irq_status &= (irq_enable);
  519. /* Due to limitation of memstick core, we don't look at bits that
  520. indicate that card was removed/inserted and/or present */
  521. if (irq_status & (R592_REG_MSC_IRQ_INSERT | R592_REG_MSC_IRQ_REMOVE)) {
  522. bool card_was_added = irq_status & R592_REG_MSC_IRQ_INSERT;
  523. ret = IRQ_HANDLED;
  524. message("IRQ: card %s", card_was_added ? "added" : "removed");
  525. mod_timer(&dev->detect_timer,
  526. jiffies + msecs_to_jiffies(card_was_added ? 500 : 50));
  527. }
  528. if (irq_status &
  529. (R592_REG_MSC_FIFO_DMA_DONE | R592_REG_MSC_FIFO_DMA_ERR)) {
  530. ret = IRQ_HANDLED;
  531. if (irq_status & R592_REG_MSC_FIFO_DMA_ERR) {
  532. message("IRQ: DMA error");
  533. error = -EIO;
  534. } else {
  535. dbg_verbose("IRQ: dma done");
  536. error = 0;
  537. }
  538. r592_stop_dma(dev, error);
  539. complete(&dev->dma_done);
  540. }
  541. spin_unlock_irqrestore(&dev->irq_lock, flags);
  542. return ret;
  543. }
  544. /* External inteface: set settings */
  545. static int r592_set_param(struct memstick_host *host,
  546. enum memstick_param param, int value)
  547. {
  548. struct r592_device *dev = memstick_priv(host);
  549. switch (param) {
  550. case MEMSTICK_POWER:
  551. switch (value) {
  552. case MEMSTICK_POWER_ON:
  553. return r592_enable_device(dev, true);
  554. case MEMSTICK_POWER_OFF:
  555. return r592_enable_device(dev, false);
  556. default:
  557. return -EINVAL;
  558. }
  559. case MEMSTICK_INTERFACE:
  560. switch (value) {
  561. case MEMSTICK_SERIAL:
  562. return r592_set_mode(dev, 0);
  563. case MEMSTICK_PAR4:
  564. return r592_set_mode(dev, 1);
  565. default:
  566. return -EINVAL;
  567. }
  568. default:
  569. return -EINVAL;
  570. }
  571. }
  572. /* External interface: submit requests */
  573. static void r592_submit_req(struct memstick_host *host)
  574. {
  575. struct r592_device *dev = memstick_priv(host);
  576. unsigned long flags;
  577. if (dev->req)
  578. return;
  579. spin_lock_irqsave(&dev->io_thread_lock, flags);
  580. if (wake_up_process(dev->io_thread))
  581. dbg_verbose("IO thread woken to process requests");
  582. spin_unlock_irqrestore(&dev->io_thread_lock, flags);
  583. }
  584. static const struct pci_device_id r592_pci_id_tbl[] = {
  585. { PCI_VDEVICE(RICOH, 0x0592), },
  586. { },
  587. };
  588. /* Main entry */
  589. static int r592_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  590. {
  591. int error = -ENOMEM;
  592. struct memstick_host *host;
  593. struct r592_device *dev;
  594. /* Allocate memory */
  595. host = memstick_alloc_host(sizeof(struct r592_device), &pdev->dev);
  596. if (!host)
  597. goto error1;
  598. dev = memstick_priv(host);
  599. dev->host = host;
  600. dev->pci_dev = pdev;
  601. pci_set_drvdata(pdev, dev);
  602. /* pci initialization */
  603. error = pci_enable_device(pdev);
  604. if (error)
  605. goto error2;
  606. pci_set_master(pdev);
  607. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  608. if (error)
  609. goto error3;
  610. error = pci_request_regions(pdev, DRV_NAME);
  611. if (error)
  612. goto error3;
  613. dev->mmio = pci_ioremap_bar(pdev, 0);
  614. if (!dev->mmio)
  615. goto error4;
  616. dev->irq = pdev->irq;
  617. spin_lock_init(&dev->irq_lock);
  618. spin_lock_init(&dev->io_thread_lock);
  619. init_completion(&dev->dma_done);
  620. INIT_KFIFO(dev->pio_fifo);
  621. setup_timer(&dev->detect_timer,
  622. r592_detect_timer, (long unsigned int)dev);
  623. /* Host initialization */
  624. host->caps = MEMSTICK_CAP_PAR4;
  625. host->request = r592_submit_req;
  626. host->set_param = r592_set_param;
  627. r592_check_dma(dev);
  628. dev->io_thread = kthread_run(r592_process_thread, dev, "r592_io");
  629. if (IS_ERR(dev->io_thread)) {
  630. error = PTR_ERR(dev->io_thread);
  631. goto error5;
  632. }
  633. /* This is just a precation, so don't fail */
  634. dev->dummy_dma_page = pci_alloc_consistent(pdev, PAGE_SIZE,
  635. &dev->dummy_dma_page_physical_address);
  636. r592_stop_dma(dev , 0);
  637. if (request_irq(dev->irq, &r592_irq, IRQF_SHARED,
  638. DRV_NAME, dev))
  639. goto error6;
  640. r592_update_card_detect(dev);
  641. if (memstick_add_host(host))
  642. goto error7;
  643. message("driver successfully loaded");
  644. return 0;
  645. error7:
  646. free_irq(dev->irq, dev);
  647. error6:
  648. if (dev->dummy_dma_page)
  649. pci_free_consistent(pdev, PAGE_SIZE, dev->dummy_dma_page,
  650. dev->dummy_dma_page_physical_address);
  651. kthread_stop(dev->io_thread);
  652. error5:
  653. iounmap(dev->mmio);
  654. error4:
  655. pci_release_regions(pdev);
  656. error3:
  657. pci_disable_device(pdev);
  658. error2:
  659. memstick_free_host(host);
  660. error1:
  661. return error;
  662. }
  663. static void r592_remove(struct pci_dev *pdev)
  664. {
  665. int error = 0;
  666. struct r592_device *dev = pci_get_drvdata(pdev);
  667. /* Stop the processing thread.
  668. That ensures that we won't take any more requests */
  669. kthread_stop(dev->io_thread);
  670. r592_enable_device(dev, false);
  671. while (!error && dev->req) {
  672. dev->req->error = -ETIME;
  673. error = memstick_next_req(dev->host, &dev->req);
  674. }
  675. memstick_remove_host(dev->host);
  676. free_irq(dev->irq, dev);
  677. iounmap(dev->mmio);
  678. pci_release_regions(pdev);
  679. pci_disable_device(pdev);
  680. memstick_free_host(dev->host);
  681. if (dev->dummy_dma_page)
  682. pci_free_consistent(pdev, PAGE_SIZE, dev->dummy_dma_page,
  683. dev->dummy_dma_page_physical_address);
  684. }
  685. #ifdef CONFIG_PM
  686. static int r592_suspend(struct device *core_dev)
  687. {
  688. struct pci_dev *pdev = to_pci_dev(core_dev);
  689. struct r592_device *dev = pci_get_drvdata(pdev);
  690. r592_clear_interrupts(dev);
  691. memstick_suspend_host(dev->host);
  692. del_timer_sync(&dev->detect_timer);
  693. return 0;
  694. }
  695. static int r592_resume(struct device *core_dev)
  696. {
  697. struct pci_dev *pdev = to_pci_dev(core_dev);
  698. struct r592_device *dev = pci_get_drvdata(pdev);
  699. r592_clear_interrupts(dev);
  700. r592_enable_device(dev, false);
  701. memstick_resume_host(dev->host);
  702. r592_update_card_detect(dev);
  703. return 0;
  704. }
  705. SIMPLE_DEV_PM_OPS(r592_pm_ops, r592_suspend, r592_resume);
  706. #endif
  707. MODULE_DEVICE_TABLE(pci, r592_pci_id_tbl);
  708. static struct pci_driver r852_pci_driver = {
  709. .name = DRV_NAME,
  710. .id_table = r592_pci_id_tbl,
  711. .probe = r592_probe,
  712. .remove = r592_remove,
  713. #ifdef CONFIG_PM
  714. .driver.pm = &r592_pm_ops,
  715. #endif
  716. };
  717. static __init int r592_module_init(void)
  718. {
  719. return pci_register_driver(&r852_pci_driver);
  720. }
  721. static void __exit r592_module_exit(void)
  722. {
  723. pci_unregister_driver(&r852_pci_driver);
  724. }
  725. module_init(r592_module_init);
  726. module_exit(r592_module_exit);
  727. module_param_named(enable_dma, r592_enable_dma, bool, S_IRUGO);
  728. MODULE_PARM_DESC(enable_dma, "Enable usage of the DMA (default)");
  729. module_param(debug, int, S_IRUGO | S_IWUSR);
  730. MODULE_PARM_DESC(debug, "Debug level (0-3)");
  731. MODULE_LICENSE("GPL");
  732. MODULE_AUTHOR("Maxim Levitsky <maximlevitsky@gmail.com>");
  733. MODULE_DESCRIPTION("Ricoh R5C592 Memstick/Memstick PRO card reader driver");