cpu.c 10 KB

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  1. /*
  2. * Copyright (C) 2005-2006 Atmel Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/init.h>
  9. #include <linux/device.h>
  10. #include <linux/seq_file.h>
  11. #include <linux/cpu.h>
  12. #include <linux/module.h>
  13. #include <linux/percpu.h>
  14. #include <linux/param.h>
  15. #include <linux/errno.h>
  16. #include <linux/clk.h>
  17. #include <asm/setup.h>
  18. #include <asm/sysreg.h>
  19. static DEFINE_PER_CPU(struct cpu, cpu_devices);
  20. #ifdef CONFIG_PERFORMANCE_COUNTERS
  21. /*
  22. * XXX: If/when a SMP-capable implementation of AVR32 will ever be
  23. * made, we must make sure that the code executes on the correct CPU.
  24. */
  25. static ssize_t show_pc0event(struct device *dev,
  26. struct device_attribute *attr, char *buf)
  27. {
  28. unsigned long pccr;
  29. pccr = sysreg_read(PCCR);
  30. return sprintf(buf, "0x%lx\n", (pccr >> 12) & 0x3f);
  31. }
  32. static ssize_t store_pc0event(struct device *dev,
  33. struct device_attribute *attr, const char *buf,
  34. size_t count)
  35. {
  36. unsigned long val;
  37. char *endp;
  38. val = simple_strtoul(buf, &endp, 0);
  39. if (endp == buf || val > 0x3f)
  40. return -EINVAL;
  41. val = (val << 12) | (sysreg_read(PCCR) & 0xfffc0fff);
  42. sysreg_write(PCCR, val);
  43. return count;
  44. }
  45. static ssize_t show_pc0count(struct device *dev,
  46. struct device_attribute *attr, char *buf)
  47. {
  48. unsigned long pcnt0;
  49. pcnt0 = sysreg_read(PCNT0);
  50. return sprintf(buf, "%lu\n", pcnt0);
  51. }
  52. static ssize_t store_pc0count(struct device *dev,
  53. struct device_attribute *attr,
  54. const char *buf, size_t count)
  55. {
  56. unsigned long val;
  57. char *endp;
  58. val = simple_strtoul(buf, &endp, 0);
  59. if (endp == buf)
  60. return -EINVAL;
  61. sysreg_write(PCNT0, val);
  62. return count;
  63. }
  64. static ssize_t show_pc1event(struct device *dev,
  65. struct device_attribute *attr, char *buf)
  66. {
  67. unsigned long pccr;
  68. pccr = sysreg_read(PCCR);
  69. return sprintf(buf, "0x%lx\n", (pccr >> 18) & 0x3f);
  70. }
  71. static ssize_t store_pc1event(struct device *dev,
  72. struct device_attribute *attr, const char *buf,
  73. size_t count)
  74. {
  75. unsigned long val;
  76. char *endp;
  77. val = simple_strtoul(buf, &endp, 0);
  78. if (endp == buf || val > 0x3f)
  79. return -EINVAL;
  80. val = (val << 18) | (sysreg_read(PCCR) & 0xff03ffff);
  81. sysreg_write(PCCR, val);
  82. return count;
  83. }
  84. static ssize_t show_pc1count(struct device *dev,
  85. struct device_attribute *attr, char *buf)
  86. {
  87. unsigned long pcnt1;
  88. pcnt1 = sysreg_read(PCNT1);
  89. return sprintf(buf, "%lu\n", pcnt1);
  90. }
  91. static ssize_t store_pc1count(struct device *dev,
  92. struct device_attribute *attr, const char *buf,
  93. size_t count)
  94. {
  95. unsigned long val;
  96. char *endp;
  97. val = simple_strtoul(buf, &endp, 0);
  98. if (endp == buf)
  99. return -EINVAL;
  100. sysreg_write(PCNT1, val);
  101. return count;
  102. }
  103. static ssize_t show_pccycles(struct device *dev,
  104. struct device_attribute *attr, char *buf)
  105. {
  106. unsigned long pccnt;
  107. pccnt = sysreg_read(PCCNT);
  108. return sprintf(buf, "%lu\n", pccnt);
  109. }
  110. static ssize_t store_pccycles(struct device *dev,
  111. struct device_attribute *attr, const char *buf,
  112. size_t count)
  113. {
  114. unsigned long val;
  115. char *endp;
  116. val = simple_strtoul(buf, &endp, 0);
  117. if (endp == buf)
  118. return -EINVAL;
  119. sysreg_write(PCCNT, val);
  120. return count;
  121. }
  122. static ssize_t show_pcenable(struct device *dev,
  123. struct device_attribute *attr, char *buf)
  124. {
  125. unsigned long pccr;
  126. pccr = sysreg_read(PCCR);
  127. return sprintf(buf, "%c\n", (pccr & 1)?'1':'0');
  128. }
  129. static ssize_t store_pcenable(struct device *dev,
  130. struct device_attribute *attr, const char *buf,
  131. size_t count)
  132. {
  133. unsigned long pccr, val;
  134. char *endp;
  135. val = simple_strtoul(buf, &endp, 0);
  136. if (endp == buf)
  137. return -EINVAL;
  138. if (val)
  139. val = 1;
  140. pccr = sysreg_read(PCCR);
  141. pccr = (pccr & ~1UL) | val;
  142. sysreg_write(PCCR, pccr);
  143. return count;
  144. }
  145. static DEVICE_ATTR(pc0event, 0600, show_pc0event, store_pc0event);
  146. static DEVICE_ATTR(pc0count, 0600, show_pc0count, store_pc0count);
  147. static DEVICE_ATTR(pc1event, 0600, show_pc1event, store_pc1event);
  148. static DEVICE_ATTR(pc1count, 0600, show_pc1count, store_pc1count);
  149. static DEVICE_ATTR(pccycles, 0600, show_pccycles, store_pccycles);
  150. static DEVICE_ATTR(pcenable, 0600, show_pcenable, store_pcenable);
  151. #endif /* CONFIG_PERFORMANCE_COUNTERS */
  152. static int __init topology_init(void)
  153. {
  154. int cpu;
  155. for_each_possible_cpu(cpu) {
  156. struct cpu *c = &per_cpu(cpu_devices, cpu);
  157. register_cpu(c, cpu);
  158. #ifdef CONFIG_PERFORMANCE_COUNTERS
  159. device_create_file(&c->dev, &dev_attr_pc0event);
  160. device_create_file(&c->dev, &dev_attr_pc0count);
  161. device_create_file(&c->dev, &dev_attr_pc1event);
  162. device_create_file(&c->dev, &dev_attr_pc1count);
  163. device_create_file(&c->dev, &dev_attr_pccycles);
  164. device_create_file(&c->dev, &dev_attr_pcenable);
  165. #endif
  166. }
  167. return 0;
  168. }
  169. subsys_initcall(topology_init);
  170. struct chip_id_map {
  171. u16 mid;
  172. u16 pn;
  173. const char *name;
  174. };
  175. static const struct chip_id_map chip_names[] = {
  176. { .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
  177. };
  178. #define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
  179. static const char *cpu_names[] = {
  180. "Morgan",
  181. "AP7",
  182. };
  183. #define NR_CPU_NAMES ARRAY_SIZE(cpu_names)
  184. static const char *arch_names[] = {
  185. "AVR32A",
  186. "AVR32B",
  187. };
  188. #define NR_ARCH_NAMES ARRAY_SIZE(arch_names)
  189. static const char *mmu_types[] = {
  190. "No MMU",
  191. "ITLB and DTLB",
  192. "Shared TLB",
  193. "MPU"
  194. };
  195. static const char *cpu_feature_flags[] = {
  196. "rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu",
  197. };
  198. static const char *get_chip_name(struct avr32_cpuinfo *cpu)
  199. {
  200. unsigned int i;
  201. unsigned int mid = avr32_get_manufacturer_id(cpu);
  202. unsigned int pn = avr32_get_product_number(cpu);
  203. for (i = 0; i < NR_CHIP_NAMES; i++) {
  204. if (chip_names[i].mid == mid && chip_names[i].pn == pn)
  205. return chip_names[i].name;
  206. }
  207. return "(unknown)";
  208. }
  209. void __init setup_processor(void)
  210. {
  211. unsigned long config0, config1;
  212. unsigned long features;
  213. unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
  214. unsigned device_id;
  215. unsigned tmp;
  216. unsigned i;
  217. config0 = sysreg_read(CONFIG0);
  218. config1 = sysreg_read(CONFIG1);
  219. cpu_id = SYSREG_BFEXT(PROCESSORID, config0);
  220. cpu_rev = SYSREG_BFEXT(PROCESSORREVISION, config0);
  221. arch_id = SYSREG_BFEXT(AT, config0);
  222. arch_rev = SYSREG_BFEXT(AR, config0);
  223. mmu_type = SYSREG_BFEXT(MMUT, config0);
  224. device_id = ocd_read(DID);
  225. boot_cpu_data.arch_type = arch_id;
  226. boot_cpu_data.cpu_type = cpu_id;
  227. boot_cpu_data.arch_revision = arch_rev;
  228. boot_cpu_data.cpu_revision = cpu_rev;
  229. boot_cpu_data.tlb_config = mmu_type;
  230. boot_cpu_data.device_id = device_id;
  231. tmp = SYSREG_BFEXT(ILSZ, config1);
  232. if (tmp) {
  233. boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1);
  234. boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1);
  235. boot_cpu_data.icache.linesz = 1 << (tmp + 1);
  236. }
  237. tmp = SYSREG_BFEXT(DLSZ, config1);
  238. if (tmp) {
  239. boot_cpu_data.dcache.ways = 1 << SYSREG_BFEXT(DASS, config1);
  240. boot_cpu_data.dcache.sets = 1 << SYSREG_BFEXT(DSET, config1);
  241. boot_cpu_data.dcache.linesz = 1 << (tmp + 1);
  242. }
  243. if ((cpu_id >= NR_CPU_NAMES) || (arch_id >= NR_ARCH_NAMES)) {
  244. printk ("Unknown CPU configuration (ID %02x, arch %02x), "
  245. "continuing anyway...\n",
  246. cpu_id, arch_id);
  247. return;
  248. }
  249. printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
  250. avr32_get_chip_revision(&boot_cpu_data) + 'A');
  251. printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n",
  252. cpu_names[cpu_id], cpu_id, cpu_rev,
  253. arch_names[arch_id], arch_rev);
  254. printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);
  255. printk ("CPU: features:");
  256. features = 0;
  257. if (config0 & SYSREG_BIT(CONFIG0_R))
  258. features |= AVR32_FEATURE_RMW;
  259. if (config0 & SYSREG_BIT(CONFIG0_D))
  260. features |= AVR32_FEATURE_DSP;
  261. if (config0 & SYSREG_BIT(CONFIG0_S))
  262. features |= AVR32_FEATURE_SIMD;
  263. if (config0 & SYSREG_BIT(CONFIG0_O))
  264. features |= AVR32_FEATURE_OCD;
  265. if (config0 & SYSREG_BIT(CONFIG0_P))
  266. features |= AVR32_FEATURE_PCTR;
  267. if (config0 & SYSREG_BIT(CONFIG0_J))
  268. features |= AVR32_FEATURE_JAVA;
  269. if (config0 & SYSREG_BIT(CONFIG0_F))
  270. features |= AVR32_FEATURE_FPU;
  271. for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
  272. if (features & (1 << i))
  273. printk(" %s", cpu_feature_flags[i]);
  274. printk("\n");
  275. boot_cpu_data.features = features;
  276. }
  277. #ifdef CONFIG_PROC_FS
  278. static int c_show(struct seq_file *m, void *v)
  279. {
  280. unsigned int icache_size, dcache_size;
  281. unsigned int cpu = smp_processor_id();
  282. unsigned int freq;
  283. unsigned int i;
  284. icache_size = boot_cpu_data.icache.ways *
  285. boot_cpu_data.icache.sets *
  286. boot_cpu_data.icache.linesz;
  287. dcache_size = boot_cpu_data.dcache.ways *
  288. boot_cpu_data.dcache.sets *
  289. boot_cpu_data.dcache.linesz;
  290. seq_printf(m, "processor\t: %d\n", cpu);
  291. seq_printf(m, "chip type\t: %s revision %c\n",
  292. get_chip_name(&boot_cpu_data),
  293. avr32_get_chip_revision(&boot_cpu_data) + 'A');
  294. if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
  295. seq_printf(m, "cpu arch\t: %s revision %d\n",
  296. arch_names[boot_cpu_data.arch_type],
  297. boot_cpu_data.arch_revision);
  298. if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
  299. seq_printf(m, "cpu core\t: %s revision %d\n",
  300. cpu_names[boot_cpu_data.cpu_type],
  301. boot_cpu_data.cpu_revision);
  302. freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
  303. seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000);
  304. seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
  305. icache_size >> 10,
  306. boot_cpu_data.icache.ways,
  307. boot_cpu_data.icache.sets,
  308. boot_cpu_data.icache.linesz);
  309. seq_printf(m, "d-cache\t\t: %dK (%u ways x %u sets x %u)\n",
  310. dcache_size >> 10,
  311. boot_cpu_data.dcache.ways,
  312. boot_cpu_data.dcache.sets,
  313. boot_cpu_data.dcache.linesz);
  314. seq_printf(m, "features\t:");
  315. for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
  316. if (boot_cpu_data.features & (1 << i))
  317. seq_printf(m, " %s", cpu_feature_flags[i]);
  318. seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
  319. boot_cpu_data.loops_per_jiffy / (500000/HZ),
  320. (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);
  321. return 0;
  322. }
  323. static void *c_start(struct seq_file *m, loff_t *pos)
  324. {
  325. return *pos < 1 ? (void *)1 : NULL;
  326. }
  327. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  328. {
  329. ++*pos;
  330. return NULL;
  331. }
  332. static void c_stop(struct seq_file *m, void *v)
  333. {
  334. }
  335. const struct seq_operations cpuinfo_op = {
  336. .start = c_start,
  337. .next = c_next,
  338. .stop = c_stop,
  339. .show = c_show
  340. };
  341. #endif /* CONFIG_PROC_FS */