mtv319_tdmb.c 33 KB

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  1. /*
  2. *
  3. * File name: mtv319_tdmb.c
  4. *
  5. * Description : MTV319 T-DMB services source file.
  6. *
  7. * Copyright (C) (2013, RAONTECH)
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation version 2.
  12. *
  13. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14. * kind, whether express or implied; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. */
  19. #include "mtv319_rf.h"
  20. #include "mtv319_internal.h"
  21. #define TDMB_MAX_NUM_ANTENNA_LEVEL 7
  22. #define MAX_NUM_TDMB_SUBCH 64
  23. #define TDMB_MAX_CER_VALUE 2000
  24. /* #define DEBUG_LOG_FOR_RSSI_FITTING */
  25. #define DIV32(x) ((x) >> 5) /* Divide by 32 */
  26. #define MOD32(x) ((x) & 31)
  27. static enum E_TDMB_STATE g_eTdmbState;
  28. /* NOTE: Do not modify the order! */
  29. enum E_TDMB_HW_SUBCH_IDX_TYPE {
  30. TDMB_HW_CH_IDX_TDMB = 0,
  31. TDMB_HW_CH_IDX_DAB_0 = 1,
  32. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  33. TDMB_HW_CH_IDX_DAB_1,
  34. #endif
  35. TDMB_HW_CH_IDX_DABPLUS,
  36. MAX_NUM_TDMB_HW_CH_IDX
  37. };
  38. static UINT g_nUsedHwSubChIdxBits;
  39. /* Registered sub channel information. */
  40. struct RTV_TDMB_REG_SUBCH_INFO {
  41. UINT nSubChID;
  42. enum E_TDMB_HW_SUBCH_IDX_TYPE eHwSubChIdx;
  43. enum E_RTV_SERVICE_TYPE eServiceType;
  44. };
  45. static struct RTV_TDMB_REG_SUBCH_INFO
  46. g_atRegSubchInfo[RTV_MAX_NUM_USE_SUBCHANNEL];
  47. static UINT g_nRegSubChArrayIdxBits;
  48. static UINT g_nTdmbPrevAntennaLevel;
  49. static UINT g_nOpenedSubChNum;
  50. /* Used sub channel ID bits. [0]: 0 ~ 31, [1]: 32 ~ 63 */
  51. static U32 g_aRegSubChIdBits[2];
  52. static BOOL g_fTdmbFastScanEnabled;
  53. #if defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  54. enum E_RTV_FIC_OPENED_PATH_TYPE g_nRtvFicOpenedStatePath;
  55. #endif
  56. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  57. UINT g_nRtvInterruptLevelSize;
  58. #endif
  59. BOOL g_fRtvFicOpened;
  60. static void Disable_DABP_SUBCH(void)
  61. {
  62. g_nUsedHwSubChIdxBits &= ~(1<<TDMB_HW_CH_IDX_DABPLUS);
  63. RTV_REG_MAP_SEL(FEC_PAGE);
  64. RTV_REG_SET(0x83, 00);
  65. #ifdef RTV_CIF_MODE_ENABLED /* can be with FIC or multi subch */
  66. RTV_REG_SET(0xB5, 0x84); /* TSIF_DABP */
  67. #else
  68. RTV_REG_SET(0xB7, 0x00); /* TSIF_ONE */
  69. #endif
  70. }
  71. static void Enable_DABP_SUBCH(UINT nSubChID)
  72. {
  73. RTV_REG_MAP_SEL(FEC_PAGE);
  74. #ifdef RTV_CIF_MODE_ENABLED /* can be with FIC or multi subch */
  75. RTV_REG_SET(0xB5, 0x04|N_DATA_LEN_BITVAL); /* TSIF_DABP */
  76. #else
  77. RTV_REG_SET(0xB7, 0x00|ONE_DATA_LEN_BITVAL); /* TSIF_ONE */
  78. #endif
  79. RTV_REG_SET(0x83, (0xC0 | nSubChID));
  80. g_nUsedHwSubChIdxBits |= (1<<TDMB_HW_CH_IDX_DABPLUS);
  81. }
  82. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  83. static void Disable_DAB_SUBCH1(void)
  84. {
  85. RTV_REG_MAP_SEL(FEC_PAGE);
  86. g_nUsedHwSubChIdxBits &= ~(1<<TDMB_HW_CH_IDX_DAB_1);
  87. /* Disable data path if the all DAB was closed. */
  88. if (!(g_nUsedHwSubChIdxBits
  89. & (((1<<TDMB_HW_CH_IDX_DAB_0))|((1<<TDMB_HW_CH_IDX_DAB_1))))) {
  90. #ifdef RTV_CIF_MODE_ENABLED
  91. RTV_REG_SET(0xB3, 0x86); /* TSIF_MSC */
  92. #else
  93. RTV_REG_SET(0xB7, 0x10); /* TSIF_ONE */
  94. #endif
  95. }
  96. RTV_REG_SET(0xB9, 00);
  97. }
  98. static void Enable_DAB_SUBCH1(UINT nSubChID)
  99. {
  100. RTV_REG_MAP_SEL(FEC_PAGE);
  101. /* Enable data path if the all DAB was closed. */
  102. if (!(g_nUsedHwSubChIdxBits
  103. & (((1<<TDMB_HW_CH_IDX_DAB_0))|((1<<TDMB_HW_CH_IDX_DAB_1))))) {
  104. #ifdef RTV_CIF_MODE_ENABLED /* can be with FIC or multi subch */
  105. RTV_REG_SET(0xB3, 0x04|N_DATA_LEN_BITVAL); /* TSIF_MSC */
  106. #else
  107. RTV_REG_MAP_SEL(FEC_PAGE);
  108. RTV_REG_SET(0xB7, 0x90|ONE_DATA_LEN_BITVAL); /* TSIF_ONE */
  109. #endif
  110. }
  111. RTV_REG_SET(0xB9, 0x80|nSubChID);
  112. g_nUsedHwSubChIdxBits |= (1<<TDMB_HW_CH_IDX_DAB_1);
  113. }
  114. #endif /* #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2) */
  115. static void Disable_DAB_SUBCH0(void)
  116. {
  117. RTV_REG_MAP_SEL(FEC_PAGE);
  118. g_nUsedHwSubChIdxBits &= ~(1<<TDMB_HW_CH_IDX_DAB_0);
  119. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  120. /* Disable data path if the all DAB was closed. */
  121. if (!(g_nUsedHwSubChIdxBits
  122. & (((1<<TDMB_HW_CH_IDX_DAB_0))|((1<<TDMB_HW_CH_IDX_DAB_1))))) {
  123. #endif
  124. #ifdef RTV_CIF_MODE_ENABLED /* can be with FIC or multi subch */
  125. RTV_REG_SET(0xB3, 0x86); /* TSIF_MSC */
  126. #else
  127. RTV_REG_SET(0xB7, 0x10); /* TSIF_ONE */
  128. #endif
  129. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  130. }
  131. #endif
  132. RTV_REG_SET(0xB8, 0x00);
  133. }
  134. static void Enable_DAB_SUBCH0(UINT nSubChID)
  135. {
  136. RTV_REG_MAP_SEL(FEC_PAGE);
  137. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  138. /* Enable data path if the all DAB was closed. */
  139. if (!(g_nUsedHwSubChIdxBits
  140. & (((1<<TDMB_HW_CH_IDX_DAB_0))|((1<<TDMB_HW_CH_IDX_DAB_1))))) {
  141. #endif
  142. #ifdef RTV_CIF_MODE_ENABLED /* can be with FIC or multi subch */
  143. RTV_REG_SET(0xB3, 0x04|N_DATA_LEN_BITVAL); /* TSIF_MSC */
  144. #else
  145. RTV_REG_SET(0xB7, 0x90|ONE_DATA_LEN_BITVAL); /* TSIF_ONE */
  146. #endif
  147. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  148. }
  149. #endif
  150. RTV_REG_SET(0xB8, 0x80|nSubChID);
  151. g_nUsedHwSubChIdxBits |= (1<<TDMB_HW_CH_IDX_DAB_0);
  152. }
  153. static void Disable_TDMB_SUBCH(void)
  154. {
  155. g_nUsedHwSubChIdxBits &= ~(1<<TDMB_HW_CH_IDX_TDMB);
  156. RTV_REG_MAP_SEL(FEC_PAGE);
  157. RTV_REG_SET(0x81, 0x00);
  158. RTV_REG_SET(0xB4, 0x80);
  159. }
  160. static void Enable_TDMB_SUBCH(UINT nSubChID)
  161. {
  162. RTV_REG_MAP_SEL(FEC_PAGE);
  163. RTV_REG_SET(0x81, (0xC0 | nSubChID));
  164. RTV_REG_SET(0xB4, 0x10|HEADER_LEN_BITVAL|N_DATA_LEN_BITVAL);
  165. g_nUsedHwSubChIdxBits |= (1<<TDMB_HW_CH_IDX_TDMB);
  166. }
  167. static void (*g_pfnDisableSUBCH[MAX_NUM_TDMB_HW_CH_IDX])(void) = {
  168. Disable_TDMB_SUBCH,
  169. Disable_DAB_SUBCH0,
  170. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  171. Disable_DAB_SUBCH1,
  172. #endif
  173. Disable_DABP_SUBCH
  174. };
  175. static void (*g_pfnEnableSUBCH[MAX_NUM_TDMB_HW_CH_IDX])(UINT nSubChID) = {
  176. Enable_TDMB_SUBCH,
  177. Enable_DAB_SUBCH0,
  178. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  179. Enable_DAB_SUBCH1,
  180. #endif
  181. Enable_DABP_SUBCH
  182. };
  183. static void tdmb_DisableFastScanMode(void)
  184. {
  185. if (!g_fTdmbFastScanEnabled)
  186. return;
  187. RTV_REG_MAP_SEL(FEC_PAGE);
  188. RTV_REG_SET(0x2D, 0x80);
  189. RTV_REG_SET(0x2E, 0x5F);
  190. RTV_REG_MAP_SEL(OFDM_PAGE);
  191. RTV_REG_SET(0x14, 0x46);
  192. RTV_REG_SET(0x50, 0x02);
  193. RTV_REG_SET(0x40, 0x42);
  194. RTV_REG_SET(0x4C, 0x41);
  195. g_fTdmbFastScanEnabled = FALSE;
  196. }
  197. static void tdmb_EnableFastScanMode(void)
  198. {
  199. if (g_fTdmbFastScanEnabled)
  200. return;
  201. RTV_REG_MAP_SEL(OFDM_PAGE);
  202. RTV_REG_SET(0x14, 0x26); /* Force Stable Test */
  203. RTV_REG_SET(0x19, 0x34);
  204. RTV_REG_SET(0x40, 0x40);
  205. /* TLock Mode <3:0> + 1 ; 40 = 1EA COUNT, 42 = 3EA COUNT */
  206. RTV_REG_SET(0x4C, 0x40);
  207. RTV_REG_SET(0x50, 0x06); /* Scan On */
  208. RTV_REG_MAP_SEL(FEC_PAGE);
  209. RTV_REG_SET(0x2D, 0x0C);
  210. RTV_REG_SET(0x2E, 0x07);
  211. g_fTdmbFastScanEnabled = TRUE;
  212. }
  213. void rtvTDMB_StandbyMode(int on)
  214. {
  215. }
  216. static INLINE UINT tdmb_GetLockStatus(void)
  217. {
  218. U8 OFDM_B8, FECL;
  219. UINT lock_st = 0;
  220. RTV_REG_MAP_SEL(OFDM_PAGE);
  221. RTV_REG_MASK_SET(0x12, 0x80, 0x80);
  222. RTV_REG_MASK_SET(0x12, 0x80, 0x00);
  223. OFDM_B8 = RTV_REG_GET(0xB8);
  224. if (OFDM_B8 & 0x01)
  225. lock_st = RTV_TDMB_OFDM_LOCK_MASK;
  226. if (OFDM_B8 & 0x08)
  227. lock_st |= RTV_TDMB_AGC_LOCK_MASK;
  228. RTV_REG_MAP_SEL(FEC_PAGE);
  229. RTV_REG_MASK_SET(0x11, 0x04, 0x04);
  230. RTV_REG_MASK_SET(0x11, 0x04, 0x00);
  231. FECL = RTV_REG_GET(0x10); /* FEC Lock (Viterbi Lock) */
  232. if (FECL & 0x01)
  233. lock_st |= RTV_TDMB_FEC_LOCK_MASK;
  234. return lock_st;
  235. }
  236. UINT rtvTDMB_GetLockStatus(void)
  237. {
  238. UINT lock_st;
  239. RTV_GUARD_LOCK;
  240. lock_st = tdmb_GetLockStatus();
  241. RTV_GUARD_FREE;
  242. return lock_st;
  243. }
  244. UINT rtvTDMB_GetAntennaLevel(U32 dwCER)
  245. {
  246. UINT nCurLevel = 0;
  247. UINT nPrevLevel = g_nTdmbPrevAntennaLevel;
  248. const UINT aAntLvlTbl[TDMB_MAX_NUM_ANTENNA_LEVEL] = {
  249. /* 0 1 2 3 4 5 6 */
  250. 900, 800, 700, 600, 500, 400, 0};
  251. if (dwCER == TDMB_MAX_CER_VALUE)
  252. return 0;
  253. do {
  254. if (dwCER >= aAntLvlTbl[nCurLevel]) /* Use equal for CER 0 */
  255. break;
  256. } while (++nCurLevel != TDMB_MAX_NUM_ANTENNA_LEVEL);
  257. if (nCurLevel != nPrevLevel) {
  258. if (nCurLevel < nPrevLevel)
  259. nPrevLevel--;
  260. else
  261. nPrevLevel++;
  262. g_nTdmbPrevAntennaLevel = nPrevLevel;
  263. }
  264. return nPrevLevel;
  265. }
  266. /* FIC CER */
  267. U32 rtvTDMB_GetFicCER(void)
  268. {
  269. U8 fec_sync, prd0, prd1, cnt0, cnt1;
  270. U32 count = 0, period, cer;
  271. RTV_GUARD_LOCK;
  272. RTV_REG_MAP_SEL(FEC_PAGE);
  273. RTV_REG_MASK_SET(0x11, 0x04, 0x04);
  274. RTV_REG_MASK_SET(0x11, 0x04, 0x00);
  275. fec_sync = RTV_REG_GET(0x10);
  276. if (fec_sync & 0x01) {
  277. prd0 = RTV_REG_GET(0x3A);
  278. prd1 = RTV_REG_GET(0x3B);
  279. period = (prd0<<8) | prd1;
  280. cnt0 = RTV_REG_GET(0x3C);
  281. cnt1 = RTV_REG_GET(0x3D);
  282. count = (cnt0<<8) | cnt1;
  283. } else
  284. period = 0;
  285. RTV_GUARD_FREE;
  286. if (period) {
  287. #if 0
  288. RTV_DBGMSG2("[rtvTDMB_GetFicCER] count(%u), period(%u)\n",
  289. count, period);
  290. #endif
  291. cer = (count * 10000) / period;
  292. if (cer > 1000)
  293. cer = TDMB_MAX_CER_VALUE; /* No service */
  294. } else
  295. cer = TDMB_MAX_CER_VALUE; /* No service */
  296. return cer;
  297. }
  298. /* MSC CER */
  299. U32 rtvTDMB_GetCER(void)
  300. {
  301. U8 fec_sync, prd0, prd1, prd2, prd3, cnt0, cnt1, cnt2, cnt3;
  302. U32 count = 0, period, cer;
  303. RTV_GUARD_LOCK;
  304. RTV_REG_MAP_SEL(FEC_PAGE);
  305. RTV_REG_MASK_SET(0x11, 0x04, 0x04);
  306. RTV_REG_MASK_SET(0x11, 0x04, 0x00);
  307. fec_sync = RTV_REG_GET(0x10);
  308. if (fec_sync & 0x01) {
  309. prd0 = RTV_REG_GET(0x3E);
  310. prd1 = RTV_REG_GET(0x3F);
  311. prd2 = RTV_REG_GET(0x40);
  312. prd3 = RTV_REG_GET(0x41);
  313. period = (prd0<<24) | (prd1<<16) | (prd2<<8) | prd3;
  314. cnt0 = RTV_REG_GET(0x42);
  315. cnt1 = RTV_REG_GET(0x43);
  316. cnt2 = RTV_REG_GET(0x44);
  317. cnt3 = RTV_REG_GET(0x45);
  318. count = (cnt0<<24) | (cnt1<<16) | (cnt2<<8) | cnt3;
  319. } else
  320. period = 0;
  321. RTV_GUARD_FREE;
  322. if (period) {
  323. #if 0
  324. RTV_DBGMSG2("[rtvTDMB_GetCER] count(%u), period(%u)\n",
  325. count, period);
  326. #endif
  327. cer = (count * 10000) / period;
  328. if (cer > 1000)
  329. cer = TDMB_MAX_CER_VALUE; /* No service */
  330. } else
  331. cer = TDMB_MAX_CER_VALUE; /* No service */
  332. return cer;
  333. }
  334. #define RSSI_RFAGC_VAL(rfagc, coeffi)\
  335. ((rfagc) * (S32)((coeffi)*RTV_TDMB_RSSI_DIVIDER))
  336. #define RSSI_GVBB_VAL(gvbb, coeffi)\
  337. ((gvbb) * (S32)((coeffi)*RTV_TDMB_RSSI_DIVIDER))
  338. S32 rtvTDMB_GetRSSI(void)
  339. {
  340. U8 RD00, GVBB, LNAGAIN, RFAGC;
  341. #ifdef DEBUG_LOG_FOR_RSSI_FITTING
  342. U8 CH_FLAG;
  343. #endif
  344. S32 nRssi = 0;
  345. RTV_GUARD_LOCK;
  346. RTV_REG_MAP_SEL(RF_PAGE);
  347. RD00 = RTV_REG_GET(0x00);
  348. GVBB = RTV_REG_GET(0x01);
  349. RTV_GUARD_FREE;
  350. #ifdef DEBUG_LOG_FOR_RSSI_FITTING
  351. CH_FLAG = ((RD00 & 0xC0) >> 6);
  352. #endif
  353. LNAGAIN = ((RD00 & 0x18) >> 3);
  354. RFAGC = (RD00 & 0x07);
  355. switch (LNAGAIN) {
  356. case 0:
  357. nRssi = -(RSSI_RFAGC_VAL(RFAGC, 2.8)
  358. + RSSI_GVBB_VAL(GVBB, 0.44) + 0)
  359. + 5 * RTV_TDMB_RSSI_DIVIDER;
  360. break;
  361. case 1:
  362. nRssi = -(RSSI_RFAGC_VAL(RFAGC, 3)
  363. + RSSI_GVBB_VAL(GVBB, 0.3) + (19 * RTV_TDMB_RSSI_DIVIDER))
  364. + 0 * RTV_TDMB_RSSI_DIVIDER;
  365. break;
  366. case 2:
  367. nRssi = -(RSSI_RFAGC_VAL(RFAGC, 3)
  368. + RSSI_GVBB_VAL(GVBB, 0.3) + (16 * 2 * RTV_TDMB_RSSI_DIVIDER))
  369. + 0 * RTV_TDMB_RSSI_DIVIDER;
  370. break;
  371. case 3:
  372. nRssi = -(RSSI_RFAGC_VAL(RFAGC, 2.6)
  373. + RSSI_GVBB_VAL(GVBB, 0.4) + (11 * 3 * RTV_TDMB_RSSI_DIVIDER))
  374. + 0 * RTV_TDMB_RSSI_DIVIDER;
  375. break;
  376. default:
  377. break;
  378. }
  379. #ifdef DEBUG_LOG_FOR_RSSI_FITTING
  380. RTV_DBGMSG3("\n[rtvTDMB_GetRSSI] Channel Flag = %d 0x00=0x%02x, 0x01=0x%02x\n",CH_FLAG, RD00, GVBB);
  381. RTV_DBGMSG3("LNAGAIN = %d, RFAGC = %d GVBB : %d\n", LNAGAIN, RFAGC,GVBB);
  382. #endif
  383. return nRssi;
  384. }
  385. /* SNR */
  386. U32 rtvTDMB_GetCNR(void)
  387. {
  388. U8 data1, data2, fec_sync;
  389. U32 data, snr = 0;
  390. RTV_GUARD_LOCK;
  391. RTV_REG_MAP_SEL(OFDM_PAGE);
  392. RTV_REG_MASK_SET(0x12, 0x80, 0x80);
  393. RTV_REG_MASK_SET(0x12, 0x80, 0x00);
  394. data1 = RTV_REG_GET(0xE0);
  395. data2 = RTV_REG_GET(0xE1);
  396. data = (((data2&0x3F)<<8) | data1) * 4;
  397. RTV_REG_MAP_SEL(FEC_PAGE);
  398. fec_sync = RTV_REG_GET(0x10);
  399. RTV_GUARD_FREE;
  400. if (fec_sync & 0x01) {
  401. if (data > 7800)
  402. snr = 0;
  403. else if ((data > 6600) && (data <= 7800))
  404. snr = (-4 * (S32)data/5200 * RTV_TDMB_CNR_DIVIDER)
  405. + (U32)(8.3*RTV_TDMB_CNR_DIVIDER);
  406. else if ((data > 4100) && (data <= 6600))
  407. snr = (-5 * (S32)data/4300 * RTV_TDMB_CNR_DIVIDER)
  408. + (U32)(14.0*RTV_TDMB_CNR_DIVIDER);
  409. else if ((data > 1400) && (data <= 4100))
  410. snr = (-5 * (S32)data/3500 * RTV_TDMB_CNR_DIVIDER)
  411. + (U32)(16.0*RTV_TDMB_CNR_DIVIDER);
  412. else if ((data > 600) && (data <= 1400))
  413. snr = (-10 * (S32)data/1200 * RTV_TDMB_CNR_DIVIDER)
  414. + (U32)(27.0*RTV_TDMB_CNR_DIVIDER);
  415. else if ((data > 200) && (data <= 600))
  416. snr = (-15 * (S32)data/400 * RTV_TDMB_CNR_DIVIDER)
  417. + (U32)(42.5*RTV_TDMB_CNR_DIVIDER);
  418. else if (data <= 200)
  419. snr = 35 * RTV_TDMB_CNR_DIVIDER;
  420. } else
  421. snr = 5 * RTV_TDMB_CNR_DIVIDER;
  422. return snr;
  423. }
  424. U32 rtvTDMB_GetPER(void)
  425. {
  426. U8 rdata0, rdata1, rs_sync;
  427. U32 per = 700;
  428. RTV_GUARD_LOCK;
  429. if (g_nUsedHwSubChIdxBits & (1<<TDMB_HW_CH_IDX_TDMB)) {
  430. RTV_REG_MAP_SEL(FEC_PAGE);
  431. rs_sync = (RTV_REG_GET(0xA2) >> 3) & 0x01;
  432. if (rs_sync) {
  433. rdata1 = RTV_REG_GET(0x5C);
  434. rdata0 = RTV_REG_GET(0x5D);
  435. per = (rdata1 << 8) | rdata0;
  436. }
  437. } else if (g_nUsedHwSubChIdxBits & (1<<TDMB_HW_CH_IDX_DABPLUS)) {
  438. RTV_REG_MAP_SEL(FEC_PAGE);
  439. rs_sync = (RTV_REG_GET(0x10) >> 1) & 0x01;
  440. if (rs_sync) {
  441. rdata1 = RTV_REG_GET(0x6F);
  442. rdata0 = RTV_REG_GET(0x70);
  443. per = (rdata1 << 8) | rdata0;
  444. }
  445. } else
  446. per = 0;
  447. RTV_GUARD_FREE;
  448. return per;
  449. }
  450. /* After Viterbi BER */
  451. U32 rtvTDMB_GetBER(void)
  452. {
  453. U8 rs_sync, prd0, prd1, cnt0, cnt1, cnt2;
  454. U32 count = 0, period, ber = RTV_TDMB_BER_DIVIDER;
  455. RTV_GUARD_LOCK;
  456. if (g_nUsedHwSubChIdxBits & (1<<TDMB_HW_CH_IDX_TDMB)) {
  457. RTV_REG_MAP_SEL(FEC_PAGE);
  458. rs_sync = (RTV_REG_GET(0xA2) >> 3) & 0x01;
  459. if (rs_sync) {
  460. prd0 = RTV_REG_GET(0x34);
  461. prd1 = RTV_REG_GET(0x35);
  462. period = (prd0<<8) | prd1;
  463. cnt0 = RTV_REG_GET(0x56);
  464. cnt1 = RTV_REG_GET(0x57);
  465. cnt2 = RTV_REG_GET(0x58);
  466. count = ((cnt0&0x7f)<<16) | (cnt1<<8) | cnt2;
  467. } else
  468. period = 0;
  469. } else if (g_nUsedHwSubChIdxBits & (1<<TDMB_HW_CH_IDX_DABPLUS)) {
  470. RTV_REG_MAP_SEL(FEC_PAGE);
  471. rs_sync = (RTV_REG_GET(0x10) >> 1) & 0x01;
  472. if (rs_sync) {
  473. prd0 = RTV_REG_GET(0x37);
  474. prd1 = RTV_REG_GET(0x38);
  475. period = (prd0<<8) | prd1;
  476. cnt0 = RTV_REG_GET(0x69);
  477. cnt1 = RTV_REG_GET(0x6A);
  478. cnt2 = RTV_REG_GET(0x6B);
  479. count = ((cnt0&0x7f)<<16) | (cnt1<<8) | cnt2;
  480. } else
  481. period = 0;
  482. } else {
  483. period = 0;
  484. ber = 0;
  485. }
  486. RTV_GUARD_FREE;
  487. if (period)
  488. ber = (count * (U32)RTV_TDMB_BER_DIVIDER) / (period*8*204);
  489. return ber;
  490. }
  491. UINT rtvTDMB_GetOpenedSubChannelCount(void)
  492. {
  493. return g_nOpenedSubChNum;
  494. }
  495. U32 rtvTDMB_GetPreviousFrequency(void)
  496. {
  497. return g_dwRtvPrevChFreqKHz;
  498. }
  499. static void tdmb_CloseSubChannel(UINT nRegSubChArrayIdx)
  500. {
  501. UINT nSubChID;
  502. enum E_TDMB_HW_SUBCH_IDX_TYPE eHwSubChIdx;
  503. nSubChID = g_atRegSubchInfo[nRegSubChArrayIdx].nSubChID;
  504. eHwSubChIdx = g_atRegSubchInfo[nRegSubChArrayIdx].eHwSubChIdx;
  505. /* Call the specified disabling of SUBCH function. */
  506. g_pfnDisableSUBCH[eHwSubChIdx]();
  507. g_nRegSubChArrayIdxBits &= ~(1<<nRegSubChArrayIdx);
  508. g_aRegSubChIdBits[DIV32(nSubChID)] &= ~(1 << MOD32(nSubChID));
  509. g_nOpenedSubChNum--;
  510. if (!g_nOpenedSubChNum && !g_fRtvFicOpened) {
  511. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  512. RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
  513. g_bRtvIntrMaskReg |= SPI_INTR_BITS; /* for polling */
  514. RTV_REG_SET(0x24, g_bRtvIntrMaskReg); /* Disable interrupts. */
  515. /* To clear interrupt and data. */
  516. RTV_REG_SET(0x2A, 1);
  517. RTV_REG_SET(0x2A, 0);
  518. #endif
  519. #ifdef TDMB_CIF_MODE_DRIVER
  520. rtvCIFDEC_Deinit(); /* Skip rtvCIFDEC_DeleteSubChannelID() */
  521. #endif
  522. /* Update the state of TDMB. */
  523. g_eTdmbState = TDMB_STATE_INIT;
  524. } else {
  525. #ifdef TDMB_CIF_MODE_DRIVER
  526. rtvCIFDEC_DeleteSubChannelID(nSubChID);
  527. #endif
  528. }
  529. }
  530. void rtvTDMB_CloseAllSubChannels(void)
  531. {
  532. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  533. UINT i = 0;
  534. UINT nRegSubChArrayIdxBits = g_nRegSubChArrayIdxBits;
  535. #endif
  536. if (g_nOpenedSubChNum == 0)
  537. return; /* not opened! already closed! */
  538. RTV_GUARD_LOCK;
  539. #if (RTV_MAX_NUM_USE_SUBCHANNEL == 1) /* Single Sub Channel */
  540. tdmb_CloseSubChannel(0);
  541. #elif (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  542. while (nRegSubChArrayIdxBits) {
  543. if (nRegSubChArrayIdxBits & 0x01)
  544. tdmb_CloseSubChannel(i);
  545. nRegSubChArrayIdxBits >>= 1;
  546. i++;
  547. }
  548. #endif
  549. RTV_GUARD_FREE;
  550. }
  551. INT rtvTDMB_CloseSubChannel(UINT nSubChID)
  552. {
  553. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  554. UINT i = 0;
  555. UINT nRegSubChArrayIdxBits = g_nRegSubChArrayIdxBits;
  556. #endif
  557. if (nSubChID > (MAX_NUM_TDMB_SUBCH-1))
  558. return RTV_INVAILD_SUBCHANNEL_ID;
  559. if (g_nOpenedSubChNum == 0)
  560. return RTV_SUCCESS; /* not opened! already closed! */
  561. RTV_GUARD_LOCK;
  562. #if (RTV_MAX_NUM_USE_SUBCHANNEL == 1) /* Single Sub Channel */
  563. tdmb_CloseSubChannel(0);
  564. #else
  565. while (nRegSubChArrayIdxBits) {
  566. if (nRegSubChArrayIdxBits & 0x01) {
  567. if (nSubChID == g_atRegSubchInfo[i].nSubChID)
  568. tdmb_CloseSubChannel(i);
  569. }
  570. nRegSubChArrayIdxBits >>= 1;
  571. i++;
  572. }
  573. #endif
  574. RTV_GUARD_FREE;
  575. return RTV_SUCCESS;
  576. }
  577. static void tdmb_OpenSubChannel(UINT nSubChID,
  578. enum E_RTV_SERVICE_TYPE eServiceType, UINT nThresholdSize,
  579. enum E_TDMB_HW_SUBCH_IDX_TYPE eHwSubChIdx)
  580. {
  581. UINT i;
  582. #if defined(TDMB_CIF_MODE_DRIVER) || defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  583. if (g_nOpenedSubChNum == 0) { /* The first open */
  584. #ifdef TDMB_CIF_MODE_DRIVER
  585. rtvCIFDEC_Init();
  586. rtvCIFDEC_AddSubChannelID(nSubChID, eServiceType);
  587. #endif
  588. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  589. rtv_SetupInterruptThreshold(nThresholdSize);
  590. RTV_REG_SET(0x2A, 1);
  591. RTV_REG_SET(0x2A, 0);
  592. /* Enable SPI interrupts */
  593. g_bRtvIntrMaskReg &= ~(SPI_INTR_BITS);
  594. RTV_REG_SET(0x24, g_bRtvIntrMaskReg);
  595. rtv_EnablePadIntrrupt();
  596. #endif
  597. } else {
  598. #ifdef TDMB_CIF_MODE_DRIVER
  599. rtvCIFDEC_AddSubChannelID(nSubChID, eServiceType);
  600. #endif
  601. }
  602. #endif
  603. /* Call the specified enabling of SUBCH function. */
  604. g_pfnEnableSUBCH[eHwSubChIdx](nSubChID);
  605. g_aRegSubChIdBits[DIV32(nSubChID)] |= (1 << MOD32(nSubChID));
  606. /* To use when close .*/
  607. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  608. for (i = 0; i < RTV_MAX_NUM_USE_SUBCHANNEL; i++) {
  609. if ((g_nRegSubChArrayIdxBits & (1<<i)) == 0) {
  610. #else
  611. i = 0;
  612. #endif
  613. g_nRegSubChArrayIdxBits |= (1<<i);
  614. g_atRegSubchInfo[i].nSubChID = nSubChID;
  615. g_atRegSubchInfo[i].eHwSubChIdx = eHwSubChIdx;
  616. g_atRegSubchInfo[i].eServiceType = eServiceType;
  617. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  618. break;
  619. }
  620. }
  621. #endif
  622. g_nOpenedSubChNum++;
  623. }
  624. /* For Test */
  625. INT rtvTDMB_OpenSubChannelExt(U32 dwChFreqKHz, UINT nSubChID,
  626. enum E_RTV_SERVICE_TYPE eServiceType, UINT nThresholdSize)
  627. {
  628. INT nRet;
  629. rtvTDMB_CloseFIC();
  630. rtvTDMB_CloseAllSubChannels();
  631. nRet = rtvTDMB_ScanFrequency(dwChFreqKHz);
  632. rtvTDMB_CloseFIC();
  633. if (nRet == RTV_SUCCESS)
  634. nRet = rtvTDMB_OpenSubChannel(dwChFreqKHz, nSubChID,
  635. eServiceType, nThresholdSize);
  636. else
  637. RTV_DBGMSG1("rtvTDMB_OpenSubChannelExt() fail: %d\n", nRet);
  638. return nRet;
  639. }
  640. INT rtvTDMB_OpenSubChannel(U32 dwChFreqKHz, UINT nSubChID,
  641. enum E_RTV_SERVICE_TYPE eServiceType, UINT nThresholdSize)
  642. {
  643. INT nRet = RTV_SUCCESS;
  644. enum E_TDMB_HW_SUBCH_IDX_TYPE eHwChIdx;
  645. if (nSubChID > (MAX_NUM_TDMB_SUBCH - 1))
  646. return RTV_INVAILD_SUBCHANNEL_ID;
  647. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  648. if (!nThresholdSize || (nThresholdSize > (32 * RTV_TSP_XFER_SIZE)))
  649. return RTV_INVAILD_THRESHOLD_SIZE;
  650. #endif
  651. #ifndef RTV_CIF_MODE_ENABLED
  652. if (g_fRtvFicOpened)
  653. return RTV_SHOULD_CLOSE_FIC;
  654. #endif
  655. if (g_nOpenedSubChNum > RTV_MAX_NUM_USE_SUBCHANNEL)
  656. return RTV_NO_MORE_SUBCHANNEL;
  657. #if (defined(RTV_IF_SPI) || defined(RTV_IF_EBI2))\
  658. && defined(RTV_CIF_MODE_ENABLED)
  659. nThresholdSize = RTV_SPI_CIF_MODE_INTERRUPT_SIZE;
  660. #endif
  661. RTV_GUARD_LOCK;
  662. /* Check if the specified subch opened or closed? */
  663. if (dwChFreqKHz == g_dwRtvPrevChFreqKHz) {
  664. /* Is registerd sub ch ID? */
  665. if (g_aRegSubChIdBits[DIV32(nSubChID)] & (1<<MOD32(nSubChID))) {
  666. RTV_DBGMSG0("[rtvTDMB_OpenSubChannel]Already opened\n");
  667. nRet = RTV_ALREADY_OPENED_SUBCHANNEL_ID;
  668. goto tdmb_open_subch_exit; /* OK */
  669. }
  670. } else { /* Different freq */
  671. if (g_nOpenedSubChNum) {
  672. nRet = RTV_SHOULD_CLOSE_SUBCHANNELS;
  673. goto tdmb_open_subch_exit;
  674. }
  675. }
  676. switch (eServiceType) {
  677. case RTV_SERVICE_DMB:
  678. eHwChIdx = TDMB_HW_CH_IDX_TDMB;
  679. break;
  680. case RTV_SERVICE_DAB: /* DAB */
  681. if (!(g_nUsedHwSubChIdxBits & (1<<TDMB_HW_CH_IDX_DAB_0)))
  682. eHwChIdx = TDMB_HW_CH_IDX_DAB_0;
  683. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  684. else if (!(g_nUsedHwSubChIdxBits & (1<<TDMB_HW_CH_IDX_DAB_1)))
  685. eHwChIdx = TDMB_HW_CH_IDX_DAB_1;
  686. #endif
  687. else {
  688. nRet = RTV_OPENING_SERVICE_FULL;
  689. goto tdmb_open_subch_exit;
  690. }
  691. break;
  692. case RTV_SERVICE_DABPLUS: /* DAB+ */
  693. eHwChIdx = TDMB_HW_CH_IDX_DABPLUS;
  694. break;
  695. default:
  696. nRet = RTV_INVAILD_SERVICE_TYPE;
  697. goto tdmb_open_subch_exit;
  698. }
  699. /* NOTE: The below code should placed after checking of subch opened. */
  700. if (g_nUsedHwSubChIdxBits & (1<<eHwChIdx)) {
  701. nRet = RTV_OPENING_SERVICE_FULL;
  702. goto tdmb_open_subch_exit;
  703. }
  704. tdmb_DisableFastScanMode();
  705. /* Check if new freq equal to previous freq or not. */
  706. if (g_dwRtvPrevChFreqKHz == dwChFreqKHz) {
  707. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  708. if (!g_nOpenedSubChNum) {
  709. #endif
  710. RTV_REG_MAP_SEL(OFDM_PAGE);
  711. RTV_REG_SET(0x10, 0xCA);
  712. RTV_REG_SET(0x10, 0xCB);
  713. #if (RTV_MAX_NUM_USE_SUBCHANNEL >= 2)
  714. }
  715. #endif
  716. tdmb_OpenSubChannel(nSubChID, eServiceType,
  717. nThresholdSize, eHwChIdx);
  718. } else {
  719. rtv_StopDemod(); /* To hold until rf set */
  720. tdmb_OpenSubChannel(nSubChID, eServiceType,
  721. nThresholdSize, eHwChIdx);
  722. /* Must place in the last */
  723. nRet = rtvRF_SetFrequency(dwChFreqKHz);
  724. rtv_SoftReset();
  725. if (nRet != RTV_SUCCESS)
  726. goto tdmb_open_subch_exit;
  727. }
  728. /* Update the state of TDMB. */
  729. g_eTdmbState = TDMB_STATE_PLAY;
  730. tdmb_open_subch_exit:
  731. RTV_GUARD_FREE;
  732. return nRet;
  733. }
  734. static INLINE BOOL tdmb_CheckScanStatus(INT *sucess_flag,
  735. U8 DAB_Mode, U8 OFDM_L,
  736. U8 FIC_CRC, int ScanT, int *scan_status)
  737. {
  738. BOOL fBreak = FALSE;
  739. if (DAB_Mode == 0x00) {
  740. if (OFDM_L) {
  741. if (FIC_CRC < 100) {
  742. sucess_flag = RTV_SUCCESS;
  743. fBreak = TRUE;
  744. } else if (FIC_CRC != 255) {
  745. *scan_status = 5;
  746. *sucess_flag = RTV_CHANNEL_NOT_DETECTED;
  747. fBreak = TRUE;
  748. }
  749. } else if (ScanT > 500) { /* Tuning pointer */
  750. *scan_status = 3;
  751. *sucess_flag = RTV_CHANNEL_NOT_DETECTED;
  752. fBreak = TRUE;
  753. }
  754. } else {
  755. *scan_status = 2;
  756. *sucess_flag = RTV_CHANNEL_NOT_DETECTED;
  757. fBreak = TRUE;
  758. }
  759. return fBreak;
  760. }
  761. /* NOTE: When this rountine executed, all sub channel and FIC should closed */
  762. INT rtvTDMB_ScanFrequency(U32 dwChFreqKHz)
  763. {
  764. U8 Mon_FSM = 0;
  765. int peak_pwr = 0;
  766. U8 DAB_Mode, peak_pwr_Msb = 0, peak_pwr_Lsb = 0;
  767. U8 OFDM_L = 0;
  768. U8 AGC_L = 0;
  769. U8 FIC_CRC = 255;
  770. U8 Sdone = 0, Slock = 0;
  771. INT sucess_flag = 0;
  772. UINT ScanT = 0;
  773. int pwr_threshold = 600; /* OPT */
  774. int scan_status = 0;
  775. U8 FIC_Sync = 0;
  776. U8 Ccnt = 0, Tcnt = 0;
  777. sucess_flag = RTV_CHANNEL_NOT_DETECTED;
  778. if (g_fRtvFicOpened) /* For openFIC[hdr_on] => Scan[hdr_off] */
  779. return RTV_SHOULD_CLOSE_FIC; /* for header On/Off */
  780. if (g_nOpenedSubChNum)
  781. return RTV_SHOULD_CLOSE_SUBCHANNELS;
  782. RTV_GUARD_LOCK;
  783. /* Update the state of TDMB. */
  784. g_eTdmbState = TDMB_STATE_SCAN;
  785. tdmb_EnableFastScanMode();
  786. rtv_StopDemod();
  787. g_fRtvFicOpened = TRUE;
  788. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  789. rtv_OpenFIC_SPI_Scan();
  790. #else
  791. RTV_DBGMSG0("[rtvTDMB_ScanFrequency] rtv_OpenFIC_TSIF_Scan()\n");
  792. g_nRtvFicOpenedStatePath = rtv_OpenFIC_TSIF_Scan();
  793. RTV_REG_MAP_SEL(FEC_PAGE);
  794. RTV_REG_MASK_SET(0x11, 0x04, 0x04);
  795. RTV_REG_MASK_SET(0x11, 0x04, 0x00);
  796. #endif
  797. sucess_flag = rtvRF_SetFrequency(dwChFreqKHz);
  798. if (sucess_flag != RTV_SUCCESS)
  799. goto TDMB_SCAN_EXIT;
  800. RTV_DELAY_MS(20);
  801. rtv_SoftReset();
  802. while (1) {
  803. if (++ScanT == 800) {
  804. RTV_DBGMSG0("[rtvTDMB_ScanFrequency] Scan Timeout!\n");\
  805. scan_status = 7;
  806. sucess_flag = RTV_CHANNEL_NOT_DETECTED;
  807. break;
  808. }
  809. RTV_REG_MAP_SEL(OFDM_PAGE);
  810. RTV_REG_MASK_SET(0x82, 0x02,0x02);
  811. RTV_REG_MASK_SET(0x82, 0x02,0x00);
  812. DAB_Mode = RTV_REG_GET(0xBA);
  813. DAB_Mode = (DAB_Mode>>4) & 0x03;
  814. RTV_REG_MASK_SET(0x12, 0x80, 0x80);
  815. RTV_REG_MASK_SET(0x12, 0x80, 0x00);
  816. RTV_REG_MAP_SEL(OFDM_PAGE);
  817. peak_pwr_Msb = RTV_REG_GET(0xD6);
  818. peak_pwr_Lsb = RTV_REG_GET(0xD5);
  819. peak_pwr = ((peak_pwr_Msb&0xff)<<8) | (peak_pwr_Lsb&0xff);
  820. OFDM_L = RTV_REG_GET(0xB8);
  821. OFDM_L = (OFDM_L>>0) & 0x01;
  822. RTV_REG_MAP_SEL(FEC_PAGE);
  823. FIC_CRC = RTV_REG_GET(0x30);
  824. RTV_REG_MAP_SEL(OFDM_PAGE);
  825. AGC_L = RTV_REG_GET(0xB8);
  826. AGC_L = (AGC_L>>3) & 0x01;
  827. Mon_FSM = RTV_REG_GET(0xB8);
  828. Mon_FSM = (Mon_FSM>>5)&0x07;
  829. Sdone = RTV_REG_GET(0xD4);
  830. Slock = RTV_REG_GET(0xD4);
  831. Sdone = (Sdone&0x02)>>1;
  832. Slock = (Slock&0x01)>>0;
  833. RTV_REG_MAP_SEL(FEC_PAGE);
  834. FIC_Sync = RTV_REG_GET(0x10);
  835. FIC_Sync = FIC_Sync & 0x01;
  836. RTV_REG_MAP_SEL(OFDM_PAGE);
  837. Ccnt = RTV_REG_GET(0xC1);
  838. Tcnt = RTV_REG_GET(0xC2);
  839. Ccnt = (Ccnt>>3)&0x1f;
  840. Tcnt = Tcnt & 0x1f;
  841. if (AGC_L) {
  842. if (Sdone || ScanT > 200) {
  843. if (Slock || (peak_pwr > pwr_threshold)) {
  844. if (tdmb_CheckScanStatus(&sucess_flag,
  845. DAB_Mode, OFDM_L,
  846. FIC_CRC, ScanT, &scan_status))
  847. break;
  848. } else {
  849. scan_status = 4;
  850. sucess_flag = RTV_CHANNEL_NOT_DETECTED;
  851. break;
  852. }
  853. }
  854. }
  855. RTV_DELAY_MS(1);
  856. }
  857. TDMB_SCAN_EXIT:
  858. tdmb_DisableFastScanMode();
  859. if (sucess_flag != RTV_SUCCESS) {
  860. rtv_CloseFIC(0); /* rtvTDMB_CloseFIC() was called when lock_s */
  861. g_eTdmbState = TDMB_STATE_INIT;
  862. g_fRtvFicOpened = FALSE;
  863. }
  864. RTV_GUARD_FREE;
  865. #if 1
  866. RTV_DBGMSG3("\n[rtvTDMB_ScanFrequency: %u] Power_Peak(%d), AGCL(%d)\n",
  867. dwChFreqKHz, peak_pwr, AGC_L);
  868. RTV_DBGMSG2("\tOFDML = %d, CRC = %d\n", OFDM_L, FIC_CRC);
  869. RTV_DBGMSG3("\tScanT = %d Status = %d scan_done = %d\n",
  870. ScanT, scan_status, Sdone);
  871. RTV_DBGMSG3("\tscan_lock = %d FSM = %d scan_success = %d\n",
  872. Slock, Mon_FSM, sucess_flag);
  873. #endif
  874. return sucess_flag;
  875. }
  876. #define RTV_TDMB_READ_FIC_TIMEOUT_CNT 500
  877. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  878. static INLINE INT tdmb_ReadFIC_SPI(U8 *pbBuf)
  879. {
  880. int ret_size;
  881. U8 istatus;
  882. UINT lock_s;
  883. UINT elapsed_cnt = 0;
  884. UINT timeout_cnt = RTV_TDMB_READ_FIC_TIMEOUT_CNT;
  885. while (1) {
  886. RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
  887. istatus = RTV_REG_GET(0x10);
  888. if (istatus & SPI_INTR_BITS) {
  889. if (!(istatus & SPI_UNDERFLOW_INTR)) {
  890. RTV_REG_MAP_SEL(SPI_MEM_PAGE);
  891. RTV_REG_BURST_GET(0x10, pbBuf,
  892. g_nRtvInterruptLevelSize);
  893. ret_size = 384;
  894. break;
  895. }
  896. }
  897. lock_s = tdmb_GetLockStatus();
  898. if (!(lock_s & RTV_TDMB_OFDM_LOCK_MASK)) {
  899. RTV_DELAY_MS(30);
  900. RTV_DBGMSG2("[tdmb_ReadFIC_SPI] ##lock_s(0x%02X)[%u]\n",
  901. lock_s, elapsed_cnt);
  902. ret_size = -55;
  903. break;
  904. }
  905. if (timeout_cnt--)
  906. RTV_DELAY_MS(1);
  907. else {
  908. ret_size = RTV_FIC_READ_TIMEOUT;
  909. break;
  910. }
  911. elapsed_cnt = RTV_TDMB_READ_FIC_TIMEOUT_CNT - timeout_cnt;
  912. }
  913. return ret_size;
  914. }
  915. #elif defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  916. static INLINE INT tdmb_ReadFIC_I2C(U8 *pbBuf)
  917. {
  918. #ifdef RTV_FIC_POLLING_MODE
  919. U8 istatus;
  920. int ret_size;
  921. UINT timeout_cnt = RTV_TDMB_READ_FIC_TIMEOUT_CNT;
  922. RTV_REG_MAP_SEL(FEC_PAGE);
  923. while (1) {
  924. istatus = RTV_REG_GET(0x13) & 0x10; /* [4] */
  925. #if 0
  926. RTV_DBGMSG1("[tdmb_ReadFIC_I2C] istatus(0x%02X)\n", istatus);
  927. #endif
  928. if (istatus) {
  929. RTV_REG_MASK_SET(0x26, 0x10, 0x10);
  930. RTV_REG_BURST_GET(0x29, pbBuf, 400);
  931. RTV_REG_SET(0x26, 0x01);
  932. /* FIC I2C interrupt status clear. */
  933. RTV_REG_SET(0x11, I2C_INTR_POL_ACTIVE|0x04);
  934. RTV_REG_SET(0x11, I2C_INTR_POL_ACTIVE);
  935. /* FIC I2C memory clear. */
  936. RTV_REG_MASK_SET(0x26, 0x04, 0x04);
  937. RTV_REG_MASK_SET(0x26, 0x04, 0x00);
  938. memmove(pbBuf+215, pbBuf+231, 169);
  939. ret_size = 384;
  940. break;
  941. }
  942. if (timeout_cnt--)
  943. RTV_DELAY_MS(1);
  944. else {
  945. ret_size = RTV_FIC_READ_TIMEOUT;
  946. break;
  947. }
  948. }
  949. return ret_size;
  950. #else
  951. RTV_REG_MAP_SEL(FEC_PAGE);
  952. RTV_REG_MASK_SET(0x26, 0x10, 0x10);
  953. RTV_REG_BURST_GET(0x29, pbBuf, 400);
  954. RTV_REG_SET(0x26, 0x01);
  955. /* FIC I2C interrupt status clear. */
  956. RTV_REG_SET(0x11, I2C_INTR_POL_ACTIVE|0x04);
  957. RTV_REG_SET(0x11, I2C_INTR_POL_ACTIVE);
  958. /* FIC I2C memory clear. */
  959. RTV_REG_MASK_SET(0x26, 0x04, 0x04);
  960. RTV_REG_MASK_SET(0x26, 0x04, 0x00);
  961. memmove(pbBuf+215, pbBuf+231, 169);
  962. #if 1
  963. printk(KERN_INFO "[READ] 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X [0x%02X 0x%02X] | 0x%02X 0x%02X\n",
  964. pbBuf[0], pbBuf[1], pbBuf[2], pbBuf[3], pbBuf[4], pbBuf[5],
  965. pbBuf[382], pbBuf[383], pbBuf[398], pbBuf[399]);
  966. #endif
  967. return 384;
  968. #endif
  969. }
  970. #endif
  971. /* NOTE: Do NOT read at the ISR */
  972. INT rtvTDMB_ReadFIC(U8 *pbBuf)
  973. {
  974. int ret_size = 0;
  975. if (!g_fRtvFicOpened) {
  976. RTV_DBGMSG0("[rtvTDMB_ReadFIC] NOT OPEN FIC\n");
  977. return RTV_NOT_OPENED_FIC;
  978. }
  979. RTV_GUARD_LOCK;
  980. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  981. ret_size = tdmb_ReadFIC_SPI(pbBuf);
  982. #elif defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  983. ret_size = tdmb_ReadFIC_I2C(pbBuf);
  984. #endif
  985. RTV_GUARD_FREE;
  986. return ret_size;
  987. }
  988. void rtvTDMB_CloseFIC(void)
  989. {
  990. if (!g_fRtvFicOpened)
  991. return;
  992. RTV_GUARD_LOCK;
  993. rtv_CloseFIC(g_nOpenedSubChNum);
  994. if (!g_nOpenedSubChNum) {
  995. #ifdef TDMB_CIF_MODE_DRIVER
  996. rtvCIFDEC_Deinit(); /* Skip rtvCIFDEC_DeleteSubChannelID() */
  997. #endif
  998. g_eTdmbState = TDMB_STATE_INIT; /* Update the state of TDMB. */
  999. }
  1000. g_fRtvFicOpened = FALSE;
  1001. RTV_GUARD_FREE;
  1002. }
  1003. INT rtvTDMB_OpenFIC(void)
  1004. {
  1005. INT nRet = RTV_SUCCESS;
  1006. RTV_DBGMSG1("[rtvTDMB_OpenFIC] g_eTdmbState(%d)\n", g_eTdmbState);
  1007. if (g_fRtvFicOpened)
  1008. return RTV_SUCCESS;
  1009. RTV_GUARD_LOCK;
  1010. nRet = rtv_OpenFIC(g_eTdmbState);
  1011. if (nRet == RTV_SUCCESS)
  1012. g_fRtvFicOpened = TRUE;
  1013. #if 0
  1014. #if defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  1015. RTV_DBGMSG1("[rtvTDMB_OpenFIC] Opened with FIC_state_path(%d)\n",
  1016. g_nRtvFicOpenedStatePath);
  1017. #endif
  1018. #endif
  1019. RTV_GUARD_FREE;
  1020. return nRet;
  1021. }
  1022. static void tdmb_InitHOST(void)
  1023. {
  1024. RTV_REG_MAP_SEL(HOST_PAGE);
  1025. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  1026. RTV_REG_SET(0x05, (1<<7) | 0x00);
  1027. RTV_REG_SET(0x04, 0x40); /* demod INT dis. */
  1028. #endif
  1029. #if defined(RTV_CHIP_PKG_CSP) && defined(RTV_FIC_I2C_INTR_ENABLED)
  1030. RTV_DBGMSG2("[tdmb_InitHOST] 0x08(0x%02X), 0x1A(0x%02X)\n",
  1031. RTV_REG_GET(0x08), RTV_REG_GET(0x1A));
  1032. RTV_REG_SET(0x04, 0x40);
  1033. RTV_REG_SET(0x1A, 0x08); /* GPD3 PAD disable */
  1034. RTV_REG_SET(0x08, (1<<5)|0x10); /* GPD3 => INT0 */
  1035. #else
  1036. RTV_REG_SET(0x08, 0x10);
  1037. #endif
  1038. RTV_REG_SET(0x09, 0x00);
  1039. RTV_REG_SET(0x10, 0xA0);
  1040. RTV_REG_SET(0x13, 0x04);
  1041. RTV_REG_SET(0x0B, 0xCE);
  1042. RTV_REG_SET(0x0D, 0x17);
  1043. RTV_REG_SET(0x19, 0x20);
  1044. RTV_REG_SET(0x20, 0x19);
  1045. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  1046. RTV_REG_SET(0x05, (1<<7) | 0x3F);
  1047. #else
  1048. RTV_REG_SET(0x05, 0x3F);
  1049. #endif
  1050. RTV_REG_SET(0x07, 0x41);
  1051. RTV_REG_SET(0x07, 0x40);
  1052. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  1053. /* <2> SPI_INT0(GPP0) disable <4> I2C INT0 disable */
  1054. RTV_REG_SET(0x1D, 0xC4);
  1055. #endif
  1056. #if defined(RTV_CHIP_PKG_CSP) && defined(RTV_FIC_I2C_INTR_ENABLED)
  1057. #ifdef RTV_INTR_POLARITY_LOW_ACTIVE
  1058. RTV_REG_SET(0x15, 0x04); /* 2013: default high */
  1059. #else
  1060. RTV_REG_SET(0x15, 0x00); /* 2013 */
  1061. #endif
  1062. #endif
  1063. }
  1064. static void tdmb_InitOFDM(void)
  1065. {
  1066. RTV_REG_MAP_SEL(OFDM_PAGE);
  1067. RTV_REG_SET(0x10, 0xCB);
  1068. RTV_REG_SET(0x1F, 0x08);
  1069. RTV_REG_SET(0x31, 0xFF);
  1070. RTV_REG_SET(0x32, 0xFF);
  1071. rtvRF_InitOfdmTnco();
  1072. RTV_REG_SET(0x3F, 0x00);
  1073. RTV_REG_SET(0x6C, 0x0C);
  1074. RTV_REG_SET(0x6F, 0x40);
  1075. RTV_REG_SET(0x86, 0x20);
  1076. RTV_REG_SET(0x87, 0x3F);
  1077. RTV_REG_SET(0x40, 0x42);
  1078. RTV_REG_SET(0x96, 0x02);
  1079. }
  1080. static void tdmb_InitFEC(void)
  1081. {
  1082. RTV_REG_MAP_SEL(FEC_PAGE);
  1083. RTV_REG_SET(0x2D, 0x80);
  1084. RTV_REG_SET(0x2E, 0x5F);
  1085. RTV_REG_SET(0x34, 0x00);
  1086. RTV_REG_SET(0x37, 0x00);
  1087. RTV_REG_SET(0xA8, 0x7F);
  1088. RTV_REG_SET(0xAA, 0x00);
  1089. RTV_REG_SET(0xB0, 0x07);
  1090. RTV_REG_SET(0xD5, 0x80); /* DEFAULT Time Slice OFF. */
  1091. #ifdef RTV_FORCE_INSERT_SYNC_BYTE
  1092. RTV_REG_SET(0xF8, 0x04|0x02);
  1093. #else
  1094. RTV_REG_SET(0xF8, 0x04);
  1095. #endif
  1096. RTV_REG_SET(0xFA, 0x07);
  1097. /* all disable output */
  1098. RTV_REG_SET(0xB2, 0x80); /* FIC: */
  1099. RTV_REG_SET(0xB3, 0xF6); /* MSC */
  1100. RTV_REG_SET(0xB4, 0x86); /* TDMB */
  1101. RTV_REG_SET(0xB5, 0xB6); /* FIDC, DABP */
  1102. RTV_REG_SET(0xAA, 0x00); /* TSIF OFF */
  1103. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  1104. #ifdef RTV_NULL_PID_GENERATE
  1105. RTV_REG_SET(0xA4, 0x81|0x02);
  1106. #else
  1107. RTV_REG_SET(0xA4, 0x81);
  1108. #endif
  1109. #ifdef RTV_ERROR_TSP_OUTPUT_DISABLE
  1110. RTV_REG_SET(0xA5, 0xC0);
  1111. #else
  1112. RTV_REG_SET(0xA5, 0x80);
  1113. #endif
  1114. RTV_REG_SET(0xAF, 0x00);
  1115. RTV_REG_SET(0xB0, 0x04);
  1116. #else
  1117. rtv_ConfigureTsifFormat();
  1118. RTV_REG_SET(0xB0, 0x00|RTV_FEC_TSIF_OUT_SPEED);
  1119. #endif
  1120. RTV_REG_SET(0xAA, 0x7F);
  1121. #if defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  1122. RTV_REG_MAP_SEL(FEC_PAGE);
  1123. RTV_REG_SET(0x16, 0xFF);
  1124. RTV_REG_SET(0x17, 0xFF); /* I2C intr disable */
  1125. #endif
  1126. RTV_REG_SET(0xD3, 0x00);
  1127. }
  1128. void rtvOEM_ConfigureInterrupt(void)
  1129. {
  1130. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  1131. RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
  1132. RTV_REG_SET(0x21, SPI_INTR_POL_ACTIVE|0x02);
  1133. #ifdef RTV_IF_SPI
  1134. RTV_REG_SET(0x27, 0x00); /* AUTO_INTR: 0 */
  1135. #else
  1136. RTV_REG_SET(0x27, 0x02); /* AUTO_INTR: 0 */
  1137. #endif
  1138. RTV_REG_SET(0x2B, RTV_SPI_INTR_DEACT_PRD_VAL);
  1139. RTV_REG_SET(0x2A, 1); /* SRAM init */
  1140. RTV_REG_SET(0x2A, 0);
  1141. #else
  1142. RTV_REG_MAP_SEL(FEC_PAGE);
  1143. RTV_REG_SET(0x11, I2C_INTR_POL_ACTIVE);
  1144. #endif
  1145. }
  1146. static void tdmb_InitDemod(void)
  1147. {
  1148. tdmb_InitHOST();
  1149. tdmb_InitOFDM();
  1150. tdmb_InitFEC();
  1151. rtvOEM_ConfigureInterrupt();
  1152. }
  1153. INT rtvTDMB_Initialize(unsigned long interface)
  1154. {
  1155. INT nRet;
  1156. #if defined(RTV_IF_SPI)
  1157. mtv319_set_port_if(interface);
  1158. #endif
  1159. g_nOpenedSubChNum = 0;
  1160. g_nRegSubChArrayIdxBits = 0x0;
  1161. g_aRegSubChIdBits[0] = 0x00000000;
  1162. g_aRegSubChIdBits[1] = 0x00000000;
  1163. g_nUsedHwSubChIdxBits = 0x00;
  1164. g_nTdmbPrevAntennaLevel = 0;
  1165. g_eTdmbState = TDMB_STATE_INIT;
  1166. g_fRtvFicOpened = FALSE;
  1167. g_fTdmbFastScanEnabled = FALSE;
  1168. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  1169. g_nRtvInterruptLevelSize = 0;
  1170. #elif defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  1171. g_nRtvFicOpenedStatePath = FIC_NOT_OPENED;
  1172. #endif
  1173. nRet = rtv_InitSystem();
  1174. if (nRet != RTV_SUCCESS)
  1175. return nRet;
  1176. /* Must after rtv_InitSystem(). */
  1177. tdmb_InitDemod();
  1178. nRet = rtvRF_Initilize();
  1179. if (nRet != RTV_SUCCESS)
  1180. goto tdmb_init_exit;
  1181. rtv_SoftReset();
  1182. tdmb_init_exit:
  1183. return RTV_SUCCESS;
  1184. }