mtv319_internal.h 16 KB

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  1. /*
  2. *
  3. * File name: mtv319_internal.h
  4. *
  5. * Description : MTV319 internal header file.
  6. *
  7. * Copyright (C) (2013, RAONTECH)
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation version 2.
  12. *
  13. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14. * kind, whether express or implied; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. */
  19. #ifndef __MTV319_INTERNAL_H__
  20. #define __MTV319_INTERNAL_H__
  21. #ifdef __cplusplus
  22. extern "C"{
  23. #endif
  24. #include "mtv319.h"
  25. #if defined(RTV_CIF_MODE_ENABLED) && defined(RTV_CIFDEC_IN_DRIVER)
  26. #include "mtv319_cifdec.h"
  27. #define TDMB_CIF_MODE_DRIVER /* Internal use only */
  28. #endif
  29. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  30. #if defined(RTV_INTR_POLARITY_LOW_ACTIVE)
  31. #define SPI_INTR_POL_ACTIVE 0x00
  32. #elif defined(RTV_INTR_POLARITY_HIGH_ACTIVE)
  33. #define SPI_INTR_POL_ACTIVE (1<<7)
  34. #endif
  35. #else
  36. #if defined(RTV_INTR_POLARITY_LOW_ACTIVE)
  37. #define I2C_INTR_POL_ACTIVE 0x08 /* level low */
  38. #elif defined(RTV_INTR_POLARITY_HIGH_ACTIVE)
  39. #define I2C_INTR_POL_ACTIVE 0x18 /* level high */
  40. #endif
  41. #endif
  42. struct RTV_REG_INIT_INFO {
  43. U8 bReg;
  44. U8 bVal;
  45. };
  46. struct RTV_REG_MASK_INFO {
  47. U8 bReg;
  48. U8 bMask;
  49. U8 bVal;
  50. };
  51. enum RTV_TDMB_CH_IDX_TYPE {
  52. RTV_TDMB_CH_IDX_7A = 0, /* 175280: 7A */
  53. RTV_TDMB_CH_IDX_7B, /* 177008: 7B */
  54. RTV_TDMB_CH_IDX_7C, /* 178736: 7C */
  55. RTV_TDMB_CH_IDX_8A, /* 181280: 8A */
  56. RTV_TDMB_CH_IDX_8B, /* 183008: 8B */
  57. RTV_TDMB_CH_IDX_8C, /* 184736: 8C */
  58. RTV_TDMB_CH_IDX_9A, /* 187280: 9A */
  59. RTV_TDMB_CH_IDX_9B, /* 189008: 9B */
  60. RTV_TDMB_CH_IDX_9C, /* 190736: 9C */
  61. RTV_TDMB_CH_IDX_10A, /* 193280: 10A */
  62. RTV_TDMB_CH_IDX_10B, /* 195008: 10B */
  63. RTV_TDMB_CH_IDX_10C, /* 196736: 10C */
  64. RTV_TDMB_CH_IDX_11A, /* 199280: 11A */
  65. RTV_TDMB_CH_IDX_11B, /* 201008: 11B */
  66. RTV_TDMB_CH_IDX_11C, /* 202736: 11C */
  67. RTV_TDMB_CH_IDX_12A, /* 205280: 12A */
  68. RTV_TDMB_CH_IDX_12B, /* 207008: 12B */
  69. RTV_TDMB_CH_IDX_12C, /* 208736: 12C */
  70. RTV_TDMB_CH_IDX_13A, /* 211280: 13A */
  71. RTV_TDMB_CH_IDX_13B, /* 213008: 13B */
  72. RTV_TDMB_CH_IDX_13C, /* 214736: 13C */
  73. MAX_NUM_RTV_TDMB_CH_IDX
  74. };
  75. struct RTV_ADC_CFG_INFO {
  76. U16 wFEBD;
  77. U8 bREFD;
  78. U32 dwTNCO;
  79. };
  80. #if defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  81. #if defined(RTV_TSIF_SPEED_3_Mbps)
  82. #define RTV_FEC_TSIF_OUT_SPEED (12<<0)
  83. #elif defined(RTV_TSIF_SPEED_4_Mbps)
  84. #define RTV_FEC_TSIF_OUT_SPEED (8<<0)
  85. #elif defined(RTV_TSIF_SPEED_5_Mbps)
  86. #define RTV_FEC_TSIF_OUT_SPEED (6<<0)
  87. #elif defined(RTV_TSIF_SPEED_6_Mbps)
  88. #define RTV_FEC_TSIF_OUT_SPEED (5<<0)
  89. #elif defined(RTV_TSIF_SPEED_8_Mbps)
  90. #define RTV_FEC_TSIF_OUT_SPEED (4<<0)
  91. #elif defined(RTV_TSIF_SPEED_10_Mbps)
  92. #define RTV_FEC_TSIF_OUT_SPEED (3<<0)
  93. #elif defined(RTV_TSIF_SPEED_15_Mbps)
  94. #define RTV_FEC_TSIF_OUT_SPEED (2<<0)
  95. #elif defined(RTV_TSIF_SPEED_30_Mbps)
  96. #define RTV_FEC_TSIF_OUT_SPEED (1<<0)
  97. #elif defined(RTV_TSIF_SPEED_60_Mbps)
  98. #define RTV_FEC_TSIF_OUT_SPEED (0<<0)
  99. #else
  100. #error "Code not present"
  101. #endif
  102. #endif /* #if defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE) */
  103. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  104. #if (RTV_SRC_CLK_FREQ_KHz == 4000) /* FPGA */
  105. #define RTV_SPI_INTR_DEACT_PRD_VAL 0x51
  106. #elif (RTV_SRC_CLK_FREQ_KHz == 13000)
  107. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  108. #elif (RTV_SRC_CLK_FREQ_KHz == 16000)
  109. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  110. #elif (RTV_SRC_CLK_FREQ_KHz == 16384)
  111. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  112. #elif (RTV_SRC_CLK_FREQ_KHz == 18000)
  113. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  114. #elif (RTV_SRC_CLK_FREQ_KHz == 19200) /* 1 clk: 52.08ns */
  115. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  116. #elif (RTV_SRC_CLK_FREQ_KHz == 24000)
  117. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  118. #elif (RTV_SRC_CLK_FREQ_KHz == 24576) /* 1 clk: 40.7ns */
  119. #define RTV_SPI_INTR_DEACT_PRD_VAL ((7<<4)|2)/*about 10us*/
  120. #elif (RTV_SRC_CLK_FREQ_KHz == 26000)
  121. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  122. #elif (RTV_SRC_CLK_FREQ_KHz == 27000)
  123. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  124. #elif (RTV_SRC_CLK_FREQ_KHz == 32000)
  125. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  126. #elif (RTV_SRC_CLK_FREQ_KHz == 32768)
  127. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  128. #elif (RTV_SRC_CLK_FREQ_KHz == 36000) /* 1clk: 27.7 ns */
  129. #define RTV_SPI_INTR_DEACT_PRD_VAL ((7<<4)|3)
  130. #elif (RTV_SRC_CLK_FREQ_KHz == 38400)
  131. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  132. #elif (RTV_SRC_CLK_FREQ_KHz == 40000)
  133. #define RTV_SPI_INTR_DEACT_PRD_VAL ((6<<4)|3)
  134. #elif (RTV_SRC_CLK_FREQ_KHz == 48000) /* 1clk: 20.8 ns */
  135. #define RTV_SPI_INTR_DEACT_PRD_VAL ((9<<4)|0)
  136. #else
  137. #error "Code not present"
  138. #endif
  139. #endif /* #if defined(RTV_IF_SPI) */
  140. #if (RTV_TSP_XFER_SIZE == 188)
  141. #define N_DATA_LEN_BITVAL 0x02
  142. #define ONE_DATA_LEN_BITVAL 0x00
  143. #elif (RTV_TSP_XFER_SIZE == 204)
  144. #define N_DATA_LEN_BITVAL 0x03
  145. #define ONE_DATA_LEN_BITVAL (1<<5)
  146. #endif
  147. #ifdef RTV_CIF_MODE_ENABLED /* can be with FIC or multi subch */
  148. #define HEADER_LEN_BITVAL (1<<2)
  149. #else
  150. #define HEADER_LEN_BITVAL 0x00
  151. #endif
  152. #define SPI_OVERFLOW_INTR 0x02
  153. #define SPI_UNDERFLOW_INTR 0x20
  154. #define SPI_THRESHOLD_INTR 0x08
  155. #define SPI_INTR_BITS (SPI_THRESHOLD_INTR|SPI_UNDERFLOW_INTR|SPI_OVERFLOW_INTR)
  156. #define TOP_PAGE 0x00
  157. #define HOST_PAGE 0x00
  158. #define OFDM_PAGE 0x08
  159. #define FEC_PAGE 0x09
  160. #define SPI_CTRL_PAGE 0x0E
  161. #define RF_PAGE 0x0F
  162. #define SPI_MEM_PAGE 0xFF /* Temp value. > 15 */
  163. #define DEMOD_0SC_DIV2_ON 0x80
  164. #define DEMOD_0SC_DIV2_OFF 0x00
  165. #if (RTV_SRC_CLK_FREQ_KHz >= 32000)
  166. #define DEMOD_OSC_DIV2 DEMOD_0SC_DIV2_ON
  167. #else
  168. #define DEMOD_OSC_DIV2 DEMOD_0SC_DIV2_OFF
  169. #endif
  170. #define MAP_SEL_REG 0x03
  171. #define MAP_SEL_VAL(page) (DEMOD_OSC_DIV2|page)
  172. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  173. #define RTV_REG_MAP_SEL(page) g_bRtvPage = page
  174. #define RTV_REG_GET_MAP_SEL g_bRtvPage
  175. #else
  176. #define RTV_REG_MAP_SEL(page)\
  177. do {\
  178. RTV_REG_SET(MAP_SEL_REG, MAP_SEL_VAL(page));\
  179. g_bRtvPage = page;\
  180. } while (0)
  181. #define RTV_REG_GET_MAP_SEL\
  182. (RTV_REG_GET(MAP_SEL_REG) & ~DEMOD_OSC_DIV2)
  183. #endif
  184. #define TDMB_FREQ_START__KOREA 175280
  185. #define TDMB_FREQ_STEP__KOREA 1728 /* about... */
  186. /* To use at open FIC */
  187. enum E_TDMB_STATE {
  188. TDMB_STATE_INIT = 0,
  189. TDMB_STATE_SCAN,
  190. TDMB_STATE_PLAY
  191. };
  192. enum E_RTV_FIC_OPENED_PATH_TYPE {
  193. FIC_NOT_OPENED = 0,
  194. FIC_OPENED_PATH_NOT_USE_IN_PLAY,
  195. FIC_OPENED_PATH_I2C_IN_SCAN,
  196. FIC_OPENED_PATH_TSIF_IN_SCAN,
  197. FIC_OPENED_PATH_I2C_IN_PLAY,
  198. FIC_OPENED_PATH_TSIF_IN_PLAY
  199. };
  200. extern BOOL g_fRtvFicOpened;
  201. #if defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  202. extern enum E_RTV_FIC_OPENED_PATH_TYPE g_nRtvFicOpenedStatePath;
  203. #endif
  204. extern U8 g_bRtvIntrMaskReg;
  205. /*==============================================================================
  206. *
  207. * Common inline functions.
  208. *
  209. *============================================================================*/
  210. /* Forward prototype. */
  211. static INLINE void rtv_DisableTSIF(void)
  212. {
  213. RTV_REG_MAP_SEL(FEC_PAGE);
  214. RTV_REG_SET(0xAA, 0x00);
  215. }
  216. static INLINE void rtv_EnableTSIF(void)
  217. {
  218. RTV_REG_MAP_SEL(FEC_PAGE);
  219. RTV_REG_SET(0xAA, 0x7F);
  220. }
  221. #if defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  222. static INLINE void rtv_ConfigureTsifFormat(void)
  223. {
  224. #if defined(RTV_TSIF_FORMAT_0) /* EN_high, CLK_rising */
  225. RTV_REG_SET(0xA4, 0x89);
  226. RTV_REG_SET(0xA5, 0x80);
  227. RTV_REG_SET(0xAF, 0x00);
  228. #elif defined(RTV_TSIF_FORMAT_1) /* EN_high, CLK_falling */
  229. RTV_REG_SET(0xA4, 0x89);
  230. RTV_REG_SET(0xA5, 0x00);
  231. RTV_REG_SET(0xAF, 0x00);
  232. #elif defined(RTV_TSIF_FORMAT_2) /* EN_low, CLK_rising */
  233. RTV_REG_SET(0xA4, 0x89);
  234. RTV_REG_SET(0xA5, 0x80);
  235. RTV_REG_SET(0xAF, 0x10);
  236. #elif defined(RTV_TSIF_FORMAT_3) /* EN_low, CLK_falling */
  237. RTV_REG_SET(0xA4, 0x89);
  238. RTV_REG_SET(0xA5, 0x00);
  239. RTV_REG_SET(0xAF, 0x10);
  240. #elif defined(RTV_TSIF_FORMAT_4) /* EN_high, CLK_rising + 1CLK add */
  241. RTV_REG_SET(0xA4, 0x89);
  242. RTV_REG_SET(0xA5, 0x84);
  243. RTV_REG_SET(0xAF, 0x00);
  244. #elif defined(RTV_TSIF_FORMAT_5) /* EN_high, CLK_falling + 1CLK add */
  245. RTV_REG_SET(0xA4, 0x89);
  246. RTV_REG_SET(0xA5, 0x04);
  247. RTV_REG_SET(0xAF, 0x00);
  248. #elif defined(RTV_TSIF_FORMAT_6) /* Parallel: EN_high, CLK_falling */
  249. RTV_REG_SET(0xA4, 0x81);
  250. RTV_REG_SET(0xA5, 0x00);
  251. RTV_REG_SET(0xAF, 0x00);
  252. #else
  253. #error "Code not present"
  254. #endif
  255. #ifdef RTV_NULL_PID_GENERATE
  256. {
  257. U8 b0xA4 = RTV_REG_GET(0xA4);
  258. RTV_REG_SET(0xA4, b0xA4|0x02);
  259. }
  260. #endif
  261. #ifdef RTV_ERROR_TSP_OUTPUT_DISABLE
  262. {
  263. U8 b0xA5 = RTV_REG_GET(0xA5);
  264. RTV_REG_SET(0xA5, b0xA5|0x40);
  265. }
  266. #endif
  267. }
  268. #endif /* #elif defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE) */
  269. static INLINE void rtv_DisablePadIntrrupt(void)
  270. {
  271. RTV_REG_MAP_SEL(HOST_PAGE);
  272. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  273. /* <2> SPI_INT0(GPP0) disable <4> I2C INT0 disable */
  274. RTV_REG_SET(0x1D, 0xC4);
  275. #else
  276. /* <2> SPI_INT0(GPP0) disable <4> I2C INT0 disable */
  277. RTV_REG_SET(0x1D, 0xD0);
  278. #endif
  279. }
  280. static INLINE void rtv_EnablePadIntrrupt(void)
  281. {
  282. RTV_REG_MAP_SEL(HOST_PAGE);
  283. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  284. /* <2> SPI_INT0(GPP0) enable <4> I2C INT0 enable */
  285. RTV_REG_SET(0x1D, 0xC0);
  286. #else
  287. RTV_REG_SET(0x1D, 0xC0);
  288. #endif
  289. }
  290. static INLINE void rtv_StopDemod(void)
  291. {
  292. U8 FEC_F8, FEC_FB;
  293. RTV_REG_MAP_SEL(OFDM_PAGE);
  294. RTV_REG_SET(0x10, 0xCA);
  295. RTV_REG_MAP_SEL(FEC_PAGE);
  296. FEC_F8 = RTV_REG_GET(0xF8);
  297. #ifdef RTV_FORCE_INSERT_SYNC_BYTE
  298. FEC_F8 |= 0x02;
  299. #endif
  300. FEC_FB = RTV_REG_GET(0xFB);
  301. RTV_REG_SET(0xFB, (FEC_FB | 0x01));
  302. RTV_REG_SET(0xF8, (FEC_F8 | 0x80));
  303. }
  304. static INLINE void rtv_SoftReset(void)
  305. {
  306. U8 OFDM_10, FEC_F8, FEC_FB;
  307. RTV_REG_MAP_SEL(OFDM_PAGE);
  308. OFDM_10 = RTV_REG_GET(0x10);
  309. RTV_REG_SET(0x10, (OFDM_10 & 0xFE));
  310. RTV_REG_SET(0x10, (OFDM_10 | 0x01));
  311. RTV_REG_MAP_SEL(FEC_PAGE);
  312. FEC_F8 = RTV_REG_GET(0xF8);
  313. #ifdef RTV_FORCE_INSERT_SYNC_BYTE
  314. FEC_F8 |= 0x02;
  315. #endif
  316. FEC_FB = RTV_REG_GET(0xFB);
  317. RTV_REG_SET(0xFB, (FEC_FB | 0x01));
  318. RTV_REG_SET(0xFB, (FEC_FB & 0xFE));
  319. RTV_REG_SET(0xF8, (FEC_F8 | 0x80));
  320. RTV_REG_SET(0xF8, (FEC_F8 & 0x7F));
  321. }
  322. static INLINE void rtv_SetupInterruptThreshold(UINT nThresholdSize)
  323. {
  324. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  325. UINT nMod;
  326. nMod = nThresholdSize % RTV_TSP_XFER_SIZE;
  327. if (nMod) /* next xfer align */
  328. nThresholdSize += (RTV_TSP_XFER_SIZE - nMod);
  329. RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
  330. RTV_REG_SET(0x23, nThresholdSize/188);
  331. /* Save for rtvTDMB_GetInterruptLevelSize() */
  332. g_nRtvInterruptLevelSize = nThresholdSize;
  333. #endif
  334. }
  335. /*=============================================================================
  336. *
  337. * T-DMB inline functions.
  338. *
  339. *============================================================================*/
  340. static INLINE void rtv_Disable_FIC(void)
  341. {
  342. RTV_REG_MAP_SEL(FEC_PAGE);
  343. RTV_REG_SET(0xB2, 0x80);
  344. }
  345. static INLINE void rtv_DisableFicTsifPath(void)
  346. {
  347. U8 i2c0;
  348. RTV_REG_MAP_SEL(FEC_PAGE);
  349. i2c0 = RTV_REG_GET(0x26);
  350. i2c0 |= 0x01;
  351. RTV_REG_SET(0x26, i2c0);
  352. }
  353. static INLINE void rtv_EnableFicTsifPath(void)
  354. {
  355. U8 i2c0;
  356. RTV_REG_MAP_SEL(FEC_PAGE);
  357. i2c0 = RTV_REG_GET(0x26);
  358. i2c0 &= ~0x01;
  359. RTV_REG_SET(0x26, i2c0);
  360. }
  361. static INLINE void rtv_DisableFicInterrupt(UINT nOpenedSubChNum)
  362. {
  363. #ifndef RTV_FIC_POLLING_MODE
  364. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  365. if (!nOpenedSubChNum) {
  366. RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
  367. g_bRtvIntrMaskReg |= SPI_INTR_BITS; /* for polling */
  368. RTV_REG_SET(0x24, g_bRtvIntrMaskReg); /* Disable interrupts. */
  369. /* To clear interrupt and data. */
  370. RTV_REG_SET(0x2A, 1);
  371. RTV_REG_SET(0x2A, 0);
  372. }
  373. #else
  374. RTV_REG_MAP_SEL(FEC_PAGE);
  375. RTV_REG_SET(0x17, 0xFF);
  376. #endif
  377. #endif /* #ifndef RTV_FIC_POLLING_MODE */
  378. }
  379. static INLINE void rtv_EnableFicInterrupt(UINT nOpenedSubChNum)
  380. {
  381. #ifndef RTV_FIC_POLLING_MODE
  382. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  383. #ifdef RTV_CIF_MODE_ENABLED
  384. UINT nThresholdSize = RTV_SPI_CIF_MODE_INTERRUPT_SIZE;
  385. #else
  386. UINT nThresholdSize = 384;
  387. #endif
  388. if (!nOpenedSubChNum) {
  389. rtv_SetupInterruptThreshold(nThresholdSize);
  390. RTV_REG_SET(0x2A, 1);
  391. RTV_REG_SET(0x2A, 0);
  392. g_bRtvIntrMaskReg &= ~(SPI_INTR_BITS);
  393. RTV_REG_SET(0x24, g_bRtvIntrMaskReg); /* Enable interrupts. */
  394. }
  395. #else
  396. RTV_REG_MAP_SEL(FEC_PAGE);
  397. RTV_REG_SET(0x17, 0xEF);
  398. #endif
  399. #endif /* #ifndef RTV_FIC_POLLING_MODE */
  400. }
  401. static INLINE void rtv_CloseFIC(UINT nOpenedSubChNum)
  402. {
  403. rtv_Disable_FIC();
  404. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  405. rtv_DisableFicInterrupt(nOpenedSubChNum);
  406. #elif defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  407. switch (g_nRtvFicOpenedStatePath) {
  408. case FIC_OPENED_PATH_I2C_IN_SCAN: /* No sub channel */
  409. case FIC_OPENED_PATH_I2C_IN_PLAY:
  410. //#ifndef RTV_FIC_POLLING_MODE
  411. RTV_REG_MAP_SEL(HOST_PAGE);
  412. RTV_REG_SET(0x1A, 0x08); /* GPD3 PAD disable */
  413. rtv_DisableFicInterrupt(nOpenedSubChNum); /* From I2C intr */
  414. //#endif
  415. break;
  416. case FIC_OPENED_PATH_TSIF_IN_SCAN: /* No sub channel */
  417. case FIC_OPENED_PATH_TSIF_IN_PLAY: /* Have sub channel */
  418. rtv_DisableFicTsifPath();
  419. break;
  420. case FIC_OPENED_PATH_NOT_USE_IN_PLAY:
  421. #if defined(RTV_FIC__SCAN_I2C__PLAY_NA)
  422. #ifndef RTV_FIC_POLLING_MODE
  423. rtv_DisableFicInterrupt(1);
  424. #endif
  425. #elif defined(RTV_FIC__SCAN_TSIF__PLAY_NA)
  426. rtv_DisableFicTsifPath();
  427. #endif
  428. break;
  429. default:
  430. break;
  431. }
  432. #endif
  433. }
  434. static INLINE void rtv_OpenFIC_SPI_Play(void)
  435. {
  436. RTV_REG_MAP_SEL(FEC_PAGE);
  437. RTV_REG_SET(0xB2, 0x04|N_DATA_LEN_BITVAL); /* out_en, hdr_on */
  438. }
  439. static INLINE void rtv_OpenFIC_SPI_Scan(void)
  440. {
  441. #ifdef RTV_FIC_POLLING_MODE
  442. rtv_DisablePadIntrrupt();
  443. #else
  444. rtv_EnablePadIntrrupt();
  445. #endif
  446. rtv_SetupInterruptThreshold(MTV319_FIC_BUF_SIZE);
  447. RTV_REG_SET(0x2A, 1);
  448. RTV_REG_SET(0x2A, 0);
  449. g_bRtvIntrMaskReg &= ~(SPI_INTR_BITS);
  450. RTV_REG_SET(0x24, g_bRtvIntrMaskReg); /* Enable interrupts. */
  451. RTV_REG_MAP_SEL(FEC_PAGE);
  452. RTV_REG_SET(0xB2, 0x00|N_DATA_LEN_BITVAL); /* out_en, no_hdr*/
  453. }
  454. #if defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE)
  455. static INLINE enum E_RTV_FIC_OPENED_PATH_TYPE rtv_OpenFIC_TSIF_Play(void)
  456. {
  457. enum E_RTV_FIC_OPENED_PATH_TYPE ePath = FIC_OPENED_PATH_NOT_USE_IN_PLAY;
  458. #if defined(RTV_FIC__SCAN_I2C__PLAY_I2C)\
  459. || defined(RTV_FIC__SCAN_TSIF__PLAY_I2C)
  460. rtv_DisableFicTsifPath(); /* For I2C path */
  461. #ifndef RTV_FIC_POLLING_MODE
  462. rtv_EnableFicInterrupt(1);
  463. #endif
  464. ePath = FIC_OPENED_PATH_I2C_IN_PLAY;
  465. #elif defined(RTV_FIC__SCAN_I2C__PLAY_TSIF)\
  466. || defined(RTV_FIC__SCAN_TSIF__PLAY_TSIF)
  467. rtv_EnableFicTsifPath();
  468. ePath = FIC_OPENED_PATH_TSIF_IN_PLAY;
  469. #elif defined(RTV_FIC__SCAN_I2C__PLAY_NA)
  470. ePath = FIC_OPENED_PATH_NOT_USE_IN_PLAY;
  471. #elif defined(RTV_FIC__SCAN_TSIF__PLAY_NA)
  472. rtv_DisableFicTsifPath();
  473. ePath = FIC_OPENED_PATH_NOT_USE_IN_PLAY;
  474. #else
  475. #error "Code not present"
  476. #endif
  477. RTV_REG_MAP_SEL(FEC_PAGE);
  478. RTV_REG_SET(0xB2, 0x04|N_DATA_LEN_BITVAL); /* out_en, hdr_on */
  479. return ePath;
  480. }
  481. static INLINE enum E_RTV_FIC_OPENED_PATH_TYPE rtv_OpenFIC_TSIF_Scan(void)
  482. {
  483. enum E_RTV_FIC_OPENED_PATH_TYPE ePath = FIC_OPENED_PATH_NOT_USE_IN_PLAY;
  484. #if defined(RTV_FIC__SCAN_I2C__PLAY_NA)\
  485. || defined(RTV_FIC__SCAN_I2C__PLAY_I2C)\
  486. || defined(RTV_FIC__SCAN_I2C__PLAY_TSIF)
  487. rtv_DisableFicTsifPath(); /* For I2C path */
  488. #ifndef RTV_FIC_POLLING_MODE
  489. RTV_REG_MAP_SEL(HOST_PAGE);
  490. RTV_REG_SET(0x1A, 0x00); /* GPD3 PAD enable */
  491. rtv_EnableFicInterrupt(1);
  492. #endif
  493. ePath = FIC_OPENED_PATH_I2C_IN_SCAN;
  494. #elif defined(RTV_FIC__SCAN_TSIF__PLAY_NA)\
  495. || defined(RTV_FIC__SCAN_TSIF__PLAY_I2C)\
  496. || defined(RTV_FIC__SCAN_TSIF__PLAY_TSIF)
  497. rtv_EnableFicTsifPath();
  498. ePath = FIC_OPENED_PATH_TSIF_IN_SCAN;
  499. #else
  500. #error "Code not present"
  501. #endif
  502. RTV_REG_MAP_SEL(FEC_PAGE);
  503. RTV_REG_SET(0xB2, 0x00|N_DATA_LEN_BITVAL); /* out_en, no_hdr*/
  504. return ePath;
  505. }
  506. #endif /* #if defined(RTV_IF_TSIF) || defined(RTV_IF_SPI_SLAVE) */
  507. static INLINE INT rtv_OpenFIC(enum E_TDMB_STATE eTdmbState)
  508. {
  509. switch (eTdmbState) {
  510. case TDMB_STATE_SCAN:
  511. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  512. rtv_OpenFIC_SPI_Scan();
  513. #else
  514. g_nRtvFicOpenedStatePath = rtv_OpenFIC_TSIF_Scan();
  515. #endif
  516. break;
  517. #ifdef RTV_FIC_CIFMODE_ENABLED
  518. case TDMB_STATE_PLAY:
  519. #if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
  520. rtv_OpenFIC_SPI_Play();
  521. #else
  522. g_nRtvFicOpenedStatePath = rtv_OpenFIC_TSIF_Play();
  523. #endif
  524. break;
  525. #endif
  526. default:
  527. return RTV_INVALID_FIC_OPEN_STATE;
  528. }
  529. return RTV_SUCCESS;
  530. }
  531. /*=============================================================================
  532. * External functions for RAONTV driver core.
  533. *============================================================================*/
  534. INT rtv_InitSystem(void);
  535. #ifdef __cplusplus
  536. }
  537. #endif
  538. #endif /* __MTV319_INTERNAL_H__ */