i2c-pasemi.c 11 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * SMBus host driver for PA Semi PWRficient
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/module.h>
  20. #include <linux/pci.h>
  21. #include <linux/kernel.h>
  22. #include <linux/stddef.h>
  23. #include <linux/sched.h>
  24. #include <linux/i2c.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include <linux/io.h>
  28. static struct pci_driver pasemi_smb_driver;
  29. struct pasemi_smbus {
  30. struct pci_dev *dev;
  31. struct i2c_adapter adapter;
  32. unsigned long base;
  33. int size;
  34. };
  35. /* Register offsets */
  36. #define REG_MTXFIFO 0x00
  37. #define REG_MRXFIFO 0x04
  38. #define REG_SMSTA 0x14
  39. #define REG_CTL 0x1c
  40. /* Register defs */
  41. #define MTXFIFO_READ 0x00000400
  42. #define MTXFIFO_STOP 0x00000200
  43. #define MTXFIFO_START 0x00000100
  44. #define MTXFIFO_DATA_M 0x000000ff
  45. #define MRXFIFO_EMPTY 0x00000100
  46. #define MRXFIFO_DATA_M 0x000000ff
  47. #define SMSTA_XEN 0x08000000
  48. #define SMSTA_MTN 0x00200000
  49. #define CTL_MRR 0x00000400
  50. #define CTL_MTR 0x00000200
  51. #define CTL_CLK_M 0x000000ff
  52. #define CLK_100K_DIV 84
  53. #define CLK_400K_DIV 21
  54. static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val)
  55. {
  56. dev_dbg(&smbus->dev->dev, "smbus write reg %lx val %08x\n",
  57. smbus->base + reg, val);
  58. outl(val, smbus->base + reg);
  59. }
  60. static inline int reg_read(struct pasemi_smbus *smbus, int reg)
  61. {
  62. int ret;
  63. ret = inl(smbus->base + reg);
  64. dev_dbg(&smbus->dev->dev, "smbus read reg %lx val %08x\n",
  65. smbus->base + reg, ret);
  66. return ret;
  67. }
  68. #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
  69. #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO)
  70. static void pasemi_smb_clear(struct pasemi_smbus *smbus)
  71. {
  72. unsigned int status;
  73. status = reg_read(smbus, REG_SMSTA);
  74. reg_write(smbus, REG_SMSTA, status);
  75. }
  76. static int pasemi_smb_waitready(struct pasemi_smbus *smbus)
  77. {
  78. int timeout = 10;
  79. unsigned int status;
  80. status = reg_read(smbus, REG_SMSTA);
  81. while (!(status & SMSTA_XEN) && timeout--) {
  82. msleep(1);
  83. status = reg_read(smbus, REG_SMSTA);
  84. }
  85. /* Got NACK? */
  86. if (status & SMSTA_MTN)
  87. return -ENXIO;
  88. if (timeout < 0) {
  89. dev_warn(&smbus->dev->dev, "Timeout, status 0x%08x\n", status);
  90. reg_write(smbus, REG_SMSTA, status);
  91. return -ETIME;
  92. }
  93. /* Clear XEN */
  94. reg_write(smbus, REG_SMSTA, SMSTA_XEN);
  95. return 0;
  96. }
  97. static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter,
  98. struct i2c_msg *msg, int stop)
  99. {
  100. struct pasemi_smbus *smbus = adapter->algo_data;
  101. int read, i, err;
  102. u32 rd;
  103. read = msg->flags & I2C_M_RD ? 1 : 0;
  104. TXFIFO_WR(smbus, MTXFIFO_START | (msg->addr << 1) | read);
  105. if (read) {
  106. TXFIFO_WR(smbus, msg->len | MTXFIFO_READ |
  107. (stop ? MTXFIFO_STOP : 0));
  108. err = pasemi_smb_waitready(smbus);
  109. if (err)
  110. goto reset_out;
  111. for (i = 0; i < msg->len; i++) {
  112. rd = RXFIFO_RD(smbus);
  113. if (rd & MRXFIFO_EMPTY) {
  114. err = -ENODATA;
  115. goto reset_out;
  116. }
  117. msg->buf[i] = rd & MRXFIFO_DATA_M;
  118. }
  119. } else {
  120. for (i = 0; i < msg->len - 1; i++)
  121. TXFIFO_WR(smbus, msg->buf[i]);
  122. TXFIFO_WR(smbus, msg->buf[msg->len-1] |
  123. (stop ? MTXFIFO_STOP : 0));
  124. }
  125. return 0;
  126. reset_out:
  127. reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
  128. (CLK_100K_DIV & CTL_CLK_M)));
  129. return err;
  130. }
  131. static int pasemi_i2c_xfer(struct i2c_adapter *adapter,
  132. struct i2c_msg *msgs, int num)
  133. {
  134. struct pasemi_smbus *smbus = adapter->algo_data;
  135. int ret, i;
  136. pasemi_smb_clear(smbus);
  137. ret = 0;
  138. for (i = 0; i < num && !ret; i++)
  139. ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1)));
  140. return ret ? ret : num;
  141. }
  142. static int pasemi_smb_xfer(struct i2c_adapter *adapter,
  143. u16 addr, unsigned short flags, char read_write, u8 command,
  144. int size, union i2c_smbus_data *data)
  145. {
  146. struct pasemi_smbus *smbus = adapter->algo_data;
  147. unsigned int rd;
  148. int read_flag, err;
  149. int len = 0, i;
  150. /* All our ops take 8-bit shifted addresses */
  151. addr <<= 1;
  152. read_flag = read_write == I2C_SMBUS_READ;
  153. pasemi_smb_clear(smbus);
  154. switch (size) {
  155. case I2C_SMBUS_QUICK:
  156. TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START |
  157. MTXFIFO_STOP);
  158. break;
  159. case I2C_SMBUS_BYTE:
  160. TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START);
  161. if (read_write)
  162. TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ);
  163. else
  164. TXFIFO_WR(smbus, MTXFIFO_STOP | command);
  165. break;
  166. case I2C_SMBUS_BYTE_DATA:
  167. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  168. TXFIFO_WR(smbus, command);
  169. if (read_write) {
  170. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  171. TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP);
  172. } else {
  173. TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte);
  174. }
  175. break;
  176. case I2C_SMBUS_WORD_DATA:
  177. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  178. TXFIFO_WR(smbus, command);
  179. if (read_write) {
  180. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  181. TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP);
  182. } else {
  183. TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
  184. TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8));
  185. }
  186. break;
  187. case I2C_SMBUS_BLOCK_DATA:
  188. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  189. TXFIFO_WR(smbus, command);
  190. if (read_write) {
  191. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  192. TXFIFO_WR(smbus, 1 | MTXFIFO_READ);
  193. rd = RXFIFO_RD(smbus);
  194. len = min_t(u8, (rd & MRXFIFO_DATA_M),
  195. I2C_SMBUS_BLOCK_MAX);
  196. TXFIFO_WR(smbus, len | MTXFIFO_READ |
  197. MTXFIFO_STOP);
  198. } else {
  199. len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX);
  200. TXFIFO_WR(smbus, len);
  201. for (i = 1; i < len; i++)
  202. TXFIFO_WR(smbus, data->block[i]);
  203. TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP);
  204. }
  205. break;
  206. case I2C_SMBUS_PROC_CALL:
  207. read_write = I2C_SMBUS_READ;
  208. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  209. TXFIFO_WR(smbus, command);
  210. TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
  211. TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M);
  212. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
  213. TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ);
  214. break;
  215. case I2C_SMBUS_BLOCK_PROC_CALL:
  216. len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1);
  217. read_write = I2C_SMBUS_READ;
  218. TXFIFO_WR(smbus, addr | MTXFIFO_START);
  219. TXFIFO_WR(smbus, command);
  220. TXFIFO_WR(smbus, len);
  221. for (i = 1; i <= len; i++)
  222. TXFIFO_WR(smbus, data->block[i]);
  223. TXFIFO_WR(smbus, addr | I2C_SMBUS_READ);
  224. TXFIFO_WR(smbus, MTXFIFO_READ | 1);
  225. rd = RXFIFO_RD(smbus);
  226. len = min_t(u8, (rd & MRXFIFO_DATA_M),
  227. I2C_SMBUS_BLOCK_MAX - len);
  228. TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP);
  229. break;
  230. default:
  231. dev_warn(&adapter->dev, "Unsupported transaction %d\n", size);
  232. return -EINVAL;
  233. }
  234. err = pasemi_smb_waitready(smbus);
  235. if (err)
  236. goto reset_out;
  237. if (read_write == I2C_SMBUS_WRITE)
  238. return 0;
  239. switch (size) {
  240. case I2C_SMBUS_BYTE:
  241. case I2C_SMBUS_BYTE_DATA:
  242. rd = RXFIFO_RD(smbus);
  243. if (rd & MRXFIFO_EMPTY) {
  244. err = -ENODATA;
  245. goto reset_out;
  246. }
  247. data->byte = rd & MRXFIFO_DATA_M;
  248. break;
  249. case I2C_SMBUS_WORD_DATA:
  250. case I2C_SMBUS_PROC_CALL:
  251. rd = RXFIFO_RD(smbus);
  252. if (rd & MRXFIFO_EMPTY) {
  253. err = -ENODATA;
  254. goto reset_out;
  255. }
  256. data->word = rd & MRXFIFO_DATA_M;
  257. rd = RXFIFO_RD(smbus);
  258. if (rd & MRXFIFO_EMPTY) {
  259. err = -ENODATA;
  260. goto reset_out;
  261. }
  262. data->word |= (rd & MRXFIFO_DATA_M) << 8;
  263. break;
  264. case I2C_SMBUS_BLOCK_DATA:
  265. case I2C_SMBUS_BLOCK_PROC_CALL:
  266. data->block[0] = len;
  267. for (i = 1; i <= len; i ++) {
  268. rd = RXFIFO_RD(smbus);
  269. if (rd & MRXFIFO_EMPTY) {
  270. err = -ENODATA;
  271. goto reset_out;
  272. }
  273. data->block[i] = rd & MRXFIFO_DATA_M;
  274. }
  275. break;
  276. }
  277. return 0;
  278. reset_out:
  279. reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
  280. (CLK_100K_DIV & CTL_CLK_M)));
  281. return err;
  282. }
  283. static u32 pasemi_smb_func(struct i2c_adapter *adapter)
  284. {
  285. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  286. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  287. I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
  288. I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C;
  289. }
  290. static const struct i2c_algorithm smbus_algorithm = {
  291. .master_xfer = pasemi_i2c_xfer,
  292. .smbus_xfer = pasemi_smb_xfer,
  293. .functionality = pasemi_smb_func,
  294. };
  295. static int __devinit pasemi_smb_probe(struct pci_dev *dev,
  296. const struct pci_device_id *id)
  297. {
  298. struct pasemi_smbus *smbus;
  299. int error;
  300. if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
  301. return -ENODEV;
  302. smbus = kzalloc(sizeof(struct pasemi_smbus), GFP_KERNEL);
  303. if (!smbus)
  304. return -ENOMEM;
  305. smbus->dev = dev;
  306. smbus->base = pci_resource_start(dev, 0);
  307. smbus->size = pci_resource_len(dev, 0);
  308. if (!request_region(smbus->base, smbus->size,
  309. pasemi_smb_driver.name)) {
  310. error = -EBUSY;
  311. goto out_kfree;
  312. }
  313. smbus->adapter.owner = THIS_MODULE;
  314. snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
  315. "PA Semi SMBus adapter at 0x%lx", smbus->base);
  316. smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  317. smbus->adapter.algo = &smbus_algorithm;
  318. smbus->adapter.algo_data = smbus;
  319. smbus->adapter.nr = PCI_FUNC(dev->devfn);
  320. /* set up the sysfs linkage to our parent device */
  321. smbus->adapter.dev.parent = &dev->dev;
  322. reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
  323. (CLK_100K_DIV & CTL_CLK_M)));
  324. error = i2c_add_numbered_adapter(&smbus->adapter);
  325. if (error)
  326. goto out_release_region;
  327. pci_set_drvdata(dev, smbus);
  328. return 0;
  329. out_release_region:
  330. release_region(smbus->base, smbus->size);
  331. out_kfree:
  332. kfree(smbus);
  333. return error;
  334. }
  335. static void __devexit pasemi_smb_remove(struct pci_dev *dev)
  336. {
  337. struct pasemi_smbus *smbus = pci_get_drvdata(dev);
  338. i2c_del_adapter(&smbus->adapter);
  339. release_region(smbus->base, smbus->size);
  340. kfree(smbus);
  341. }
  342. static DEFINE_PCI_DEVICE_TABLE(pasemi_smb_ids) = {
  343. { PCI_DEVICE(0x1959, 0xa003) },
  344. { 0, }
  345. };
  346. MODULE_DEVICE_TABLE(pci, pasemi_smb_ids);
  347. static struct pci_driver pasemi_smb_driver = {
  348. .name = "i2c-pasemi",
  349. .id_table = pasemi_smb_ids,
  350. .probe = pasemi_smb_probe,
  351. .remove = __devexit_p(pasemi_smb_remove),
  352. };
  353. static int __init pasemi_smb_init(void)
  354. {
  355. return pci_register_driver(&pasemi_smb_driver);
  356. }
  357. static void __exit pasemi_smb_exit(void)
  358. {
  359. pci_unregister_driver(&pasemi_smb_driver);
  360. }
  361. MODULE_LICENSE("GPL");
  362. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  363. MODULE_DESCRIPTION("PA Semi PWRficient SMBus driver");
  364. module_init(pasemi_smb_init);
  365. module_exit(pasemi_smb_exit);