msm_serial.h 4.4 KB

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  1. /*
  2. * Copyright (C) 2007 Google, Inc.
  3. * Author: Robert Love <rlove@google.com>
  4. * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
  5. *
  6. * This software is licensed under the terms of the GNU General Public
  7. * License version 2, as published by the Free Software Foundation, and
  8. * may be copied, distributed, and modified under those terms.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
  16. #define __DRIVERS_SERIAL_MSM_SERIAL_H
  17. #define UART_MR1 0x0000
  18. #define UART_MR1_AUTO_RFR_LEVEL0 0x3F
  19. #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
  20. #define UART_MR1_RX_RDY_CTL (1 << 7)
  21. #define UART_MR1_CTS_CTL (1 << 6)
  22. #define UART_MR2 0x0004
  23. #define UART_MR2_ERROR_MODE (1 << 6)
  24. #define UART_MR2_BITS_PER_CHAR 0x30
  25. #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
  26. #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
  27. #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
  28. #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
  29. #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
  30. #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
  31. #define UART_MR2_PARITY_MODE_NONE 0x0
  32. #define UART_MR2_PARITY_MODE_ODD 0x1
  33. #define UART_MR2_PARITY_MODE_EVEN 0x2
  34. #define UART_MR2_PARITY_MODE_SPACE 0x3
  35. #define UART_MR2_PARITY_MODE 0x3
  36. #define UART_CSR 0x0008
  37. #define UART_CSR_115200 0xFF
  38. #define UART_CSR_57600 0xEE
  39. #define UART_CSR_38400 0xDD
  40. #define UART_CSR_28800 0xCC
  41. #define UART_CSR_19200 0xBB
  42. #define UART_CSR_14400 0xAA
  43. #define UART_CSR_9600 0x99
  44. #define UART_CSR_7200 0x88
  45. #define UART_CSR_4800 0x77
  46. #define UART_CSR_2400 0x55
  47. #define UART_CSR_1200 0x44
  48. #define UART_CSR_600 0x33
  49. #define UART_CSR_300 0x22
  50. #define UART_CSR_150 0x11
  51. #define UART_CSR_75 0x00
  52. #define UART_TF 0x000C
  53. #define UARTDM_TF 0x0070
  54. #define UART_CR 0x0010
  55. #define UART_CR_CMD_NULL (0 << 4)
  56. #define UART_CR_CMD_RESET_RX (1 << 4)
  57. #define UART_CR_CMD_RESET_TX (2 << 4)
  58. #define UART_CR_CMD_RESET_ERR (3 << 4)
  59. #define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
  60. #define UART_CR_CMD_START_BREAK (5 << 4)
  61. #define UART_CR_CMD_STOP_BREAK (6 << 4)
  62. #define UART_CR_CMD_RESET_CTS (7 << 4)
  63. #define UART_CR_CMD_RESET_STALE_INT (8 << 4)
  64. #define UART_CR_CMD_PACKET_MODE (9 << 4)
  65. #define UART_CR_CMD_MODE_RESET (12 << 4)
  66. #define UART_CR_CMD_SET_RFR (13 << 4)
  67. #define UART_CR_CMD_RESET_RFR (14 << 4)
  68. #define UART_CR_CMD_PROTECTION_EN (16 << 4)
  69. #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4)
  70. #define UART_CR_TX_DISABLE (1 << 3)
  71. #define UART_CR_TX_ENABLE (1 << 2)
  72. #define UART_CR_RX_DISABLE (1 << 1)
  73. #define UART_CR_RX_ENABLE (1 << 0)
  74. #define UART_IMR 0x0014
  75. #define UART_IMR_TXLEV (1 << 0)
  76. #define UART_IMR_RXSTALE (1 << 3)
  77. #define UART_IMR_RXLEV (1 << 4)
  78. #define UART_IMR_DELTA_CTS (1 << 5)
  79. #define UART_IMR_CURRENT_CTS (1 << 6)
  80. #define UART_IPR_RXSTALE_LAST 0x20
  81. #define UART_IPR_STALE_LSB 0x1F
  82. #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
  83. #define UART_IPR 0x0018
  84. #define UART_TFWR 0x001C
  85. #define UART_RFWR 0x0020
  86. #define UART_HCR 0x0024
  87. #define UART_MREG 0x0028
  88. #define UART_NREG 0x002C
  89. #define UART_DREG 0x0030
  90. #define UART_MNDREG 0x0034
  91. #define UART_IRDA 0x0038
  92. #define UART_SIM_CFG 0x003c
  93. #define UART_SIM_CFG_UIM_TX_MODE (1 << 17)
  94. #define UART_SIM_CFG_UIM_RX_MODE (1 << 16)
  95. #define UART_SIM_CFG_STOP_BIT_LEN_N(n) ((n) << 8)
  96. #define UART_SIM_CFG_SIM_CLK_ON (1 << 7)
  97. #define UART_SIM_CFG_SIM_CLK_TD8_SEL (1 << 6)
  98. #define UART_SIM_CFG_SIM_CLK_STOP_HIGH (1 << 5)
  99. #define UART_SIM_CFG_MASK_RX (1 << 3)
  100. #define UART_SIM_CFG_SIM_SEL (1 << 0)
  101. #define UART_MISR_MODE 0x0040
  102. #define UART_MISR_RESET 0x0044
  103. #define UART_MISR_EXPORT 0x0048
  104. #define UART_MISR_VAL 0x004C
  105. #define UART_TEST_CTRL 0x0050
  106. #define UART_SR 0x0008
  107. #define UART_SR_HUNT_CHAR (1 << 7)
  108. #define UART_SR_RX_BREAK (1 << 6)
  109. #define UART_SR_PAR_FRAME_ERR (1 << 5)
  110. #define UART_SR_OVERRUN (1 << 4)
  111. #define UART_SR_TX_EMPTY (1 << 3)
  112. #define UART_SR_TX_READY (1 << 2)
  113. #define UART_SR_RX_FULL (1 << 1)
  114. #define UART_SR_RX_READY (1 << 0)
  115. #define UART_RF 0x000C
  116. #define UARTDM_RF 0x0070
  117. #define UART_MISR 0x0010
  118. #define UART_ISR 0x0014
  119. #define UART_ISR_TX_READY (1 << 7)
  120. #define GSBI_CONTROL 0x0
  121. #define GSBI_PROTOCOL_CODE 0x30
  122. #define GSBI_PROTOCOL_UART 0x40
  123. #define GSBI_PROTOCOL_IDLE 0x0
  124. #define UARTDM_DMRX 0x34
  125. #define UARTDM_NCF_TX 0x40
  126. #define UARTDM_RX_TOTAL_SNAP 0x38
  127. #endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */