ssp_iio_ring.c 45 KB

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  1. /*
  2. * Copyright (C) 2011, Samsung Electronics Co. Ltd. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. */
  15. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/slab.h>
  19. #include <linux/i2c.h>
  20. #include <linux/err.h>
  21. #include <linux/delay.h>
  22. #include <linux/sysfs.h>
  23. #include <linux/jiffies.h>
  24. #include <linux/irq.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/kfifo.h>
  27. #include <linux/poll.h>
  28. #include <linux/miscdevice.h>
  29. #include "ssp.h"
  30. #include "../../staging/iio/iio.h"
  31. #include "../../staging/iio/kfifo_buf.h"
  32. #include "../../staging/iio/trigger_consumer.h"
  33. #include "../../staging/iio/sysfs.h"
  34. //#include "inv_mpu_iio.h"
  35. #if 0
  36. static u8 fifo_data[HARDWARE_FIFO_SIZE + HEADERED_Q_BYTES];
  37. static int inv_process_batchmode(struct inv_mpu_state *st, bool insert);
  38. static int inv_push_marker_to_buffer(struct inv_mpu_state *st, u16 hdr)
  39. {
  40. struct iio_dev *indio_dev = iio_priv_to_dev(st);
  41. u8 buf[IIO_BUFFER_BYTES];
  42. memcpy(buf, &hdr, sizeof(hdr));
  43. iio_push_to_buffer(indio_dev->buffer, buf, 0);
  44. return 0;
  45. }
  46. static int inv_push_8bytes_buffer(struct inv_mpu_state *st, u16 hdr,
  47. u64 t, s16 *d)
  48. {
  49. struct iio_dev *indio_dev = iio_priv_to_dev(st);
  50. u8 buf[IIO_BUFFER_BYTES];
  51. int i;
  52. memcpy(buf, &hdr, sizeof(hdr));
  53. for (i = 0; i < 3; i++)
  54. memcpy(&buf[2 + i * 2], &d[i], sizeof(d[i]));
  55. iio_push_to_buffer(indio_dev->buffer, buf, 0);
  56. memcpy(buf, &t, sizeof(t));
  57. iio_push_to_buffer(indio_dev->buffer, buf, 0);
  58. return 0;
  59. }
  60. static int inv_push_16bytes_buffer(struct inv_mpu_state *st, u16 hdr, u64 t,
  61. int *q)
  62. {
  63. struct iio_dev *indio_dev = iio_priv_to_dev(st);
  64. u8 buf[IIO_BUFFER_BYTES];
  65. int i;
  66. memcpy(buf, &hdr, sizeof(hdr));
  67. memcpy(buf + 4, &q[0], sizeof(q[0]));
  68. iio_push_to_buffer(indio_dev->buffer, buf, 0);
  69. for (i = 0; i < 2; i++)
  70. memcpy(buf + 4 * i, &q[i + 1], sizeof(q[i]));
  71. iio_push_to_buffer(indio_dev->buffer, buf, 0);
  72. memcpy(buf, &t, sizeof(t));
  73. iio_push_to_buffer(indio_dev->buffer, buf, 0);
  74. return 0;
  75. }
  76. static int inv_send_pressure_data(struct inv_mpu_state *st)
  77. {
  78. short sen[3];
  79. struct inv_chip_config_s *conf;
  80. struct inv_mpu_slave *slave;
  81. u64 curr_ts;
  82. conf = &st->chip_config;
  83. slave = st->slave_pressure;
  84. if (!st->sensor[SENSOR_PRESSURE].on)
  85. return 0;
  86. if (conf->dmp_on && conf->dmp_event_int_on)
  87. return 0;
  88. if (!conf->normal_pressure_measure) {
  89. conf->normal_pressure_measure = 1;
  90. return 0;
  91. }
  92. curr_ts = get_time_ns();
  93. if (curr_ts - slave->prev_ts > slave->min_read_time) {
  94. slave->read_data(st, sen);
  95. inv_push_8bytes_buffer(st, PRESSURE_HDR, st->last_ts, sen);
  96. slave->prev_ts = curr_ts;
  97. }
  98. return 0;
  99. }
  100. static int inv_send_compass_data(struct inv_mpu_state *st)
  101. {
  102. short sen[3];
  103. struct inv_chip_config_s *conf;
  104. struct inv_mpu_slave *slave;
  105. u64 curr_ts;
  106. conf = &st->chip_config;
  107. slave = st->slave_compass;
  108. if (!st->sensor[SENSOR_COMPASS].on)
  109. return 0;
  110. if (conf->dmp_on && conf->dmp_event_int_on)
  111. return 0;
  112. if (!conf->normal_compass_measure) {
  113. conf->normal_compass_measure = 1;
  114. return 0;
  115. }
  116. curr_ts = get_time_ns();
  117. if (curr_ts - slave->prev_ts > slave->min_read_time) {
  118. slave->read_data(st, sen);
  119. inv_push_8bytes_buffer(st, COMPASS_HDR, st->last_ts, sen);
  120. slave->prev_ts = curr_ts;
  121. }
  122. return 0;
  123. }
  124. static void process_step_only_batch(struct inv_mpu_state *st)
  125. {
  126. int target_bytes, tmp, r;
  127. u8 *dptr, *d;
  128. u16 hdr;
  129. s16 sen[3];
  130. u64 t;
  131. d = fifo_data;
  132. dptr = d;
  133. if (st->fifo_count == 0)
  134. return;
  135. target_bytes = st->fifo_count;
  136. while (target_bytes > 0) {
  137. if (target_bytes < MAX_READ_SIZE)
  138. tmp = target_bytes;
  139. else
  140. tmp = MAX_READ_SIZE;
  141. r = inv_i2c_read(st, st->reg.fifo_r_w, tmp, dptr);
  142. if (r < 0)
  143. return;
  144. dptr += tmp;
  145. target_bytes -= tmp;
  146. }
  147. dptr = d;
  148. target_bytes = st->fifo_count;
  149. while (dptr - d <= target_bytes - HEADERED_NORMAL_BYTES) {
  150. hdr = (u16)be16_to_cpup((__be16 *)(dptr));
  151. switch (hdr & (~1)) {
  152. case STEP_DETECTOR_HDR:
  153. tmp = (int)be32_to_cpup((__be32 *)(dptr + 4));
  154. t = st->step_detector_base_ts +
  155. (u64)tmp * 5 * NSEC_PER_MSEC;
  156. sen[0] = sen[1] = sen[2] = 0;
  157. inv_push_8bytes_buffer(st, hdr, t, sen);
  158. break;
  159. default:
  160. break;
  161. }
  162. dptr += HEADERED_NORMAL_BYTES;
  163. }
  164. return;
  165. }
  166. static int inv_batchmode_calc(struct inv_mpu_state *st)
  167. {
  168. int b, c, num_rate, rate;
  169. int i, j, timeout, num_sensor_on, timeout_count;
  170. bool int_on;
  171. num_sensor_on = 0;
  172. num_rate = 0;
  173. rate = 0;
  174. for (i = 0; i < SENSOR_NUM_MAX; i++) {
  175. if (st->sensor[i].on) {
  176. if (i != SENSOR_STEP) {
  177. if (num_rate == 0) {
  178. rate = st->sensor[i].rate;
  179. num_rate++;
  180. } else if (rate != st->sensor[i].rate) {
  181. num_rate++;
  182. }
  183. num_sensor_on++;
  184. }
  185. }
  186. }
  187. if ((num_sensor_on == 0) && st->sensor[SENSOR_STEP].on) {
  188. /* in step only batchmode, counter is fixed */
  189. st->batch.counter = FIFO_SIZE / 8;
  190. st->batch.step_only = true;
  191. st->batch.on = true;
  192. return 0;
  193. } else if (num_sensor_on == 0) {
  194. return 0;
  195. }
  196. b = st->batch.timeout * st->bytes_per_sec;
  197. if ((b > (FIFO_SIZE * ONE_K_HZ)) && (!st->batch.overflow_on))
  198. timeout = FIFO_SIZE * ONE_K_HZ / st->bytes_per_sec;
  199. else
  200. timeout = st->batch.timeout;
  201. /* 5 ms per count */
  202. timeout_count = timeout / 5;
  203. if (num_rate == 1) {
  204. c = timeout * rate / ONE_K_HZ;
  205. } else {
  206. c = 0;
  207. for (i = 1; i <= timeout_count; i++) {
  208. int_on = false;
  209. for (j = 0; j < SENSOR_NUM_MAX; j++) {
  210. if (st->sensor[j].on) {
  211. if ((i % st->sensor[j].counter) == 0)
  212. int_on = true;
  213. }
  214. }
  215. if (int_on)
  216. c++;
  217. }
  218. }
  219. st->batch.counter = c;
  220. st->batch.on = true;
  221. return 0;
  222. }
  223. int inv_batchmode_setup(struct inv_mpu_state *st)
  224. {
  225. int r;
  226. r = inv_write_2bytes(st, KEY_BM_NUMWORD_TOFILL, 0);
  227. if (r)
  228. return r;
  229. r = inv_write_2bytes(st, KEY_BM_BATCH_CNTR, 0);
  230. if (r)
  231. return r;
  232. if (st->chip_config.dmp_on && (st->batch.timeout > 0) &&
  233. (st->chip_config.dmp_event_int_on == 0)) {
  234. r = inv_batchmode_calc(st);
  235. if (r)
  236. return r;
  237. }
  238. if (st->batch.on) {
  239. r = inv_write_2bytes(st, KEY_BM_BATCH_THLD, st->batch.counter);
  240. if (r)
  241. return r;
  242. }
  243. r = inv_write_2bytes(st, KEY_BM_ENABLE, st->batch.on);
  244. return r;
  245. }
  246. /**
  247. * reset_fifo_mpu3050() - Reset FIFO related registers
  248. * @indio_dev: Device driver instance.
  249. */
  250. static int reset_fifo_mpu3050(struct iio_dev *indio_dev)
  251. {
  252. struct inv_reg_map_s *reg;
  253. int result;
  254. u8 val, user_ctrl;
  255. struct inv_mpu_state *st = iio_priv(indio_dev);
  256. reg = &st->reg;
  257. /* disable interrupt */
  258. result = inv_i2c_single_write(st, reg->int_enable,
  259. st->plat_data.int_config);
  260. if (result)
  261. return result;
  262. /* disable the sensor output to FIFO */
  263. result = inv_i2c_single_write(st, reg->fifo_en, 0);
  264. if (result)
  265. goto reset_fifo_fail;
  266. result = inv_i2c_read(st, reg->user_ctrl, 1, &user_ctrl);
  267. if (result)
  268. goto reset_fifo_fail;
  269. /* disable fifo reading */
  270. user_ctrl &= ~BIT_FIFO_EN;
  271. st->chip_config.has_footer = 0;
  272. /* reset fifo */
  273. val = (BIT_3050_FIFO_RST | user_ctrl);
  274. result = inv_i2c_single_write(st, reg->user_ctrl, val);
  275. if (result)
  276. goto reset_fifo_fail;
  277. if (st->chip_config.dmp_on) {
  278. /* enable interrupt when DMP is done */
  279. result = inv_i2c_single_write(st, reg->int_enable,
  280. st->plat_data.int_config | BIT_DMP_INT_EN);
  281. if (result)
  282. return result;
  283. result = inv_i2c_single_write(st, reg->user_ctrl,
  284. BIT_FIFO_EN|user_ctrl);
  285. if (result)
  286. return result;
  287. } else {
  288. /* enable interrupt */
  289. if (st->sensor[SENSOR_ACCEL].on ||
  290. st->sensor[SENSOR_GYRO].on) {
  291. result = inv_i2c_single_write(st, reg->int_enable,
  292. st->plat_data.int_config | BIT_DATA_RDY_EN);
  293. if (result)
  294. return result;
  295. }
  296. /* enable FIFO reading and I2C master interface*/
  297. result = inv_i2c_single_write(st, reg->user_ctrl,
  298. BIT_FIFO_EN | user_ctrl);
  299. if (result)
  300. return result;
  301. /* enable sensor output to FIFO and FIFO footer*/
  302. val = 1;
  303. if (st->sensor[SENSOR_ACCEL].on)
  304. val |= BITS_3050_ACCEL_OUT;
  305. if (st->sensor[SENSOR_GYRO].on)
  306. val |= BITS_GYRO_OUT;
  307. result = inv_i2c_single_write(st, reg->fifo_en, val);
  308. if (result)
  309. return result;
  310. }
  311. return 0;
  312. reset_fifo_fail:
  313. if (st->chip_config.dmp_on)
  314. val = BIT_DMP_INT_EN;
  315. else
  316. val = BIT_DATA_RDY_EN;
  317. inv_i2c_single_write(st, reg->int_enable,
  318. st->plat_data.int_config | val);
  319. pr_err("reset fifo failed\n");
  320. return result;
  321. }
  322. /*
  323. * inv_set_lpf() - set low pass filer based on fifo rate.
  324. */
  325. static int inv_set_lpf(struct inv_mpu_state *st, int rate)
  326. {
  327. const short hz[] = {188, 98, 42, 20, 10, 5};
  328. const int d[] = {INV_FILTER_188HZ, INV_FILTER_98HZ,
  329. INV_FILTER_42HZ, INV_FILTER_20HZ,
  330. INV_FILTER_10HZ, INV_FILTER_5HZ};
  331. int i, h, data, result;
  332. struct inv_reg_map_s *reg;
  333. reg = &st->reg;
  334. h = (rate >> 1);
  335. i = 0;
  336. while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
  337. i++;
  338. data = d[i];
  339. if (INV_MPU3050 == st->chip_type) {
  340. if (st->slave_accel != NULL) {
  341. result = st->slave_accel->set_lpf(st, rate);
  342. if (result)
  343. return result;
  344. }
  345. result = inv_i2c_single_write(st, reg->lpf, data |
  346. (st->chip_config.fsr << GYRO_CONFIG_FSR_SHIFT));
  347. } else {
  348. result = inv_i2c_single_write(st, reg->lpf, data);
  349. }
  350. if (result)
  351. return result;
  352. st->chip_config.lpf = data;
  353. return 0;
  354. }
  355. /*
  356. * set_fifo_rate_reg() - Set fifo rate in hardware register
  357. */
  358. static int set_fifo_rate_reg(struct inv_mpu_state *st)
  359. {
  360. u8 data;
  361. u16 fifo_rate;
  362. int result;
  363. struct inv_reg_map_s *reg;
  364. reg = &st->reg;
  365. fifo_rate = st->chip_config.new_fifo_rate;
  366. data = ONE_K_HZ / fifo_rate - 1;
  367. result = inv_i2c_single_write(st, reg->sample_rate_div, data);
  368. if (result)
  369. return result;
  370. result = inv_set_lpf(st, fifo_rate);
  371. if (result)
  372. return result;
  373. /* wait for the sampling rate change to stabilize */
  374. mdelay(INV_MPU_SAMPLE_RATE_CHANGE_STABLE);
  375. st->chip_config.fifo_rate = fifo_rate;
  376. return 0;
  377. }
  378. /*
  379. * inv_lpa_mode() - store current low power mode settings
  380. */
  381. static int inv_lpa_mode(struct inv_mpu_state *st, int lpa_mode)
  382. {
  383. unsigned long result;
  384. u8 d;
  385. struct inv_reg_map_s *reg;
  386. reg = &st->reg;
  387. result = inv_i2c_read(st, reg->pwr_mgmt_1, 1, &d);
  388. if (result)
  389. return result;
  390. if (lpa_mode)
  391. d |= BIT_CYCLE;
  392. else
  393. d &= ~BIT_CYCLE;
  394. result = inv_i2c_single_write(st, reg->pwr_mgmt_1, d);
  395. if (result)
  396. return result;
  397. if (INV_MPU6500 == st->chip_type) {
  398. d = BIT_FIFO_SIZE_1K;
  399. if (lpa_mode)
  400. d |= BIT_ACCEL_FCHOCIE_B;
  401. result = inv_i2c_single_write(st, REG_6500_ACCEL_CONFIG2, d);
  402. if (result)
  403. return result;
  404. }
  405. return 0;
  406. }
  407. static int inv_set_master_delay(struct inv_mpu_state *st)
  408. {
  409. int d, result, rate;
  410. u8 delay;
  411. if ((!st->sensor[SENSOR_COMPASS].on) &&
  412. (!st->sensor[SENSOR_PRESSURE].on))
  413. return 0;
  414. delay = 0;
  415. d = 0;
  416. if (st->sensor[SENSOR_COMPASS].on) {
  417. switch (st->plat_data.sec_slave_id) {
  418. case COMPASS_ID_AK8975:
  419. case COMPASS_ID_AK8972:
  420. case COMPASS_ID_AK8963:
  421. delay = (BIT_SLV0_DLY_EN | BIT_SLV1_DLY_EN);
  422. break;
  423. case COMPASS_ID_MLX90399:
  424. delay = (BIT_SLV0_DLY_EN |
  425. BIT_SLV1_DLY_EN |
  426. BIT_SLV2_DLY_EN |
  427. BIT_SLV3_DLY_EN);
  428. break;
  429. default:
  430. return -EINVAL;
  431. }
  432. d = max(d, st->slave_compass->rate_scale);
  433. }
  434. if (st->sensor[SENSOR_PRESSURE].on) {
  435. /* read fake data when compass is disabled for DMP read */
  436. if (!st->sensor[SENSOR_COMPASS].on)
  437. delay |= BIT_SLV0_DLY_EN;
  438. switch (st->plat_data.aux_slave_id) {
  439. case PRESSURE_ID_BMP280:
  440. delay |= (BIT_SLV2_DLY_EN | BIT_SLV3_DLY_EN);
  441. break;
  442. default:
  443. return -EINVAL;
  444. }
  445. d = max(d, st->slave_pressure->rate_scale);
  446. }
  447. result = inv_i2c_single_write(st, REG_I2C_MST_DELAY_CTRL, delay);
  448. if (result)
  449. return result;
  450. d = d * st->chip_config.fifo_rate / ONE_K_HZ;
  451. if (st->chip_config.dmp_on) {
  452. rate = 0;
  453. if (st->sensor[SENSOR_PRESSURE].on)
  454. rate = max(rate, st->sensor[SENSOR_PRESSURE].rate);
  455. if (st->sensor[SENSOR_COMPASS].on)
  456. rate = max(rate, st->sensor[SENSOR_COMPASS].rate);
  457. if (rate == 0)
  458. return -EINVAL;
  459. d = max(d, st->chip_config.fifo_rate / rate);
  460. }
  461. if (d > 0)
  462. d -= 1;
  463. if (d > 0x1F)
  464. d = 0x1F;
  465. /* I2C_MST_DLY is set to slow down secondary I2C */
  466. return inv_i2c_single_write(st, REG_I2C_SLV4_CTRL, d);
  467. }
  468. /*
  469. * reset_fifo_itg() - Reset FIFO related registers.
  470. */
  471. static int reset_fifo_itg(struct iio_dev *indio_dev)
  472. {
  473. struct inv_reg_map_s *reg;
  474. int result, i;
  475. u8 val, int_word;
  476. struct inv_mpu_state *st = iio_priv(indio_dev);
  477. reg = &st->reg;
  478. if (st->chip_config.lpa_mode) {
  479. result = inv_lpa_mode(st, 0);
  480. if (result) {
  481. pr_err("reset lpa mode failed\n");
  482. return result;
  483. }
  484. }
  485. /* disable interrupt */
  486. result = inv_i2c_single_write(st, reg->int_enable, 0);
  487. if (result) {
  488. pr_err("int_enable write failed\n");
  489. return result;
  490. }
  491. /* disable the sensor output to FIFO */
  492. result = inv_i2c_single_write(st, reg->fifo_en, 0);
  493. if (result)
  494. goto reset_fifo_fail;
  495. /* disable fifo reading */
  496. result = inv_i2c_single_write(st, reg->user_ctrl, 0);
  497. if (result)
  498. goto reset_fifo_fail;
  499. int_word = 0;
  500. /* MPU6500's BIT_6500_WOM_EN is the same as BIT_MOT_EN */
  501. if (st->mot_int.mot_on)
  502. int_word |= BIT_MOT_EN;
  503. if (st->chip_config.dmp_on) {
  504. val = (BIT_FIFO_RST | BIT_DMP_RST);
  505. result = inv_i2c_single_write(st, reg->user_ctrl, val);
  506. if (result)
  507. goto reset_fifo_fail;
  508. if (st->chip_config.dmp_int_on) {
  509. int_word |= BIT_DMP_INT_EN;
  510. result = inv_i2c_single_write(st, reg->int_enable,
  511. int_word);
  512. if (result)
  513. return result;
  514. }
  515. val = (BIT_DMP_EN | BIT_FIFO_EN);
  516. if ((st->sensor[SENSOR_COMPASS].on ||
  517. st->sensor[SENSOR_PRESSURE].on) &&
  518. (!st->chip_config.dmp_event_int_on))
  519. val |= BIT_I2C_MST_EN;
  520. result = inv_i2c_single_write(st, reg->user_ctrl, val);
  521. if (result)
  522. goto reset_fifo_fail;
  523. } else {
  524. /* reset FIFO and possibly reset I2C*/
  525. val = BIT_FIFO_RST;
  526. result = inv_i2c_single_write(st, reg->user_ctrl, val);
  527. if (result)
  528. goto reset_fifo_fail;
  529. /* enable interrupt */
  530. if (st->sensor[SENSOR_ACCEL].on ||
  531. st->sensor[SENSOR_GYRO].on ||
  532. st->sensor[SENSOR_COMPASS].on ||
  533. st->sensor[SENSOR_PRESSURE].on)
  534. int_word |= BIT_DATA_RDY_EN;
  535. result = inv_i2c_single_write(st, reg->int_enable, int_word);
  536. if (result)
  537. return result;
  538. /* enable FIFO reading and I2C master interface*/
  539. val = BIT_FIFO_EN;
  540. if (st->sensor[SENSOR_COMPASS].on ||
  541. st->sensor[SENSOR_PRESSURE].on)
  542. val |= BIT_I2C_MST_EN;
  543. result = inv_i2c_single_write(st, reg->user_ctrl, val);
  544. if (result)
  545. goto reset_fifo_fail;
  546. /* enable sensor output to FIFO */
  547. val = 0;
  548. if (st->sensor[SENSOR_GYRO].on)
  549. val |= BITS_GYRO_OUT;
  550. if (st->sensor[SENSOR_ACCEL].on)
  551. val |= BIT_ACCEL_OUT;
  552. result = inv_i2c_single_write(st, reg->fifo_en, val);
  553. if (result)
  554. goto reset_fifo_fail;
  555. }
  556. result = inv_set_master_delay(st);
  557. if (result)
  558. goto reset_fifo_fail;
  559. st->last_ts = get_time_ns();
  560. st->prev_ts = st->last_ts;
  561. st->last_run_time = st->last_ts;
  562. if (st->sensor[SENSOR_COMPASS].on)
  563. st->slave_compass->prev_ts = st->last_ts;
  564. if (st->sensor[SENSOR_PRESSURE].on)
  565. st->slave_pressure->prev_ts = st->last_ts;
  566. st->dmp_interval = DMP_INTERVAL_INIT;
  567. st->ts_counter = 0;
  568. st->diff_accumulater = 0;
  569. st->dmp_interval_accum = 0;
  570. st->step_detector_base_ts = st->last_ts;
  571. st->chip_config.normal_compass_measure = 0;
  572. st->chip_config.normal_pressure_measure = 0;
  573. st->left_over_size = 0;
  574. st->batch.post_isr_run = false;
  575. for (i = 0; i < SENSOR_NUM_MAX; i++)
  576. st->sensor[i].ts = st->last_ts;
  577. result = inv_lpa_mode(st, st->chip_config.lpa_mode);
  578. if (result)
  579. goto reset_fifo_fail;
  580. return 0;
  581. reset_fifo_fail:
  582. if (st->chip_config.dmp_on)
  583. val = BIT_DMP_INT_EN;
  584. else
  585. val = BIT_DATA_RDY_EN;
  586. inv_i2c_single_write(st, reg->int_enable, val);
  587. pr_err("reset fifo failed\n");
  588. return result;
  589. }
  590. /**
  591. * inv_clear_kfifo() - clear time stamp fifo
  592. * @st: Device driver instance.
  593. */
  594. static void inv_clear_kfifo(struct inv_mpu_state *st)
  595. {
  596. unsigned long flags;
  597. spin_lock_irqsave(&st->time_stamp_lock, flags);
  598. kfifo_reset(&st->timestamps);
  599. spin_unlock_irqrestore(&st->time_stamp_lock, flags);
  600. }
  601. /*
  602. * inv_reset_fifo() - Reset FIFO related registers.
  603. */
  604. int inv_reset_fifo(struct iio_dev *indio_dev)
  605. {
  606. struct inv_mpu_state *st = iio_priv(indio_dev);
  607. inv_clear_kfifo(st);
  608. if (INV_MPU3050 == st->chip_type)
  609. return reset_fifo_mpu3050(indio_dev);
  610. else
  611. return reset_fifo_itg(indio_dev);
  612. }
  613. static int inv_send_gyro_data(struct inv_mpu_state *st, bool on)
  614. {
  615. u8 rn[] = {0xa3, 0xa3};
  616. u8 rf[] = {0xf4, 0x12};
  617. int result;
  618. u8 *r;
  619. if (on)
  620. r = rn;
  621. else
  622. r = rf;
  623. result = mem_w_key(KEY_CFG_OUT_GYRO, ARRAY_SIZE(rf), r);
  624. return result;
  625. }
  626. static int inv_send_accel_data(struct inv_mpu_state *st, bool on)
  627. {
  628. u8 rn[] = {0xa3, 0xa3};
  629. u8 rf[] = {0xf4, 0x12};
  630. int result;
  631. u8 *r;
  632. if (on)
  633. r = rn;
  634. else
  635. r = rf;
  636. result = mem_w_key(KEY_CFG_OUT_ACCL, ARRAY_SIZE(rf), r);
  637. return result;
  638. }
  639. static int inv_send_three_q_data(struct inv_mpu_state *st, bool on)
  640. {
  641. u8 rn[] = {0xa3, 0xa3};
  642. u8 rf[] = {0xf4, 0x13};
  643. int result;
  644. u8 *r;
  645. if (on)
  646. r = rn;
  647. else
  648. r = rf;
  649. result = mem_w_key(KEY_CFG_OUT_3QUAT, ARRAY_SIZE(rf), r);
  650. return result;
  651. }
  652. static int inv_send_six_q_data(struct inv_mpu_state *st, bool on)
  653. {
  654. u8 rn[] = {0xa3, 0xa3};
  655. u8 rf[] = {0xf4, 0x13};
  656. int result;
  657. u8 *r;
  658. if (on)
  659. r = rn;
  660. else
  661. r = rf;
  662. result = mem_w_key(KEY_CFG_OUT_6QUAT, ARRAY_SIZE(rf), r);
  663. return result;
  664. }
  665. static int inv_send_ped_q_data(struct inv_mpu_state *st, bool on)
  666. {
  667. u8 rn[] = {0xa3, 0xa3};
  668. u8 rf[] = {0xf4, 0x12};
  669. u8 *r;
  670. int result;
  671. if (on)
  672. r = rn;
  673. else
  674. r = rf;
  675. result = mem_w_key(KEY_CFG_OUT_PQUAT, ARRAY_SIZE(rn), r);
  676. return result;
  677. }
  678. static int inv_add_step_indicator(struct inv_mpu_state *st, bool on)
  679. {
  680. u8 rn[] = {0xf3, 0xf3};
  681. u8 rf[] = {0xf4, 0x03};
  682. int result;
  683. u8 *r;
  684. if (on)
  685. r = rn;
  686. else
  687. r = rf;
  688. result = mem_w_key(KEY_CFG_PEDSTEP_DET, ARRAY_SIZE(rn), r);
  689. return result;
  690. }
  691. static int inv_send_compass_dmp_data(struct inv_mpu_state *st, bool on)
  692. {
  693. u8 rn[] = {0xa3, 0xa3};
  694. u8 rf[] = {0xf4, 0x12};
  695. u8 *r;
  696. int result;
  697. if (on)
  698. r = rn;
  699. else
  700. r = rf;
  701. result = mem_w_key(KEY_CFG_OUT_CPASS, ARRAY_SIZE(rf), r);
  702. return result;
  703. }
  704. static int inv_send_pressure_dmp_data(struct inv_mpu_state *st, bool on)
  705. {
  706. u8 rn[] = {0xa3, 0xa3};
  707. u8 rf[] = {0xf4, 0x12};
  708. u8 *r;
  709. int result;
  710. if (on)
  711. r = rn;
  712. else
  713. r = rf;
  714. result = mem_w_key(KEY_CFG_OUT_PRESS, ARRAY_SIZE(rf), r);
  715. return result;
  716. }
  717. static int inv_send_step_detector(struct inv_mpu_state *st, bool on)
  718. {
  719. u8 rn[] = {0xa3, 0xa3};
  720. u8 rf[] = {0xf4, 0x0e};
  721. u8 *r;
  722. int result;
  723. if (on)
  724. r = rn;
  725. else
  726. r = rf;
  727. result = mem_w_key(KEY_CFG_OUT_STEPDET, ARRAY_SIZE(rf), r);
  728. return result;
  729. }
  730. static int inv_set_rate(struct inv_mpu_state *st, int k, int k_ct, int rate)
  731. {
  732. int v, result;
  733. v = MPU_DEFAULT_DMP_FREQ / rate - 1;
  734. result = inv_write_2bytes(st, k, v);
  735. if (result)
  736. return result;
  737. result = inv_write_2bytes(st, k_ct, 0);
  738. return result;
  739. }
  740. static int inv_set_gyro_rate(struct inv_mpu_state *st)
  741. {
  742. int result;
  743. result = inv_set_rate(st, KEY_CFG_GYRO_ODR, KEY_ODR_CNTR_GYRO,
  744. st->sensor[SENSOR_GYRO].rate);
  745. return result;
  746. }
  747. static int inv_set_accel_rate(struct inv_mpu_state *st)
  748. {
  749. int result;
  750. result = inv_set_rate(st, KEY_CFG_ACCL_ODR, KEY_ODR_CNTR_ACCL,
  751. st->sensor[SENSOR_ACCEL].rate);
  752. return result;
  753. }
  754. static int inv_set_compass_rate(struct inv_mpu_state *st)
  755. {
  756. int result;
  757. result = inv_set_rate(st, KEY_CFG_CPASS_ODR, KEY_ODR_CNTR_CPASS,
  758. st->sensor[SENSOR_COMPASS].rate);
  759. return result;
  760. }
  761. static int inv_set_pressure_rate(struct inv_mpu_state *st)
  762. {
  763. int result;
  764. result = inv_set_rate(st, KEY_CFG_PRESS_ODR, KEY_ODR_CNTR_PRESS,
  765. st->sensor[SENSOR_PRESSURE].rate);
  766. return result;
  767. }
  768. static int inv_set_step_detector(struct inv_mpu_state *st)
  769. {
  770. return 0;
  771. }
  772. static int inv_set_lpq_rate(struct inv_mpu_state *st)
  773. {
  774. int result;
  775. result = inv_set_rate(st, KEY_CFG_3QUAT_ODR, KEY_ODR_CNTR_3QUAT,
  776. st->sensor[SENSOR_LPQ].rate);
  777. return result;
  778. }
  779. static int inv_set_sixq_rate(struct inv_mpu_state *st)
  780. {
  781. int result;
  782. result = inv_set_rate(st, KEY_CFG_6QUAT_ODR, KEY_ODR_CNTR_6QUAT,
  783. st->sensor[SENSOR_SIXQ].rate);
  784. return result;
  785. }
  786. static int inv_set_pedq_rate(struct inv_mpu_state *st)
  787. {
  788. int result;
  789. result = inv_set_rate(st, KEY_CFG_PQUAT6_ODR, KEY_ODR_CNTR_PQUAT,
  790. st->sensor[SENSOR_PEDQ].rate);
  791. return result;
  792. }
  793. static int inv_set_dmp_sysfs(struct inv_mpu_state *st)
  794. {
  795. int result, i, s;
  796. u8 d[] = {0, 0, 0, 0};
  797. result = inv_set_interrupt_on_gesture_event(st,
  798. st->chip_config.dmp_event_int_on);
  799. if (st->chip_config.dmp_event_int_on) {
  800. for (i = 0; i < SENSOR_NUM_MAX; i++) {
  801. result = st->sensor[i].send_data(st, false);
  802. if (result)
  803. return result;
  804. }
  805. } else {
  806. s = 0;
  807. for (i = 0; i < SENSOR_NUM_MAX; i++) {
  808. result = st->sensor[i].send_data(st, st->sensor[i].on);
  809. if (result)
  810. return result;
  811. if (st->sensor[i].on) {
  812. if (0 == st->sensor[i].rate)
  813. return -EINVAL;
  814. s += st->sensor[i].rate *
  815. st->sensor[i].sample_size;
  816. result = st->sensor[i].set_rate(st);
  817. if (result)
  818. return result;
  819. st->sensor[i].counter = MPU_DEFAULT_DMP_FREQ /
  820. st->sensor[i].rate;
  821. }
  822. }
  823. st->bytes_per_sec = s;
  824. if (st->sensor[SENSOR_STEP].on)
  825. result = inv_add_step_indicator(st, true);
  826. else
  827. result = inv_add_step_indicator(st,
  828. st->chip_config.step_indicator_on);
  829. if (result)
  830. return result;
  831. }
  832. result = inv_batchmode_setup(st);
  833. if (result)
  834. return result;
  835. st->dmp_counter = 0;
  836. result = mem_w_key(KEY_DMP_RUN_CNTR, ARRAY_SIZE(d), d);
  837. if (result)
  838. return result;
  839. /* set the compass flag invalid at the beginning */
  840. result = inv_write_2bytes(st, KEY_CPASS_VALID, 0);
  841. return result;
  842. }
  843. static void inv_get_data_count(struct inv_mpu_state *st)
  844. {
  845. struct inv_chip_config_s *c;
  846. int b, i;
  847. c = &st->chip_config;
  848. b = 0;
  849. if (st->chip_config.dmp_on) {
  850. for (i = 0; i < SENSOR_NUM_MAX; i++) {
  851. if (st->sensor[i].on)
  852. b += st->sensor[i].sample_size;
  853. }
  854. } else {
  855. if (st->sensor[SENSOR_ACCEL].on)
  856. b += BYTES_PER_SENSOR;
  857. if (st->sensor[SENSOR_GYRO].on)
  858. b += BYTES_PER_SENSOR;
  859. }
  860. c->bytes_per_datum = b;
  861. return;
  862. }
  863. /*
  864. * set_inv_enable() - main enable/disable function.
  865. */
  866. int set_inv_enable(struct iio_dev *indio_dev, bool enable)
  867. {
  868. struct inv_mpu_state *st = iio_priv(indio_dev);
  869. struct inv_reg_map_s *reg;
  870. u8 data[2];
  871. int result;
  872. reg = &st->reg;
  873. if (enable) {
  874. st->batch.on = false;
  875. st->batch.step_only = false;
  876. inv_get_data_count(st);
  877. if (st->chip_config.new_fifo_rate !=
  878. st->chip_config.fifo_rate) {
  879. result = set_fifo_rate_reg(st);
  880. if (result)
  881. return result;
  882. }
  883. if (st->chip_config.dmp_on) {
  884. result = inv_set_dmp_sysfs(st);
  885. if (result)
  886. return result;
  887. }
  888. if (st->chip_config.gyro_enable) {
  889. result = st->switch_gyro_engine(st, true);
  890. if (result)
  891. return result;
  892. }
  893. if (st->chip_config.accel_enable) {
  894. result = st->switch_accel_engine(st, true);
  895. if (result)
  896. return result;
  897. }
  898. if (st->sensor[SENSOR_COMPASS].on) {
  899. result = st->slave_compass->resume(st);
  900. if (result)
  901. return result;
  902. }
  903. if (st->sensor[SENSOR_PRESSURE].on) {
  904. result = st->slave_pressure->resume(st);
  905. if (result)
  906. return result;
  907. }
  908. result = inv_reset_fifo(indio_dev);
  909. if (result)
  910. return result;
  911. if (st->batch.step_only)
  912. schedule_delayed_work(&st->work,
  913. msecs_to_jiffies(st->batch.timeout));
  914. } else {
  915. if (st->batch.step_only)
  916. cancel_delayed_work_sync(&st->work);
  917. if ((INV_MPU3050 != st->chip_type)
  918. && st->chip_config.lpa_mode) {
  919. /* if the chip is in low power mode,
  920. register write/read could fail */
  921. result = inv_lpa_mode(st, 0);
  922. if (result)
  923. return result;
  924. }
  925. result = inv_i2c_single_write(st, reg->fifo_en, 0);
  926. if (result)
  927. return result;
  928. if (st->chip_config.dmp_on) {
  929. result = inv_read_time_and_ticks(st, false);
  930. if (result)
  931. return result;
  932. result = inv_i2c_read(st, reg->fifo_count_h,
  933. FIFO_COUNT_BYTE, data);
  934. if (result)
  935. return result;
  936. st->fifo_count = be16_to_cpup((__be16 *)(data));
  937. result = inv_process_batchmode(st, true);
  938. if (result)
  939. return result;
  940. }
  941. /* disable fifo reading */
  942. if (INV_MPU3050 != st->chip_type) {
  943. result = inv_i2c_single_write(st, reg->int_enable, 0);
  944. if (result)
  945. return result;
  946. result = inv_i2c_single_write(st, reg->user_ctrl, 0);
  947. } else {
  948. result = inv_i2c_single_write(st, reg->int_enable,
  949. st->plat_data.int_config);
  950. }
  951. if (result)
  952. return result;
  953. /* turn off the gyro/accel engine during disable phase */
  954. result = st->switch_gyro_engine(st, false);
  955. if (result)
  956. return result;
  957. result = st->switch_accel_engine(st, false);
  958. if (result)
  959. return result;
  960. if (st->sensor[SENSOR_COMPASS].on) {
  961. result = st->slave_compass->suspend(st);
  962. if (result)
  963. return result;
  964. }
  965. if (st->sensor[SENSOR_PRESSURE].on) {
  966. result = st->slave_pressure->suspend(st);
  967. if (result)
  968. return result;
  969. }
  970. }
  971. st->chip_config.enable = enable;
  972. return 0;
  973. }
  974. /*
  975. * inv_irq_handler() - Cache a timestamp at each data ready interrupt.
  976. */
  977. static irqreturn_t inv_irq_handler(int irq, void *dev_id)
  978. {
  979. struct inv_mpu_state *st = (struct inv_mpu_state *)dev_id;
  980. u64 ts;
  981. if (!st->chip_config.dmp_on) {
  982. ts = get_time_ns();
  983. kfifo_in_spinlocked(&st->timestamps, &ts, 1,
  984. &st->time_stamp_lock);
  985. }
  986. return IRQ_WAKE_THREAD;
  987. }
  988. static void inv_report_data_3050(struct iio_dev *indio_dev, s64 t,
  989. int has_footer, u8 *data)
  990. {
  991. struct inv_mpu_state *st = iio_priv(indio_dev);
  992. int ind, i;
  993. short s[THREE_AXIS];
  994. ind = 0;
  995. if (has_footer)
  996. ind += 2;
  997. if (st->sensor[SENSOR_GYRO].on) {
  998. for (i = 0; i < 3; i++)
  999. s[i] = be16_to_cpup((__be16 *)(&data[ind + i * 2]));
  1000. inv_push_8bytes_buffer(st, GYRO_HDR, t, s);
  1001. ind += BYTES_PER_SENSOR;
  1002. }
  1003. if (st->sensor[SENSOR_ACCEL].on) {
  1004. st->slave_accel->combine_data(&data[ind], s);
  1005. inv_push_8bytes_buffer(st, ACCEL_HDR, t, s);
  1006. }
  1007. }
  1008. /*
  1009. * inv_read_fifo_mpu3050() - Transfer data from FIFO to ring buffer for
  1010. * mpu3050.
  1011. */
  1012. irqreturn_t inv_read_fifo_mpu3050(int irq, void *dev_id)
  1013. {
  1014. struct inv_mpu_state *st = (struct inv_mpu_state *)dev_id;
  1015. struct iio_dev *indio_dev = iio_priv_to_dev(st);
  1016. int bytes_per_datum;
  1017. u8 data[64];
  1018. int result;
  1019. short fifo_count, byte_read;
  1020. s64 timestamp;
  1021. struct inv_reg_map_s *reg;
  1022. reg = &st->reg;
  1023. mutex_lock(&indio_dev->mlock);
  1024. if (st->chip_config.dmp_on)
  1025. bytes_per_datum = HEADERED_NORMAL_BYTES;
  1026. else
  1027. bytes_per_datum = (st->sensor[SENSOR_ACCEL].on +
  1028. st->sensor[SENSOR_GYRO].on) * BYTES_PER_SENSOR;
  1029. if (st->chip_config.has_footer)
  1030. byte_read = bytes_per_datum + MPU3050_FOOTER_SIZE;
  1031. else
  1032. byte_read = bytes_per_datum;
  1033. fifo_count = 0;
  1034. if (byte_read != 0) {
  1035. result = inv_i2c_read(st, reg->fifo_count_h,
  1036. FIFO_COUNT_BYTE, data);
  1037. if (result)
  1038. goto end_session;
  1039. fifo_count = be16_to_cpup((__be16 *)(&data[0]));
  1040. if (fifo_count < byte_read)
  1041. goto end_session;
  1042. if (fifo_count & 1)
  1043. goto flush_fifo;
  1044. if (fifo_count > FIFO_THRESHOLD)
  1045. goto flush_fifo;
  1046. /* Timestamp mismatch. */
  1047. if (kfifo_len(&st->timestamps) <
  1048. fifo_count / byte_read)
  1049. goto flush_fifo;
  1050. if (kfifo_len(&st->timestamps) >
  1051. fifo_count / byte_read + TIME_STAMP_TOR) {
  1052. if (st->chip_config.dmp_on) {
  1053. result = kfifo_out(&st->timestamps,
  1054. &timestamp, 1);
  1055. if (result != 1)
  1056. goto flush_fifo;
  1057. } else {
  1058. goto flush_fifo;
  1059. }
  1060. }
  1061. }
  1062. while ((bytes_per_datum != 0) && (fifo_count >= byte_read)) {
  1063. result = inv_i2c_read(st, reg->fifo_r_w, byte_read, data);
  1064. if (result)
  1065. goto flush_fifo;
  1066. result = kfifo_out(&st->timestamps, &timestamp, 1);
  1067. if (result != 1)
  1068. goto flush_fifo;
  1069. inv_report_data_3050(indio_dev, timestamp,
  1070. st->chip_config.has_footer, data);
  1071. fifo_count -= byte_read;
  1072. if (st->chip_config.has_footer == 0) {
  1073. st->chip_config.has_footer = 1;
  1074. byte_read = bytes_per_datum + MPU3050_FOOTER_SIZE;
  1075. }
  1076. }
  1077. end_session:
  1078. mutex_unlock(&indio_dev->mlock);
  1079. return IRQ_HANDLED;
  1080. flush_fifo:
  1081. /* Flush HW and SW FIFOs. */
  1082. inv_reset_fifo(indio_dev);
  1083. inv_clear_kfifo(st);
  1084. mutex_unlock(&indio_dev->mlock);
  1085. return IRQ_HANDLED;
  1086. }
  1087. static int inv_report_gyro_accel(struct iio_dev *indio_dev,
  1088. u8 *data, s64 t)
  1089. {
  1090. struct inv_mpu_state *st = iio_priv(indio_dev);
  1091. short s[THREE_AXIS];
  1092. int ind;
  1093. int i;
  1094. ind = 0;
  1095. if (st->sensor[SENSOR_ACCEL].on) {
  1096. for (i = 0; i < 3; i++)
  1097. s[i] = be16_to_cpup((__be16 *)(&data[ind + i * 2]));
  1098. inv_push_8bytes_buffer(st, ACCEL_HDR, t, s);
  1099. ind += BYTES_PER_SENSOR;
  1100. }
  1101. if (st->sensor[SENSOR_GYRO].on) {
  1102. for (i = 0; i < 3; i++)
  1103. s[i] = be16_to_cpup((__be16 *)(&data[ind + i * 2]));
  1104. inv_push_8bytes_buffer(st, GYRO_HDR, t, s);
  1105. ind += BYTES_PER_SENSOR;
  1106. }
  1107. return 0;
  1108. }
  1109. static void inv_process_motion(struct inv_mpu_state *st)
  1110. {
  1111. struct iio_dev *indio_dev = iio_priv_to_dev(st);
  1112. int result;
  1113. u8 data[1];
  1114. /* motion interrupt */
  1115. result = inv_i2c_read(st, REG_INT_STATUS, 1, data);
  1116. if (result)
  1117. return;
  1118. if (data[0] & BIT_MOT_INT)
  1119. sysfs_notify(&indio_dev->dev.kobj, NULL, "event_accel_motion");
  1120. }
  1121. static int inv_get_timestamp(struct inv_mpu_state *st, int count)
  1122. {
  1123. u32 *dur;
  1124. u32 thresh;
  1125. s32 diff, result, counter;
  1126. u64 ts;
  1127. /* goal of algorithm is to estimate the true frequency of the chip */
  1128. if (st->chip_config.dmp_on && st->chip_config.dmp_event_int_on)
  1129. return 0;
  1130. dur = &st->irq_dur_ns;
  1131. counter = 1;
  1132. thresh = min((u32)((*dur) >> 2), (u32)(10 * NSEC_PER_MSEC));
  1133. while (kfifo_len(&st->timestamps) >= count) {
  1134. result = kfifo_out(&st->timestamps, &ts, 1);
  1135. if (result != 1)
  1136. return -EINVAL;
  1137. /* first time since reset fifo, just take it */
  1138. if (!st->ts_counter) {
  1139. st->last_ts = ts;
  1140. st->prev_ts = ts;
  1141. st->ts_counter++;
  1142. return 0;
  1143. }
  1144. diff = (s32)(ts - st->prev_ts);
  1145. st->prev_ts = ts;
  1146. if (abs(diff - (*dur)) < thresh) {
  1147. st->diff_accumulater >>= 1;
  1148. if (*dur > diff)
  1149. st->diff_accumulater -= (((*dur) - diff) >> 7);
  1150. else
  1151. st->diff_accumulater += ((diff - (*dur)) >> 7);
  1152. *dur += st->diff_accumulater;
  1153. }
  1154. }
  1155. ts = *dur;
  1156. ts *= counter;
  1157. st->last_ts += ts;
  1158. return 0;
  1159. }
  1160. static int inv_process_dmp_interrupt(struct inv_mpu_state *st)
  1161. {
  1162. int r;
  1163. u8 d[1];
  1164. struct iio_dev *indio_dev = iio_priv_to_dev(st);
  1165. #define DMP_INT_SMD 0x04
  1166. #define DMP_INT_PED 0x08
  1167. #define DMP_INT_TAP 0x10
  1168. if ((!st->chip_config.smd_enable) &&
  1169. (!st->ped.int_on) &&
  1170. (!st->tap.on))
  1171. return 0;
  1172. r = inv_i2c_read(st, REG_DMP_INT_STATUS, 1, d);
  1173. if (r)
  1174. return r;
  1175. if (d[0] & DMP_INT_SMD) {
  1176. sysfs_notify(&indio_dev->dev.kobj, NULL, "event_smd");
  1177. st->chip_config.smd_enable = false;
  1178. st->chip_config.smd_triggered = true;
  1179. }
  1180. if (d[0] & DMP_INT_PED)
  1181. sysfs_notify(&indio_dev->dev.kobj, NULL, "event_pedometer");
  1182. if (d[0] & DMP_INT_TAP)
  1183. sysfs_notify(&indio_dev->dev.kobj, NULL, "event_tap");
  1184. return 0;
  1185. }
  1186. static int inv_get_shift2(int count)
  1187. {
  1188. int i;
  1189. if (1 == count)
  1190. return 13;
  1191. if (count > 2000)
  1192. return 2;
  1193. i = 13;
  1194. while (count > 0) {
  1195. count >>= 1;
  1196. i--;
  1197. }
  1198. return i;
  1199. }
  1200. static void inv_adjust_sensor_ts(struct inv_mpu_state *st, int sensor_ind)
  1201. {
  1202. s64 diff;
  1203. int i, rate_adj, s3, delta, total_count;
  1204. if (!st->chip_config.adjust_time)
  1205. return;
  1206. #define MAX_DIFF 0x7fffffff
  1207. total_count = st->dmp_ticks;
  1208. if (0 == total_count)
  1209. total_count = 1;
  1210. diff = (st->last_ts - st->prev_ts) - (u64)(st->dmp_interval) *
  1211. total_count;
  1212. if (diff > MAX_DIFF)
  1213. diff = MAX_DIFF;
  1214. if (diff < -MAX_DIFF)
  1215. diff = -MAX_DIFF;
  1216. s3 = 4;
  1217. rate_adj = (int)diff;
  1218. rate_adj /= total_count;
  1219. delta = min(abs(rate_adj) >> inv_get_shift2(total_count),
  1220. DMP_INTERVAL_MIN_ADJ);
  1221. if (rate_adj < 0)
  1222. delta = -delta;
  1223. st->dmp_interval_accum >>= 1;
  1224. st->dmp_interval_accum += delta;
  1225. st->dmp_interval += st->dmp_interval_accum;
  1226. for (i = 0; i < SENSOR_NUM_MAX; i++)
  1227. if (st->sensor[i].on)
  1228. st->sensor[i].dur = st->dmp_interval *
  1229. st->sensor[i].counter;
  1230. st->prev_ts = st->last_ts;
  1231. }
  1232. static void inv_reset_ts(struct inv_mpu_state *st, u64 curr_ts)
  1233. {
  1234. u32 dur, i;
  1235. dur = USEC_PER_SEC / st->bytes_per_sec;
  1236. dur *= 1024;
  1237. curr_ts -= ((u64)dur * NSEC_PER_USEC);
  1238. for (i = 0; i < SENSOR_NUM_MAX; i++)
  1239. st->sensor[i].ts = curr_ts;
  1240. }
  1241. static void inv_push_step_indicator(struct inv_mpu_state *st, int sensor_ind,
  1242. int steps)
  1243. {
  1244. int dur, i;
  1245. s16 sen[3];
  1246. u64 base;
  1247. #define STEP_INDICATOR_HEADER 0x0001
  1248. dur = st->sensor[sensor_ind].dur / steps;
  1249. base = st->sensor[sensor_ind].ts;
  1250. for (i = 1; i < steps; i++)
  1251. inv_push_8bytes_buffer(st, STEP_INDICATOR_HEADER,
  1252. base + i * dur, sen);
  1253. }
  1254. static int inv_parse_header(u16 hdr)
  1255. {
  1256. int sensor_ind;
  1257. switch (hdr) {
  1258. case ACCEL_HDR:
  1259. sensor_ind = SENSOR_ACCEL;
  1260. break;
  1261. case GYRO_HDR:
  1262. sensor_ind = SENSOR_GYRO;
  1263. break;
  1264. case PEDQUAT_HDR:
  1265. sensor_ind = SENSOR_PEDQ;
  1266. break;
  1267. case LPQUAT_HDR:
  1268. sensor_ind = SENSOR_LPQ;
  1269. break;
  1270. case SIXQUAT_HDR:
  1271. sensor_ind = SENSOR_SIXQ;
  1272. break;
  1273. case COMPASS_HDR:
  1274. sensor_ind = SENSOR_COMPASS;
  1275. break;
  1276. case PRESSURE_HDR:
  1277. sensor_ind = SENSOR_PRESSURE;
  1278. break;
  1279. case STEP_DETECTOR_HDR:
  1280. sensor_ind = SENSOR_STEP;
  1281. break;
  1282. default:
  1283. sensor_ind = SENSOR_INVALID;
  1284. break;
  1285. }
  1286. return sensor_ind;
  1287. }
  1288. static int inv_get_sensor_count(struct inv_mpu_state *st,
  1289. u8 *d, int target_bytes)
  1290. {
  1291. u8 *dptr;
  1292. u16 hdr;
  1293. int sensor_ind;
  1294. int sensor_count;
  1295. sensor_count = 0;
  1296. dptr = d;
  1297. while (dptr - d <= target_bytes - HEADERED_NORMAL_BYTES) {
  1298. hdr = (u16)be16_to_cpup((__be16 *)(dptr));
  1299. hdr &= (~STEP_INDICATOR_MASK);
  1300. sensor_ind = inv_parse_header(hdr);
  1301. /* incomplete packet */
  1302. if (target_bytes - (dptr - d) <
  1303. st->sensor[sensor_ind].sample_size)
  1304. break;
  1305. if ((sensor_ind != SENSOR_INVALID) &&
  1306. st->sensor[sensor_ind].on) {
  1307. dptr += st->sensor[sensor_ind].sample_size;
  1308. sensor_count++;
  1309. } else {
  1310. dptr += HEADERED_NORMAL_BYTES;
  1311. }
  1312. }
  1313. return sensor_count;
  1314. }
  1315. static int inv_process_batchmode(struct inv_mpu_state *st, bool insert)
  1316. {
  1317. int i, target_bytes, tmp, res, sensor_count, counter;
  1318. int sensor_ind, q[3];
  1319. u8 *dptr, *d;
  1320. u16 hdr, steps;
  1321. s16 sen[3];
  1322. u64 t;
  1323. bool done_flag;
  1324. #define END_MARKER 0x0010
  1325. if (1024 == st->fifo_count) {
  1326. inv_reset_ts(st, st->last_ts);
  1327. st->left_over_size = 0;
  1328. }
  1329. d = fifo_data;
  1330. if (st->left_over_size > 0) {
  1331. dptr = d + st->left_over_size;
  1332. memcpy(d, st->left_over, st->left_over_size);
  1333. } else {
  1334. dptr = d;
  1335. }
  1336. target_bytes = st->fifo_count;
  1337. while (target_bytes > 0) {
  1338. if (target_bytes < MAX_READ_SIZE)
  1339. tmp = target_bytes;
  1340. else
  1341. tmp = MAX_READ_SIZE;
  1342. res = inv_i2c_read(st, st->reg.fifo_r_w, tmp, dptr);
  1343. if (res < 0)
  1344. return res;
  1345. dptr += tmp;
  1346. target_bytes -= tmp;
  1347. }
  1348. dptr = d;
  1349. done_flag = false;
  1350. target_bytes = st->fifo_count + st->left_over_size;
  1351. if (insert)
  1352. sensor_count = inv_get_sensor_count(st, d, target_bytes);
  1353. else
  1354. sensor_count = 0;
  1355. counter = 0;
  1356. while ((dptr - d <= target_bytes - HEADERED_NORMAL_BYTES) &&
  1357. (!done_flag)) {
  1358. hdr = (u16)be16_to_cpup((__be16 *)(dptr));
  1359. steps = (hdr & STEP_INDICATOR_MASK);
  1360. hdr &= (~STEP_INDICATOR_MASK);
  1361. sensor_ind = inv_parse_header(hdr);
  1362. /* incomplete packet */
  1363. if (target_bytes - (dptr - d) <
  1364. st->sensor[sensor_ind].sample_size) {
  1365. done_flag = true;
  1366. continue;
  1367. }
  1368. /* error packet */
  1369. if ((sensor_ind == SENSOR_INVALID) ||
  1370. (!st->sensor[sensor_ind].on)) {
  1371. dptr += HEADERED_NORMAL_BYTES;
  1372. continue;
  1373. }
  1374. if (insert) {
  1375. counter++;
  1376. if (counter == sensor_count)
  1377. hdr |= END_MARKER;
  1378. }
  1379. if (sensor_ind == SENSOR_STEP) {
  1380. tmp = (int)be32_to_cpup((__be32 *)(dptr + 4));
  1381. t = st->step_detector_base_ts +
  1382. (u64)tmp * 5 * NSEC_PER_MSEC;
  1383. inv_push_8bytes_buffer(st, hdr, t, sen);
  1384. dptr += HEADERED_NORMAL_BYTES;
  1385. continue;
  1386. }
  1387. if (steps > 1)
  1388. inv_push_step_indicator(st, sensor_ind, steps);
  1389. st->sensor[sensor_ind].ts += (u64)st->sensor[sensor_ind].dur;
  1390. t = st->sensor[sensor_ind].ts;
  1391. if (sensor_ind == SENSOR_COMPASS) {
  1392. if (!st->chip_config.normal_compass_measure) {
  1393. st->chip_config.normal_compass_measure = 1;
  1394. dptr += HEADERED_NORMAL_BYTES;
  1395. continue;
  1396. }
  1397. for (i = 0; i < 6; i++)
  1398. st->fifo_data[i] = dptr[i + 2];
  1399. st->slave_compass->read_data(st, sen);
  1400. inv_push_8bytes_buffer(st, hdr | (!!steps), t, sen);
  1401. dptr += HEADERED_NORMAL_BYTES;
  1402. continue;
  1403. }
  1404. if (sensor_ind == SENSOR_PRESSURE) {
  1405. if (!st->chip_config.normal_pressure_measure) {
  1406. st->chip_config.normal_pressure_measure = 1;
  1407. dptr += HEADERED_NORMAL_BYTES;
  1408. continue;
  1409. }
  1410. for (i = 0; i < 6; i++)
  1411. st->fifo_data[i] = dptr[i + 2];
  1412. st->slave_pressure->read_data(st, sen);
  1413. inv_push_8bytes_buffer(st, hdr | (!!steps), t, sen);
  1414. dptr += HEADERED_NORMAL_BYTES;
  1415. continue;
  1416. }
  1417. if (st->sensor[sensor_ind].sample_size == HEADERED_Q_BYTES) {
  1418. for (i = 0; i < 3; i++)
  1419. q[i] = (int)be32_to_cpup((__be32 *)(dptr + 4
  1420. + i * 4));
  1421. inv_push_16bytes_buffer(st, hdr | (!!steps), t, q);
  1422. } else {
  1423. for (i = 0; i < 3; i++)
  1424. sen[i] = (short)be16_to_cpup((__be16 *)(dptr +
  1425. 2 + i * 2));
  1426. inv_push_8bytes_buffer(st, hdr | (!!steps), t, sen);
  1427. }
  1428. dptr += st->sensor[sensor_ind].sample_size;
  1429. }
  1430. inv_adjust_sensor_ts(st, sensor_ind);
  1431. st->left_over_size = target_bytes - (dptr - d);
  1432. if (st->left_over_size)
  1433. memcpy(st->left_over, dptr, st->left_over_size);
  1434. return 0;
  1435. }
  1436. int inv_read_time_and_ticks(struct inv_mpu_state *st, bool resume)
  1437. {
  1438. int result;
  1439. u32 counter;
  1440. u8 data[4];
  1441. #define MIN_TICK_READING_TIME NSEC_PER_SEC
  1442. st->last_ts = get_time_ns();
  1443. if ((st->last_ts - st->prev_ts < MIN_TICK_READING_TIME) &&
  1444. (!resume)) {
  1445. st->chip_config.adjust_time = false;
  1446. return 0;
  1447. }
  1448. result = mpu_memory_read(st, st->i2c_addr,
  1449. inv_dmp_get_address(KEY_DMP_RUN_CNTR), 4, data);
  1450. if (result)
  1451. return result;
  1452. counter = be32_to_cpup((__be32 *)(data));
  1453. if (resume) {
  1454. st->dmp_counter = counter;
  1455. st->prev_ts = st->last_ts;
  1456. return 0;
  1457. }
  1458. if (counter > st->dmp_counter)
  1459. st->dmp_ticks = counter - st->dmp_counter;
  1460. else
  1461. st->dmp_ticks = 0xffffffff - st->dmp_counter + counter + 1;
  1462. st->dmp_counter = counter;
  1463. st->chip_config.adjust_time = true;
  1464. return 0;
  1465. }
  1466. /*
  1467. * inv_read_fifo() - Transfer data from FIFO to ring buffer.
  1468. */
  1469. irqreturn_t inv_read_fifo(int irq, void *dev_id)
  1470. {
  1471. struct inv_mpu_state *st = (struct inv_mpu_state *)dev_id;
  1472. struct iio_dev *indio_dev = iio_priv_to_dev(st);
  1473. int result, bpm;
  1474. u8 data[MAX_HW_FIFO_BYTES];
  1475. u16 fifo_count;
  1476. struct inv_reg_map_s *reg;
  1477. u64 pts1;
  1478. #define DMP_MIN_RUN_TIME (37 * NSEC_PER_MSEC)
  1479. mutex_lock(&st->suspend_resume_lock);
  1480. mutex_lock(&indio_dev->mlock);
  1481. if (st->chip_config.dmp_on) {
  1482. pts1 = get_time_ns();
  1483. result = inv_process_dmp_interrupt(st);
  1484. if (result || st->chip_config.dmp_event_int_on)
  1485. goto end_session;
  1486. if (!st->chip_config.smd_triggered) {
  1487. if (pts1 - st->last_run_time < DMP_MIN_RUN_TIME)
  1488. goto end_session;
  1489. else
  1490. st->last_run_time = pts1;
  1491. } else {
  1492. st->chip_config.smd_triggered = false;
  1493. }
  1494. }
  1495. if (!(iio_buffer_enabled(indio_dev)) || (!st->chip_config.enable))
  1496. goto end_session;
  1497. reg = &st->reg;
  1498. if (!(st->sensor[SENSOR_ACCEL].on |
  1499. st->sensor[SENSOR_GYRO].on |
  1500. st->sensor[SENSOR_COMPASS].on |
  1501. st->sensor[SENSOR_PRESSURE].on |
  1502. st->chip_config.dmp_on |
  1503. st->mot_int.mot_on))
  1504. goto end_session;
  1505. if (st->chip_config.lpa_mode) {
  1506. result = inv_i2c_read(st, reg->raw_accel,
  1507. BYTES_PER_SENSOR, data);
  1508. if (result)
  1509. goto end_session;
  1510. inv_report_gyro_accel(indio_dev, data, get_time_ns());
  1511. if (st->mot_int.mot_on)
  1512. inv_process_motion(st);
  1513. goto end_session;
  1514. }
  1515. if (st->chip_config.dmp_on) {
  1516. result = inv_read_time_and_ticks(st, false);
  1517. if (result)
  1518. goto end_session;
  1519. }
  1520. bpm = st->chip_config.bytes_per_datum;
  1521. fifo_count = 0;
  1522. if (bpm) {
  1523. result = inv_i2c_read(st, reg->fifo_count_h, FIFO_COUNT_BYTE,
  1524. data);
  1525. if (result)
  1526. goto end_session;
  1527. fifo_count = be16_to_cpup((__be16 *)(data));
  1528. /* fifo count can't be odd number */
  1529. if (fifo_count & 1)
  1530. goto flush_fifo;
  1531. if (fifo_count == 0)
  1532. goto end_session;
  1533. st->fifo_count = fifo_count;
  1534. }
  1535. if (st->batch.step_only) {
  1536. process_step_only_batch(st);
  1537. st->batch.post_isr_run = true;
  1538. } else if (st->chip_config.dmp_on) {
  1539. result = inv_process_batchmode(st, false);
  1540. } else {
  1541. if (fifo_count > FIFO_THRESHOLD)
  1542. goto flush_fifo;
  1543. if (bpm) {
  1544. while (fifo_count >= bpm) {
  1545. result = inv_i2c_read(st, reg->fifo_r_w, bpm,
  1546. data);
  1547. if (result)
  1548. goto flush_fifo;
  1549. result = inv_get_timestamp(st,
  1550. fifo_count / bpm);
  1551. if (result)
  1552. goto flush_fifo;
  1553. inv_report_gyro_accel(indio_dev, data,
  1554. st->last_ts);
  1555. fifo_count -= bpm;
  1556. }
  1557. } else {
  1558. result = inv_get_timestamp(st, 1);
  1559. if (result)
  1560. goto flush_fifo;
  1561. }
  1562. inv_send_compass_data(st);
  1563. inv_send_pressure_data(st);
  1564. }
  1565. end_session:
  1566. mutex_unlock(&indio_dev->mlock);
  1567. mutex_unlock(&st->suspend_resume_lock);
  1568. return IRQ_HANDLED;
  1569. flush_fifo:
  1570. /* Flush HW and SW FIFOs. */
  1571. inv_reset_fifo(indio_dev);
  1572. inv_clear_kfifo(st);
  1573. mutex_unlock(&indio_dev->mlock);
  1574. mutex_unlock(&st->suspend_resume_lock);
  1575. return IRQ_HANDLED;
  1576. }
  1577. #endif
  1578. void ssp_iio_unconfigure_ring(struct iio_dev *indio_dev)
  1579. {
  1580. iio_kfifo_free(indio_dev->buffer);
  1581. };
  1582. static int ssp_predisable(struct iio_dev *indio_dev)
  1583. {
  1584. /* sch0317 need to implement
  1585. struct inv_mpu_state *st = iio_priv(indio_dev);
  1586. int result;
  1587. if (st->chip_config.enable) {
  1588. result = set_inv_enable(indio_dev, false);
  1589. if (result)
  1590. return result;
  1591. result = st->set_power_state(st, false);
  1592. if (result)
  1593. return result;
  1594. }
  1595. */
  1596. return 0;
  1597. }
  1598. #if 0
  1599. static int inv_check_conflict_sysfs(struct iio_dev *indio_dev)
  1600. {
  1601. struct inv_mpu_state *st = iio_priv(indio_dev);
  1602. if (st->chip_config.lpa_mode) {
  1603. /* dmp cannot run with low power mode on */
  1604. st->chip_config.dmp_on = 0;
  1605. st->chip_config.gyro_enable = false;
  1606. st->sensor[SENSOR_GYRO].on = false;
  1607. st->sensor[SENSOR_COMPASS].on = false;
  1608. }
  1609. if (st->sensor[SENSOR_GYRO].on &&
  1610. (!st->chip_config.gyro_enable)) {
  1611. st->chip_config.gyro_enable = true;
  1612. }
  1613. if (st->sensor[SENSOR_ACCEL].on &&
  1614. (!st->chip_config.accel_enable)) {
  1615. st->chip_config.accel_enable = true;
  1616. }
  1617. return 0;
  1618. }
  1619. #endif
  1620. static int ssp_preenable(struct iio_dev *indio_dev)
  1621. {
  1622. int result;
  1623. //result = inv_check_conflict_sysfs(indio_dev);
  1624. //if (result)
  1625. // return result;
  1626. result = iio_sw_buffer_preenable(indio_dev);
  1627. return result;
  1628. }
  1629. #if 0
  1630. void inv_init_sensor_struct(struct inv_mpu_state *st)
  1631. {
  1632. int i;
  1633. for (i = 0; i < SENSOR_NUM_MAX; i++) {
  1634. if (i < SENSOR_SIXQ)
  1635. st->sensor[i].sample_size =
  1636. HEADERED_NORMAL_BYTES;
  1637. else
  1638. st->sensor[i].sample_size = HEADERED_Q_BYTES;
  1639. if (i == SENSOR_STEP) {
  1640. st->sensor[i].rate = 1;
  1641. st->sensor[i].dur = NSEC_PER_SEC;
  1642. } else {
  1643. st->sensor[i].rate = INIT_DMP_OUTPUT_RATE;
  1644. st->sensor[i].dur = NSEC_PER_SEC /
  1645. INIT_DMP_OUTPUT_RATE;
  1646. }
  1647. }
  1648. st->sensor[SENSOR_ACCEL].send_data = inv_send_accel_data;
  1649. st->sensor[SENSOR_GYRO].send_data = inv_send_gyro_data;
  1650. st->sensor[SENSOR_COMPASS].send_data = inv_send_compass_dmp_data;
  1651. st->sensor[SENSOR_PRESSURE].send_data = inv_send_pressure_dmp_data;
  1652. st->sensor[SENSOR_STEP].send_data = inv_send_step_detector;
  1653. st->sensor[SENSOR_PEDQ].send_data = inv_send_ped_q_data;
  1654. st->sensor[SENSOR_SIXQ].send_data = inv_send_six_q_data;
  1655. st->sensor[SENSOR_LPQ].send_data = inv_send_three_q_data;
  1656. st->sensor[SENSOR_ACCEL].set_rate = inv_set_accel_rate;
  1657. st->sensor[SENSOR_GYRO].set_rate = inv_set_gyro_rate;
  1658. st->sensor[SENSOR_COMPASS].set_rate = inv_set_compass_rate;
  1659. st->sensor[SENSOR_PRESSURE].set_rate = inv_set_pressure_rate;
  1660. st->sensor[SENSOR_STEP].set_rate = inv_set_step_detector;
  1661. st->sensor[SENSOR_PEDQ].set_rate = inv_set_pedq_rate;
  1662. st->sensor[SENSOR_SIXQ].set_rate = inv_set_sixq_rate;
  1663. st->sensor[SENSOR_LPQ].set_rate = inv_set_lpq_rate;
  1664. }
  1665. void batch_step_only_work(struct work_struct *work)
  1666. {
  1667. struct inv_mpu_state *st = container_of((struct delayed_work *)work,
  1668. struct inv_mpu_state, work);
  1669. struct iio_dev *indio_dev = iio_priv_to_dev(st);
  1670. u32 delay = msecs_to_jiffies(st->batch.timeout);
  1671. u8 data[FIFO_COUNT_BYTE];
  1672. int result;
  1673. mutex_lock(&indio_dev->mlock);
  1674. if (!(iio_buffer_enabled(indio_dev)) || (!st->chip_config.enable))
  1675. goto error_ret;
  1676. schedule_delayed_work(&st->work, delay);
  1677. if (st->batch.post_isr_run) {
  1678. st->batch.post_isr_run = false;
  1679. } else {
  1680. result = inv_i2c_read(st, st->reg.fifo_count_h,
  1681. FIFO_COUNT_BYTE, data);
  1682. if (result)
  1683. goto error_ret;
  1684. st->fifo_count = be16_to_cpup((__be16 *)(data));
  1685. process_step_only_batch(st);
  1686. }
  1687. error_ret:
  1688. mutex_unlock(&indio_dev->mlock);
  1689. }
  1690. int inv_flush_batch_data(struct iio_dev *indio_dev, bool *has_data)
  1691. {
  1692. struct inv_mpu_state *st = iio_priv(indio_dev);
  1693. struct inv_reg_map_s *reg;
  1694. u8 data[2];
  1695. int result;
  1696. #define EMPTY_MARKER 0x0020
  1697. reg = &st->reg;
  1698. if (!(iio_buffer_enabled(indio_dev)) || (!st->chip_config.enable))
  1699. return -EINVAL;
  1700. if (st->batch.on) {
  1701. result = inv_read_time_and_ticks(st, false);
  1702. if (result)
  1703. return result;
  1704. result = inv_i2c_read(st, reg->fifo_count_h,
  1705. FIFO_COUNT_BYTE, data);
  1706. if (result)
  1707. return result;
  1708. st->fifo_count = be16_to_cpup((__be16 *)(data));
  1709. if (st->fifo_count) {
  1710. result = inv_process_batchmode(st, true);
  1711. if (result)
  1712. return result;
  1713. *has_data = !!st->fifo_count;
  1714. return 0;
  1715. }
  1716. }
  1717. inv_push_marker_to_buffer(st, EMPTY_MARKER);
  1718. return 0;
  1719. }
  1720. #endif
  1721. static const struct iio_buffer_setup_ops ssp_iio_ring_setup_ops = {
  1722. .preenable = &ssp_preenable,
  1723. .predisable = &ssp_predisable,
  1724. };
  1725. int ssp_iio_configure_ring(struct iio_dev *indio_dev)
  1726. {
  1727. struct iio_buffer *ring;
  1728. ring = iio_kfifo_allocate(indio_dev);
  1729. if (!ring)
  1730. return -ENOMEM;
  1731. ring->bytes_per_datum = 8;
  1732. indio_dev->buffer = ring;
  1733. /* setup ring buffer */
  1734. ring->scan_timestamp = true;
  1735. indio_dev->setup_ops = &ssp_iio_ring_setup_ops;
  1736. /*scan count double count timestamp. should subtract 1. but
  1737. number of channels still includes timestamp*/
  1738. indio_dev->modes |= INDIO_BUFFER_HARDWARE; // INDIO_BUFFER_TRIGGERED
  1739. return 0;
  1740. }