dmaengine.c 28 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #include <linux/dma-mapping.h>
  47. #include <linux/init.h>
  48. #include <linux/module.h>
  49. #include <linux/mm.h>
  50. #include <linux/device.h>
  51. #include <linux/dmaengine.h>
  52. #include <linux/hardirq.h>
  53. #include <linux/spinlock.h>
  54. #include <linux/percpu.h>
  55. #include <linux/rcupdate.h>
  56. #include <linux/mutex.h>
  57. #include <linux/jiffies.h>
  58. #include <linux/rculist.h>
  59. #include <linux/idr.h>
  60. #include <linux/slab.h>
  61. static DEFINE_MUTEX(dma_list_mutex);
  62. static DEFINE_IDR(dma_idr);
  63. static LIST_HEAD(dma_device_list);
  64. static long dmaengine_ref_count;
  65. /* --- sysfs implementation --- */
  66. /**
  67. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  68. * @dev - device node
  69. *
  70. * Must be called under dma_list_mutex
  71. */
  72. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  73. {
  74. struct dma_chan_dev *chan_dev;
  75. chan_dev = container_of(dev, typeof(*chan_dev), device);
  76. return chan_dev->chan;
  77. }
  78. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  79. {
  80. struct dma_chan *chan;
  81. unsigned long count = 0;
  82. int i;
  83. int err;
  84. mutex_lock(&dma_list_mutex);
  85. chan = dev_to_dma_chan(dev);
  86. if (chan) {
  87. for_each_possible_cpu(i)
  88. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  89. err = sprintf(buf, "%lu\n", count);
  90. } else
  91. err = -ENODEV;
  92. mutex_unlock(&dma_list_mutex);
  93. return err;
  94. }
  95. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  96. char *buf)
  97. {
  98. struct dma_chan *chan;
  99. unsigned long count = 0;
  100. int i;
  101. int err;
  102. mutex_lock(&dma_list_mutex);
  103. chan = dev_to_dma_chan(dev);
  104. if (chan) {
  105. for_each_possible_cpu(i)
  106. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  107. err = sprintf(buf, "%lu\n", count);
  108. } else
  109. err = -ENODEV;
  110. mutex_unlock(&dma_list_mutex);
  111. return err;
  112. }
  113. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  114. {
  115. struct dma_chan *chan;
  116. int err;
  117. mutex_lock(&dma_list_mutex);
  118. chan = dev_to_dma_chan(dev);
  119. if (chan)
  120. err = sprintf(buf, "%d\n", chan->client_count);
  121. else
  122. err = -ENODEV;
  123. mutex_unlock(&dma_list_mutex);
  124. return err;
  125. }
  126. static struct device_attribute dma_attrs[] = {
  127. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  128. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  129. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  130. __ATTR_NULL
  131. };
  132. static void chan_dev_release(struct device *dev)
  133. {
  134. struct dma_chan_dev *chan_dev;
  135. chan_dev = container_of(dev, typeof(*chan_dev), device);
  136. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  137. mutex_lock(&dma_list_mutex);
  138. idr_remove(&dma_idr, chan_dev->dev_id);
  139. mutex_unlock(&dma_list_mutex);
  140. kfree(chan_dev->idr_ref);
  141. }
  142. kfree(chan_dev);
  143. }
  144. static struct class dma_devclass = {
  145. .name = "dma",
  146. .dev_attrs = dma_attrs,
  147. .dev_release = chan_dev_release,
  148. };
  149. /* --- client and device registration --- */
  150. #define dma_device_satisfies_mask(device, mask) \
  151. __dma_device_satisfies_mask((device), &(mask))
  152. static int
  153. __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
  154. {
  155. dma_cap_mask_t has;
  156. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  157. DMA_TX_TYPE_END);
  158. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  159. }
  160. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  161. {
  162. return chan->device->dev->driver->owner;
  163. }
  164. /**
  165. * balance_ref_count - catch up the channel reference count
  166. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  167. *
  168. * balance_ref_count must be called under dma_list_mutex
  169. */
  170. static void balance_ref_count(struct dma_chan *chan)
  171. {
  172. struct module *owner = dma_chan_to_owner(chan);
  173. while (chan->client_count < dmaengine_ref_count) {
  174. __module_get(owner);
  175. chan->client_count++;
  176. }
  177. }
  178. /**
  179. * dma_chan_get - try to grab a dma channel's parent driver module
  180. * @chan - channel to grab
  181. *
  182. * Must be called under dma_list_mutex
  183. */
  184. static int dma_chan_get(struct dma_chan *chan)
  185. {
  186. int err = -ENODEV;
  187. struct module *owner = dma_chan_to_owner(chan);
  188. if (chan->client_count) {
  189. __module_get(owner);
  190. err = 0;
  191. } else if (try_module_get(owner))
  192. err = 0;
  193. if (err == 0)
  194. chan->client_count++;
  195. /* allocate upon first client reference */
  196. if (chan->client_count == 1 && err == 0) {
  197. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  198. if (desc_cnt < 0) {
  199. err = desc_cnt;
  200. chan->client_count = 0;
  201. module_put(owner);
  202. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  203. balance_ref_count(chan);
  204. }
  205. return err;
  206. }
  207. /**
  208. * dma_chan_put - drop a reference to a dma channel's parent driver module
  209. * @chan - channel to release
  210. *
  211. * Must be called under dma_list_mutex
  212. */
  213. static void dma_chan_put(struct dma_chan *chan)
  214. {
  215. if (!chan->client_count)
  216. return; /* this channel failed alloc_chan_resources */
  217. chan->client_count--;
  218. module_put(dma_chan_to_owner(chan));
  219. if (chan->client_count == 0)
  220. chan->device->device_free_chan_resources(chan);
  221. }
  222. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  223. {
  224. enum dma_status status;
  225. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  226. dma_async_issue_pending(chan);
  227. do {
  228. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  229. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  230. printk(KERN_ERR "dma_sync_wait_timeout!\n");
  231. return DMA_ERROR;
  232. }
  233. } while (status == DMA_IN_PROGRESS);
  234. return status;
  235. }
  236. EXPORT_SYMBOL(dma_sync_wait);
  237. /**
  238. * dma_cap_mask_all - enable iteration over all operation types
  239. */
  240. static dma_cap_mask_t dma_cap_mask_all;
  241. /**
  242. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  243. * @chan - associated channel for this entry
  244. */
  245. struct dma_chan_tbl_ent {
  246. struct dma_chan *chan;
  247. };
  248. /**
  249. * channel_table - percpu lookup table for memory-to-memory offload providers
  250. */
  251. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  252. static int __init dma_channel_table_init(void)
  253. {
  254. enum dma_transaction_type cap;
  255. int err = 0;
  256. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  257. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  258. * but are not associated with an operation so they do not need
  259. * an entry in the channel_table
  260. */
  261. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  262. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  263. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  264. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  265. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  266. if (!channel_table[cap]) {
  267. err = -ENOMEM;
  268. break;
  269. }
  270. }
  271. if (err) {
  272. pr_err("dmaengine: initialization failure\n");
  273. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  274. if (channel_table[cap])
  275. free_percpu(channel_table[cap]);
  276. }
  277. return err;
  278. }
  279. arch_initcall(dma_channel_table_init);
  280. /**
  281. * dma_find_channel - find a channel to carry out the operation
  282. * @tx_type: transaction type
  283. */
  284. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  285. {
  286. return this_cpu_read(channel_table[tx_type]->chan);
  287. }
  288. EXPORT_SYMBOL(dma_find_channel);
  289. /*
  290. * net_dma_find_channel - find a channel for net_dma
  291. * net_dma has alignment requirements
  292. */
  293. struct dma_chan *net_dma_find_channel(void)
  294. {
  295. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  296. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  297. return NULL;
  298. return chan;
  299. }
  300. EXPORT_SYMBOL(net_dma_find_channel);
  301. /**
  302. * dma_issue_pending_all - flush all pending operations across all channels
  303. */
  304. void dma_issue_pending_all(void)
  305. {
  306. struct dma_device *device;
  307. struct dma_chan *chan;
  308. rcu_read_lock();
  309. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  310. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  311. continue;
  312. list_for_each_entry(chan, &device->channels, device_node)
  313. if (chan->client_count)
  314. device->device_issue_pending(chan);
  315. }
  316. rcu_read_unlock();
  317. }
  318. EXPORT_SYMBOL(dma_issue_pending_all);
  319. /**
  320. * nth_chan - returns the nth channel of the given capability
  321. * @cap: capability to match
  322. * @n: nth channel desired
  323. *
  324. * Defaults to returning the channel with the desired capability and the
  325. * lowest reference count when 'n' cannot be satisfied. Must be called
  326. * under dma_list_mutex.
  327. */
  328. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  329. {
  330. struct dma_device *device;
  331. struct dma_chan *chan;
  332. struct dma_chan *ret = NULL;
  333. struct dma_chan *min = NULL;
  334. list_for_each_entry(device, &dma_device_list, global_node) {
  335. if (!dma_has_cap(cap, device->cap_mask) ||
  336. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  337. continue;
  338. list_for_each_entry(chan, &device->channels, device_node) {
  339. if (!chan->client_count)
  340. continue;
  341. if (!min)
  342. min = chan;
  343. else if (chan->table_count < min->table_count)
  344. min = chan;
  345. if (n-- == 0) {
  346. ret = chan;
  347. break; /* done */
  348. }
  349. }
  350. if (ret)
  351. break; /* done */
  352. }
  353. if (!ret)
  354. ret = min;
  355. if (ret)
  356. ret->table_count++;
  357. return ret;
  358. }
  359. /**
  360. * dma_channel_rebalance - redistribute the available channels
  361. *
  362. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  363. * operation type) in the SMP case, and operation isolation (avoid
  364. * multi-tasking channels) in the non-SMP case. Must be called under
  365. * dma_list_mutex.
  366. */
  367. static void dma_channel_rebalance(void)
  368. {
  369. struct dma_chan *chan;
  370. struct dma_device *device;
  371. int cpu;
  372. int cap;
  373. int n;
  374. /* undo the last distribution */
  375. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  376. for_each_possible_cpu(cpu)
  377. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  378. list_for_each_entry(device, &dma_device_list, global_node) {
  379. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  380. continue;
  381. list_for_each_entry(chan, &device->channels, device_node)
  382. chan->table_count = 0;
  383. }
  384. /* don't populate the channel_table if no clients are available */
  385. if (!dmaengine_ref_count)
  386. return;
  387. /* redistribute available channels */
  388. n = 0;
  389. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  390. for_each_online_cpu(cpu) {
  391. if (num_possible_cpus() > 1)
  392. chan = nth_chan(cap, n++);
  393. else
  394. chan = nth_chan(cap, -1);
  395. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  396. }
  397. }
  398. static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
  399. dma_filter_fn fn, void *fn_param)
  400. {
  401. struct dma_chan *chan;
  402. if (!__dma_device_satisfies_mask(dev, mask)) {
  403. pr_debug("%s: wrong capabilities\n", __func__);
  404. return NULL;
  405. }
  406. /* devices with multiple channels need special handling as we need to
  407. * ensure that all channels are either private or public.
  408. */
  409. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  410. list_for_each_entry(chan, &dev->channels, device_node) {
  411. /* some channels are already publicly allocated */
  412. if (chan->client_count)
  413. return NULL;
  414. }
  415. list_for_each_entry(chan, &dev->channels, device_node) {
  416. if (chan->client_count) {
  417. pr_debug("%s: %s busy\n",
  418. __func__, dma_chan_name(chan));
  419. continue;
  420. }
  421. if (fn && !fn(chan, fn_param)) {
  422. pr_debug("%s: %s filter said false\n",
  423. __func__, dma_chan_name(chan));
  424. continue;
  425. }
  426. return chan;
  427. }
  428. return NULL;
  429. }
  430. /**
  431. * dma_request_channel - try to allocate an exclusive channel
  432. * @mask: capabilities that the channel must satisfy
  433. * @fn: optional callback to disposition available channels
  434. * @fn_param: opaque parameter to pass to dma_filter_fn
  435. */
  436. struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
  437. {
  438. struct dma_device *device, *_d;
  439. struct dma_chan *chan = NULL;
  440. int err;
  441. /* Find a channel */
  442. mutex_lock(&dma_list_mutex);
  443. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  444. chan = private_candidate(mask, device, fn, fn_param);
  445. if (chan) {
  446. /* Found a suitable channel, try to grab, prep, and
  447. * return it. We first set DMA_PRIVATE to disable
  448. * balance_ref_count as this channel will not be
  449. * published in the general-purpose allocator
  450. */
  451. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  452. device->privatecnt++;
  453. err = dma_chan_get(chan);
  454. if (err == -ENODEV) {
  455. pr_debug("%s: %s module removed\n", __func__,
  456. dma_chan_name(chan));
  457. list_del_rcu(&device->global_node);
  458. } else if (err)
  459. pr_debug("%s: failed to get %s: (%d)\n",
  460. __func__, dma_chan_name(chan), err);
  461. else
  462. break;
  463. if (--device->privatecnt == 0)
  464. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  465. chan = NULL;
  466. }
  467. }
  468. mutex_unlock(&dma_list_mutex);
  469. pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
  470. chan ? dma_chan_name(chan) : NULL);
  471. return chan;
  472. }
  473. EXPORT_SYMBOL_GPL(__dma_request_channel);
  474. void dma_release_channel(struct dma_chan *chan)
  475. {
  476. mutex_lock(&dma_list_mutex);
  477. WARN_ONCE(chan->client_count != 1,
  478. "chan reference count %d != 1\n", chan->client_count);
  479. dma_chan_put(chan);
  480. /* drop PRIVATE cap enabled by __dma_request_channel() */
  481. if (--chan->device->privatecnt == 0)
  482. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  483. mutex_unlock(&dma_list_mutex);
  484. }
  485. EXPORT_SYMBOL_GPL(dma_release_channel);
  486. /**
  487. * dmaengine_get - register interest in dma_channels
  488. */
  489. void dmaengine_get(void)
  490. {
  491. struct dma_device *device, *_d;
  492. struct dma_chan *chan;
  493. int err;
  494. mutex_lock(&dma_list_mutex);
  495. dmaengine_ref_count++;
  496. /* try to grab channels */
  497. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  498. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  499. continue;
  500. list_for_each_entry(chan, &device->channels, device_node) {
  501. err = dma_chan_get(chan);
  502. if (err == -ENODEV) {
  503. /* module removed before we could use it */
  504. list_del_rcu(&device->global_node);
  505. break;
  506. } else if (err)
  507. pr_debug("%s: failed to get %s: (%d)\n",
  508. __func__, dma_chan_name(chan), err);
  509. }
  510. }
  511. /* if this is the first reference and there were channels
  512. * waiting we need to rebalance to get those channels
  513. * incorporated into the channel table
  514. */
  515. if (dmaengine_ref_count == 1)
  516. dma_channel_rebalance();
  517. mutex_unlock(&dma_list_mutex);
  518. }
  519. EXPORT_SYMBOL(dmaengine_get);
  520. /**
  521. * dmaengine_put - let dma drivers be removed when ref_count == 0
  522. */
  523. void dmaengine_put(void)
  524. {
  525. struct dma_device *device;
  526. struct dma_chan *chan;
  527. mutex_lock(&dma_list_mutex);
  528. dmaengine_ref_count--;
  529. BUG_ON(dmaengine_ref_count < 0);
  530. /* drop channel references */
  531. list_for_each_entry(device, &dma_device_list, global_node) {
  532. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  533. continue;
  534. list_for_each_entry(chan, &device->channels, device_node)
  535. dma_chan_put(chan);
  536. }
  537. mutex_unlock(&dma_list_mutex);
  538. }
  539. EXPORT_SYMBOL(dmaengine_put);
  540. static bool device_has_all_tx_types(struct dma_device *device)
  541. {
  542. /* A device that satisfies this test has channels that will never cause
  543. * an async_tx channel switch event as all possible operation types can
  544. * be handled.
  545. */
  546. #ifdef CONFIG_ASYNC_TX_DMA
  547. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  548. return false;
  549. #endif
  550. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  551. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  552. return false;
  553. #endif
  554. #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
  555. if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
  556. return false;
  557. #endif
  558. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  559. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  560. return false;
  561. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  562. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  563. return false;
  564. #endif
  565. #endif
  566. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  567. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  568. return false;
  569. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  570. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  571. return false;
  572. #endif
  573. #endif
  574. return true;
  575. }
  576. static int get_dma_id(struct dma_device *device)
  577. {
  578. int rc;
  579. idr_retry:
  580. if (!idr_pre_get(&dma_idr, GFP_KERNEL))
  581. return -ENOMEM;
  582. mutex_lock(&dma_list_mutex);
  583. rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
  584. mutex_unlock(&dma_list_mutex);
  585. if (rc == -EAGAIN)
  586. goto idr_retry;
  587. else if (rc != 0)
  588. return rc;
  589. return 0;
  590. }
  591. /**
  592. * dma_async_device_register - registers DMA devices found
  593. * @device: &dma_device
  594. */
  595. int dma_async_device_register(struct dma_device *device)
  596. {
  597. int chancnt = 0, rc;
  598. struct dma_chan* chan;
  599. atomic_t *idr_ref;
  600. if (!device)
  601. return -ENODEV;
  602. /* validate device routines */
  603. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  604. !device->device_prep_dma_memcpy);
  605. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  606. !device->device_prep_dma_xor);
  607. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  608. !device->device_prep_dma_xor_val);
  609. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  610. !device->device_prep_dma_pq);
  611. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  612. !device->device_prep_dma_pq_val);
  613. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  614. !device->device_prep_dma_memset);
  615. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  616. !device->device_prep_dma_interrupt);
  617. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  618. !device->device_prep_dma_sg);
  619. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  620. !device->device_prep_dma_cyclic);
  621. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  622. !device->device_control);
  623. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  624. !device->device_prep_interleaved_dma);
  625. BUG_ON(!device->device_alloc_chan_resources);
  626. BUG_ON(!device->device_free_chan_resources);
  627. BUG_ON(!device->device_tx_status);
  628. BUG_ON(!device->device_issue_pending);
  629. BUG_ON(!device->dev);
  630. /* note: this only matters in the
  631. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  632. */
  633. if (device_has_all_tx_types(device))
  634. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  635. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  636. if (!idr_ref)
  637. return -ENOMEM;
  638. rc = get_dma_id(device);
  639. if (rc != 0) {
  640. kfree(idr_ref);
  641. return rc;
  642. }
  643. atomic_set(idr_ref, 0);
  644. /* represent channels in sysfs. Probably want devs too */
  645. list_for_each_entry(chan, &device->channels, device_node) {
  646. rc = -ENOMEM;
  647. chan->local = alloc_percpu(typeof(*chan->local));
  648. if (chan->local == NULL)
  649. goto err_out;
  650. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  651. if (chan->dev == NULL) {
  652. free_percpu(chan->local);
  653. chan->local = NULL;
  654. goto err_out;
  655. }
  656. chan->chan_id = chancnt++;
  657. chan->dev->device.class = &dma_devclass;
  658. chan->dev->device.parent = device->dev;
  659. chan->dev->chan = chan;
  660. chan->dev->idr_ref = idr_ref;
  661. chan->dev->dev_id = device->dev_id;
  662. atomic_inc(idr_ref);
  663. dev_set_name(&chan->dev->device, "dma%dchan%d",
  664. device->dev_id, chan->chan_id);
  665. rc = device_register(&chan->dev->device);
  666. if (rc) {
  667. free_percpu(chan->local);
  668. chan->local = NULL;
  669. kfree(chan->dev);
  670. atomic_dec(idr_ref);
  671. goto err_out;
  672. }
  673. chan->client_count = 0;
  674. }
  675. device->chancnt = chancnt;
  676. mutex_lock(&dma_list_mutex);
  677. /* take references on public channels */
  678. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  679. list_for_each_entry(chan, &device->channels, device_node) {
  680. /* if clients are already waiting for channels we need
  681. * to take references on their behalf
  682. */
  683. if (dma_chan_get(chan) == -ENODEV) {
  684. /* note we can only get here for the first
  685. * channel as the remaining channels are
  686. * guaranteed to get a reference
  687. */
  688. rc = -ENODEV;
  689. mutex_unlock(&dma_list_mutex);
  690. goto err_out;
  691. }
  692. }
  693. list_add_tail_rcu(&device->global_node, &dma_device_list);
  694. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  695. device->privatecnt++; /* Always private */
  696. dma_channel_rebalance();
  697. mutex_unlock(&dma_list_mutex);
  698. return 0;
  699. err_out:
  700. /* if we never registered a channel just release the idr */
  701. if (atomic_read(idr_ref) == 0) {
  702. mutex_lock(&dma_list_mutex);
  703. idr_remove(&dma_idr, device->dev_id);
  704. mutex_unlock(&dma_list_mutex);
  705. kfree(idr_ref);
  706. return rc;
  707. }
  708. list_for_each_entry(chan, &device->channels, device_node) {
  709. if (chan->local == NULL)
  710. continue;
  711. mutex_lock(&dma_list_mutex);
  712. chan->dev->chan = NULL;
  713. mutex_unlock(&dma_list_mutex);
  714. device_unregister(&chan->dev->device);
  715. free_percpu(chan->local);
  716. }
  717. return rc;
  718. }
  719. EXPORT_SYMBOL(dma_async_device_register);
  720. /**
  721. * dma_async_device_unregister - unregister a DMA device
  722. * @device: &dma_device
  723. *
  724. * This routine is called by dma driver exit routines, dmaengine holds module
  725. * references to prevent it being called while channels are in use.
  726. */
  727. void dma_async_device_unregister(struct dma_device *device)
  728. {
  729. struct dma_chan *chan;
  730. mutex_lock(&dma_list_mutex);
  731. list_del_rcu(&device->global_node);
  732. dma_channel_rebalance();
  733. mutex_unlock(&dma_list_mutex);
  734. list_for_each_entry(chan, &device->channels, device_node) {
  735. WARN_ONCE(chan->client_count,
  736. "%s called while %d clients hold a reference\n",
  737. __func__, chan->client_count);
  738. mutex_lock(&dma_list_mutex);
  739. chan->dev->chan = NULL;
  740. mutex_unlock(&dma_list_mutex);
  741. device_unregister(&chan->dev->device);
  742. free_percpu(chan->local);
  743. }
  744. }
  745. EXPORT_SYMBOL(dma_async_device_unregister);
  746. /**
  747. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  748. * @chan: DMA channel to offload copy to
  749. * @dest: destination address (virtual)
  750. * @src: source address (virtual)
  751. * @len: length
  752. *
  753. * Both @dest and @src must be mappable to a bus address according to the
  754. * DMA mapping API rules for streaming mappings.
  755. * Both @dest and @src must stay memory resident (kernel memory or locked
  756. * user space pages).
  757. */
  758. dma_cookie_t
  759. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  760. void *src, size_t len)
  761. {
  762. struct dma_device *dev = chan->device;
  763. struct dma_async_tx_descriptor *tx;
  764. dma_addr_t dma_dest, dma_src;
  765. dma_cookie_t cookie;
  766. unsigned long flags;
  767. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  768. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  769. flags = DMA_CTRL_ACK |
  770. DMA_COMPL_SRC_UNMAP_SINGLE |
  771. DMA_COMPL_DEST_UNMAP_SINGLE;
  772. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  773. if (!tx) {
  774. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  775. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  776. return -ENOMEM;
  777. }
  778. tx->callback = NULL;
  779. cookie = tx->tx_submit(tx);
  780. preempt_disable();
  781. __this_cpu_add(chan->local->bytes_transferred, len);
  782. __this_cpu_inc(chan->local->memcpy_count);
  783. preempt_enable();
  784. return cookie;
  785. }
  786. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  787. /**
  788. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  789. * @chan: DMA channel to offload copy to
  790. * @page: destination page
  791. * @offset: offset in page to copy to
  792. * @kdata: source address (virtual)
  793. * @len: length
  794. *
  795. * Both @page/@offset and @kdata must be mappable to a bus address according
  796. * to the DMA mapping API rules for streaming mappings.
  797. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  798. * locked user space pages)
  799. */
  800. dma_cookie_t
  801. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  802. unsigned int offset, void *kdata, size_t len)
  803. {
  804. struct dma_device *dev = chan->device;
  805. struct dma_async_tx_descriptor *tx;
  806. dma_addr_t dma_dest, dma_src;
  807. dma_cookie_t cookie;
  808. unsigned long flags;
  809. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  810. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  811. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  812. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  813. if (!tx) {
  814. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  815. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  816. return -ENOMEM;
  817. }
  818. tx->callback = NULL;
  819. cookie = tx->tx_submit(tx);
  820. preempt_disable();
  821. __this_cpu_add(chan->local->bytes_transferred, len);
  822. __this_cpu_inc(chan->local->memcpy_count);
  823. preempt_enable();
  824. return cookie;
  825. }
  826. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  827. /**
  828. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  829. * @chan: DMA channel to offload copy to
  830. * @dest_pg: destination page
  831. * @dest_off: offset in page to copy to
  832. * @src_pg: source page
  833. * @src_off: offset in page to copy from
  834. * @len: length
  835. *
  836. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  837. * address according to the DMA mapping API rules for streaming mappings.
  838. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  839. * (kernel memory or locked user space pages).
  840. */
  841. dma_cookie_t
  842. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  843. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  844. size_t len)
  845. {
  846. struct dma_device *dev = chan->device;
  847. struct dma_async_tx_descriptor *tx;
  848. dma_addr_t dma_dest, dma_src;
  849. dma_cookie_t cookie;
  850. unsigned long flags;
  851. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  852. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  853. DMA_FROM_DEVICE);
  854. flags = DMA_CTRL_ACK;
  855. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  856. if (!tx) {
  857. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  858. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  859. return -ENOMEM;
  860. }
  861. tx->callback = NULL;
  862. cookie = tx->tx_submit(tx);
  863. preempt_disable();
  864. __this_cpu_add(chan->local->bytes_transferred, len);
  865. __this_cpu_inc(chan->local->memcpy_count);
  866. preempt_enable();
  867. return cookie;
  868. }
  869. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  870. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  871. struct dma_chan *chan)
  872. {
  873. tx->chan = chan;
  874. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  875. spin_lock_init(&tx->lock);
  876. #endif
  877. }
  878. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  879. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  880. * @tx: in-flight transaction to wait on
  881. */
  882. enum dma_status
  883. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  884. {
  885. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  886. if (!tx)
  887. return DMA_SUCCESS;
  888. while (tx->cookie == -EBUSY) {
  889. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  890. pr_err("%s timeout waiting for descriptor submission\n",
  891. __func__);
  892. return DMA_ERROR;
  893. }
  894. cpu_relax();
  895. }
  896. return dma_sync_wait(tx->chan, tx->cookie);
  897. }
  898. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  899. /* dma_run_dependencies - helper routine for dma drivers to process
  900. * (start) dependent operations on their target channel
  901. * @tx: transaction with dependencies
  902. */
  903. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  904. {
  905. struct dma_async_tx_descriptor *dep = txd_next(tx);
  906. struct dma_async_tx_descriptor *dep_next;
  907. struct dma_chan *chan;
  908. if (!dep)
  909. return;
  910. /* we'll submit tx->next now, so clear the link */
  911. txd_clear_next(tx);
  912. chan = dep->chan;
  913. /* keep submitting up until a channel switch is detected
  914. * in that case we will be called again as a result of
  915. * processing the interrupt from async_tx_channel_switch
  916. */
  917. for (; dep; dep = dep_next) {
  918. txd_lock(dep);
  919. txd_clear_parent(dep);
  920. dep_next = txd_next(dep);
  921. if (dep_next && dep_next->chan == chan)
  922. txd_clear_next(dep); /* ->next will be submitted */
  923. else
  924. dep_next = NULL; /* submit current dep and terminate */
  925. txd_unlock(dep);
  926. dep->tx_submit(dep);
  927. }
  928. chan->device->device_issue_pending(chan);
  929. }
  930. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  931. static int __init dma_bus_init(void)
  932. {
  933. return class_register(&dma_devclass);
  934. }
  935. arch_initcall(dma_bus_init);