synclink_cs.c 109 KB

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  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/module.h>
  36. #include <linux/errno.h>
  37. #include <linux/signal.h>
  38. #include <linux/sched.h>
  39. #include <linux/timer.h>
  40. #include <linux/time.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/tty.h>
  43. #include <linux/tty_flip.h>
  44. #include <linux/serial.h>
  45. #include <linux/major.h>
  46. #include <linux/string.h>
  47. #include <linux/fcntl.h>
  48. #include <linux/ptrace.h>
  49. #include <linux/ioport.h>
  50. #include <linux/mm.h>
  51. #include <linux/seq_file.h>
  52. #include <linux/slab.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/vmalloc.h>
  55. #include <linux/init.h>
  56. #include <linux/delay.h>
  57. #include <linux/ioctl.h>
  58. #include <linux/synclink.h>
  59. #include <asm/io.h>
  60. #include <asm/irq.h>
  61. #include <asm/dma.h>
  62. #include <linux/bitops.h>
  63. #include <asm/types.h>
  64. #include <linux/termios.h>
  65. #include <linux/workqueue.h>
  66. #include <linux/hdlc.h>
  67. #include <pcmcia/cistpl.h>
  68. #include <pcmcia/cisreg.h>
  69. #include <pcmcia/ds.h>
  70. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_CS_MODULE))
  71. #define SYNCLINK_GENERIC_HDLC 1
  72. #else
  73. #define SYNCLINK_GENERIC_HDLC 0
  74. #endif
  75. #define GET_USER(error,value,addr) error = get_user(value,addr)
  76. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  77. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  78. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  79. #include <asm/uaccess.h>
  80. static MGSL_PARAMS default_params = {
  81. MGSL_MODE_HDLC, /* unsigned long mode */
  82. 0, /* unsigned char loopback; */
  83. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  84. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  85. 0, /* unsigned long clock_speed; */
  86. 0xff, /* unsigned char addr_filter; */
  87. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  88. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  89. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  90. 9600, /* unsigned long data_rate; */
  91. 8, /* unsigned char data_bits; */
  92. 1, /* unsigned char stop_bits; */
  93. ASYNC_PARITY_NONE /* unsigned char parity; */
  94. };
  95. typedef struct
  96. {
  97. int count;
  98. unsigned char status;
  99. char data[1];
  100. } RXBUF;
  101. /* The queue of BH actions to be performed */
  102. #define BH_RECEIVE 1
  103. #define BH_TRANSMIT 2
  104. #define BH_STATUS 4
  105. #define IO_PIN_SHUTDOWN_LIMIT 100
  106. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  107. struct _input_signal_events {
  108. int ri_up;
  109. int ri_down;
  110. int dsr_up;
  111. int dsr_down;
  112. int dcd_up;
  113. int dcd_down;
  114. int cts_up;
  115. int cts_down;
  116. };
  117. /*
  118. * Device instance data structure
  119. */
  120. typedef struct _mgslpc_info {
  121. struct tty_port port;
  122. void *if_ptr; /* General purpose pointer (used by SPPP) */
  123. int magic;
  124. int line;
  125. struct mgsl_icount icount;
  126. int timeout;
  127. int x_char; /* xon/xoff character */
  128. unsigned char read_status_mask;
  129. unsigned char ignore_status_mask;
  130. unsigned char *tx_buf;
  131. int tx_put;
  132. int tx_get;
  133. int tx_count;
  134. /* circular list of fixed length rx buffers */
  135. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  136. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  137. int rx_put; /* index of next empty rx buffer */
  138. int rx_get; /* index of next full rx buffer */
  139. int rx_buf_size; /* size in bytes of single rx buffer */
  140. int rx_buf_count; /* total number of rx buffers */
  141. int rx_frame_count; /* number of full rx buffers */
  142. wait_queue_head_t status_event_wait_q;
  143. wait_queue_head_t event_wait_q;
  144. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  145. struct _mgslpc_info *next_device; /* device list link */
  146. unsigned short imra_value;
  147. unsigned short imrb_value;
  148. unsigned char pim_value;
  149. spinlock_t lock;
  150. struct work_struct task; /* task structure for scheduling bh */
  151. u32 max_frame_size;
  152. u32 pending_bh;
  153. bool bh_running;
  154. bool bh_requested;
  155. int dcd_chkcount; /* check counts to prevent */
  156. int cts_chkcount; /* too many IRQs if a signal */
  157. int dsr_chkcount; /* is floating */
  158. int ri_chkcount;
  159. bool rx_enabled;
  160. bool rx_overflow;
  161. bool tx_enabled;
  162. bool tx_active;
  163. bool tx_aborting;
  164. u32 idle_mode;
  165. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  166. char device_name[25]; /* device instance name */
  167. unsigned int io_base; /* base I/O address of adapter */
  168. unsigned int irq_level;
  169. MGSL_PARAMS params; /* communications parameters */
  170. unsigned char serial_signals; /* current serial signal states */
  171. bool irq_occurred; /* for diagnostics use */
  172. char testing_irq;
  173. unsigned int init_error; /* startup error (DIAGS) */
  174. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  175. bool drop_rts_on_tx_done;
  176. struct _input_signal_events input_signal_events;
  177. /* PCMCIA support */
  178. struct pcmcia_device *p_dev;
  179. int stop;
  180. /* SPPP/Cisco HDLC device parts */
  181. int netcount;
  182. spinlock_t netlock;
  183. #if SYNCLINK_GENERIC_HDLC
  184. struct net_device *netdev;
  185. #endif
  186. } MGSLPC_INFO;
  187. #define MGSLPC_MAGIC 0x5402
  188. /*
  189. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  190. */
  191. #define TXBUFSIZE 4096
  192. #define CHA 0x00 /* channel A offset */
  193. #define CHB 0x40 /* channel B offset */
  194. /*
  195. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  196. */
  197. #undef PVR
  198. #define RXFIFO 0
  199. #define TXFIFO 0
  200. #define STAR 0x20
  201. #define CMDR 0x20
  202. #define RSTA 0x21
  203. #define PRE 0x21
  204. #define MODE 0x22
  205. #define TIMR 0x23
  206. #define XAD1 0x24
  207. #define XAD2 0x25
  208. #define RAH1 0x26
  209. #define RAH2 0x27
  210. #define DAFO 0x27
  211. #define RAL1 0x28
  212. #define RFC 0x28
  213. #define RHCR 0x29
  214. #define RAL2 0x29
  215. #define RBCL 0x2a
  216. #define XBCL 0x2a
  217. #define RBCH 0x2b
  218. #define XBCH 0x2b
  219. #define CCR0 0x2c
  220. #define CCR1 0x2d
  221. #define CCR2 0x2e
  222. #define CCR3 0x2f
  223. #define VSTR 0x34
  224. #define BGR 0x34
  225. #define RLCR 0x35
  226. #define AML 0x36
  227. #define AMH 0x37
  228. #define GIS 0x38
  229. #define IVA 0x38
  230. #define IPC 0x39
  231. #define ISR 0x3a
  232. #define IMR 0x3a
  233. #define PVR 0x3c
  234. #define PIS 0x3d
  235. #define PIM 0x3d
  236. #define PCR 0x3e
  237. #define CCR4 0x3f
  238. // IMR/ISR
  239. #define IRQ_BREAK_ON BIT15 // rx break detected
  240. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  241. #define IRQ_ALLSENT BIT13 // all sent
  242. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  243. #define IRQ_TIMER BIT11 // timer interrupt
  244. #define IRQ_CTS BIT10 // CTS status change
  245. #define IRQ_TXREPEAT BIT9 // tx message repeat
  246. #define IRQ_TXFIFO BIT8 // transmit pool ready
  247. #define IRQ_RXEOM BIT7 // receive message end
  248. #define IRQ_EXITHUNT BIT6 // receive frame start
  249. #define IRQ_RXTIME BIT6 // rx char timeout
  250. #define IRQ_DCD BIT2 // carrier detect status change
  251. #define IRQ_OVERRUN BIT1 // receive frame overflow
  252. #define IRQ_RXFIFO BIT0 // receive pool full
  253. // STAR
  254. #define XFW BIT6 // transmit FIFO write enable
  255. #define CEC BIT2 // command executing
  256. #define CTS BIT1 // CTS state
  257. #define PVR_DTR BIT0
  258. #define PVR_DSR BIT1
  259. #define PVR_RI BIT2
  260. #define PVR_AUTOCTS BIT3
  261. #define PVR_RS232 0x20 /* 0010b */
  262. #define PVR_V35 0xe0 /* 1110b */
  263. #define PVR_RS422 0x40 /* 0100b */
  264. /* Register access functions */
  265. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  266. #define read_reg(info, reg) inb((info)->io_base + (reg))
  267. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  268. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  269. #define set_reg_bits(info, reg, mask) \
  270. write_reg(info, (reg), \
  271. (unsigned char) (read_reg(info, (reg)) | (mask)))
  272. #define clear_reg_bits(info, reg, mask) \
  273. write_reg(info, (reg), \
  274. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  275. /*
  276. * interrupt enable/disable routines
  277. */
  278. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  279. {
  280. if (channel == CHA) {
  281. info->imra_value |= mask;
  282. write_reg16(info, CHA + IMR, info->imra_value);
  283. } else {
  284. info->imrb_value |= mask;
  285. write_reg16(info, CHB + IMR, info->imrb_value);
  286. }
  287. }
  288. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  289. {
  290. if (channel == CHA) {
  291. info->imra_value &= ~mask;
  292. write_reg16(info, CHA + IMR, info->imra_value);
  293. } else {
  294. info->imrb_value &= ~mask;
  295. write_reg16(info, CHB + IMR, info->imrb_value);
  296. }
  297. }
  298. #define port_irq_disable(info, mask) \
  299. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  300. #define port_irq_enable(info, mask) \
  301. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  302. static void rx_start(MGSLPC_INFO *info);
  303. static void rx_stop(MGSLPC_INFO *info);
  304. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty);
  305. static void tx_stop(MGSLPC_INFO *info);
  306. static void tx_set_idle(MGSLPC_INFO *info);
  307. static void get_signals(MGSLPC_INFO *info);
  308. static void set_signals(MGSLPC_INFO *info);
  309. static void reset_device(MGSLPC_INFO *info);
  310. static void hdlc_mode(MGSLPC_INFO *info);
  311. static void async_mode(MGSLPC_INFO *info);
  312. static void tx_timeout(unsigned long context);
  313. static int carrier_raised(struct tty_port *port);
  314. static void dtr_rts(struct tty_port *port, int onoff);
  315. #if SYNCLINK_GENERIC_HDLC
  316. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  317. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  318. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  319. static int hdlcdev_init(MGSLPC_INFO *info);
  320. static void hdlcdev_exit(MGSLPC_INFO *info);
  321. #endif
  322. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  323. static bool register_test(MGSLPC_INFO *info);
  324. static bool irq_test(MGSLPC_INFO *info);
  325. static int adapter_test(MGSLPC_INFO *info);
  326. static int claim_resources(MGSLPC_INFO *info);
  327. static void release_resources(MGSLPC_INFO *info);
  328. static void mgslpc_add_device(MGSLPC_INFO *info);
  329. static void mgslpc_remove_device(MGSLPC_INFO *info);
  330. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty);
  331. static void rx_reset_buffers(MGSLPC_INFO *info);
  332. static int rx_alloc_buffers(MGSLPC_INFO *info);
  333. static void rx_free_buffers(MGSLPC_INFO *info);
  334. static irqreturn_t mgslpc_isr(int irq, void *dev_id);
  335. /*
  336. * Bottom half interrupt handlers
  337. */
  338. static void bh_handler(struct work_struct *work);
  339. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty);
  340. static void bh_status(MGSLPC_INFO *info);
  341. /*
  342. * ioctl handlers
  343. */
  344. static int tiocmget(struct tty_struct *tty);
  345. static int tiocmset(struct tty_struct *tty,
  346. unsigned int set, unsigned int clear);
  347. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  348. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  349. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params, struct tty_struct *tty);
  350. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  351. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  352. static int set_txenable(MGSLPC_INFO *info, int enable, struct tty_struct *tty);
  353. static int tx_abort(MGSLPC_INFO *info);
  354. static int set_rxenable(MGSLPC_INFO *info, int enable);
  355. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  356. static MGSLPC_INFO *mgslpc_device_list = NULL;
  357. static int mgslpc_device_count = 0;
  358. /*
  359. * Set this param to non-zero to load eax with the
  360. * .text section address and breakpoint on module load.
  361. * This is useful for use with gdb and add-symbol-file command.
  362. */
  363. static bool break_on_load=0;
  364. /*
  365. * Driver major number, defaults to zero to get auto
  366. * assigned major number. May be forced as module parameter.
  367. */
  368. static int ttymajor=0;
  369. static int debug_level = 0;
  370. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  371. module_param(break_on_load, bool, 0);
  372. module_param(ttymajor, int, 0);
  373. module_param(debug_level, int, 0);
  374. module_param_array(maxframe, int, NULL, 0);
  375. MODULE_LICENSE("GPL");
  376. static char *driver_name = "SyncLink PC Card driver";
  377. static char *driver_version = "$Revision: 4.34 $";
  378. static struct tty_driver *serial_driver;
  379. /* number of characters left in xmit buffer before we ask for more */
  380. #define WAKEUP_CHARS 256
  381. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty);
  382. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  383. /* PCMCIA prototypes */
  384. static int mgslpc_config(struct pcmcia_device *link);
  385. static void mgslpc_release(u_long arg);
  386. static void mgslpc_detach(struct pcmcia_device *p_dev);
  387. /*
  388. * 1st function defined in .text section. Calling this function in
  389. * init_module() followed by a breakpoint allows a remote debugger
  390. * (gdb) to get the .text address for the add-symbol-file command.
  391. * This allows remote debugging of dynamically loadable modules.
  392. */
  393. static void* mgslpc_get_text_ptr(void)
  394. {
  395. return mgslpc_get_text_ptr;
  396. }
  397. /**
  398. * line discipline callback wrappers
  399. *
  400. * The wrappers maintain line discipline references
  401. * while calling into the line discipline.
  402. *
  403. * ldisc_receive_buf - pass receive data to line discipline
  404. */
  405. static void ldisc_receive_buf(struct tty_struct *tty,
  406. const __u8 *data, char *flags, int count)
  407. {
  408. struct tty_ldisc *ld;
  409. if (!tty)
  410. return;
  411. ld = tty_ldisc_ref(tty);
  412. if (ld) {
  413. if (ld->ops->receive_buf)
  414. ld->ops->receive_buf(tty, data, flags, count);
  415. tty_ldisc_deref(ld);
  416. }
  417. }
  418. static const struct tty_port_operations mgslpc_port_ops = {
  419. .carrier_raised = carrier_raised,
  420. .dtr_rts = dtr_rts
  421. };
  422. static int mgslpc_probe(struct pcmcia_device *link)
  423. {
  424. MGSLPC_INFO *info;
  425. int ret;
  426. if (debug_level >= DEBUG_LEVEL_INFO)
  427. printk("mgslpc_attach\n");
  428. info = kzalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  429. if (!info) {
  430. printk("Error can't allocate device instance data\n");
  431. return -ENOMEM;
  432. }
  433. info->magic = MGSLPC_MAGIC;
  434. tty_port_init(&info->port);
  435. info->port.ops = &mgslpc_port_ops;
  436. INIT_WORK(&info->task, bh_handler);
  437. info->max_frame_size = 4096;
  438. info->port.close_delay = 5*HZ/10;
  439. info->port.closing_wait = 30*HZ;
  440. init_waitqueue_head(&info->status_event_wait_q);
  441. init_waitqueue_head(&info->event_wait_q);
  442. spin_lock_init(&info->lock);
  443. spin_lock_init(&info->netlock);
  444. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  445. info->idle_mode = HDLC_TXIDLE_FLAGS;
  446. info->imra_value = 0xffff;
  447. info->imrb_value = 0xffff;
  448. info->pim_value = 0xff;
  449. info->p_dev = link;
  450. link->priv = info;
  451. /* Initialize the struct pcmcia_device structure */
  452. ret = mgslpc_config(link);
  453. if (ret)
  454. return ret;
  455. mgslpc_add_device(info);
  456. return 0;
  457. }
  458. /* Card has been inserted.
  459. */
  460. static int mgslpc_ioprobe(struct pcmcia_device *p_dev, void *priv_data)
  461. {
  462. return pcmcia_request_io(p_dev);
  463. }
  464. static int mgslpc_config(struct pcmcia_device *link)
  465. {
  466. MGSLPC_INFO *info = link->priv;
  467. int ret;
  468. if (debug_level >= DEBUG_LEVEL_INFO)
  469. printk("mgslpc_config(0x%p)\n", link);
  470. link->config_flags |= CONF_ENABLE_IRQ | CONF_AUTO_SET_IO;
  471. ret = pcmcia_loop_config(link, mgslpc_ioprobe, NULL);
  472. if (ret != 0)
  473. goto failed;
  474. link->config_index = 8;
  475. link->config_regs = PRESENT_OPTION;
  476. ret = pcmcia_request_irq(link, mgslpc_isr);
  477. if (ret)
  478. goto failed;
  479. ret = pcmcia_enable_device(link);
  480. if (ret)
  481. goto failed;
  482. info->io_base = link->resource[0]->start;
  483. info->irq_level = link->irq;
  484. return 0;
  485. failed:
  486. mgslpc_release((u_long)link);
  487. return -ENODEV;
  488. }
  489. /* Card has been removed.
  490. * Unregister device and release PCMCIA configuration.
  491. * If device is open, postpone until it is closed.
  492. */
  493. static void mgslpc_release(u_long arg)
  494. {
  495. struct pcmcia_device *link = (struct pcmcia_device *)arg;
  496. if (debug_level >= DEBUG_LEVEL_INFO)
  497. printk("mgslpc_release(0x%p)\n", link);
  498. pcmcia_disable_device(link);
  499. }
  500. static void mgslpc_detach(struct pcmcia_device *link)
  501. {
  502. if (debug_level >= DEBUG_LEVEL_INFO)
  503. printk("mgslpc_detach(0x%p)\n", link);
  504. ((MGSLPC_INFO *)link->priv)->stop = 1;
  505. mgslpc_release((u_long)link);
  506. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  507. }
  508. static int mgslpc_suspend(struct pcmcia_device *link)
  509. {
  510. MGSLPC_INFO *info = link->priv;
  511. info->stop = 1;
  512. return 0;
  513. }
  514. static int mgslpc_resume(struct pcmcia_device *link)
  515. {
  516. MGSLPC_INFO *info = link->priv;
  517. info->stop = 0;
  518. return 0;
  519. }
  520. static inline bool mgslpc_paranoia_check(MGSLPC_INFO *info,
  521. char *name, const char *routine)
  522. {
  523. #ifdef MGSLPC_PARANOIA_CHECK
  524. static const char *badmagic =
  525. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  526. static const char *badinfo =
  527. "Warning: null mgslpc_info for (%s) in %s\n";
  528. if (!info) {
  529. printk(badinfo, name, routine);
  530. return true;
  531. }
  532. if (info->magic != MGSLPC_MAGIC) {
  533. printk(badmagic, name, routine);
  534. return true;
  535. }
  536. #else
  537. if (!info)
  538. return true;
  539. #endif
  540. return false;
  541. }
  542. #define CMD_RXFIFO BIT7 // release current rx FIFO
  543. #define CMD_RXRESET BIT6 // receiver reset
  544. #define CMD_RXFIFO_READ BIT5
  545. #define CMD_START_TIMER BIT4
  546. #define CMD_TXFIFO BIT3 // release current tx FIFO
  547. #define CMD_TXEOM BIT1 // transmit end message
  548. #define CMD_TXRESET BIT0 // transmit reset
  549. static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  550. {
  551. int i = 0;
  552. /* wait for command completion */
  553. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  554. udelay(1);
  555. if (i++ == 1000)
  556. return false;
  557. }
  558. return true;
  559. }
  560. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  561. {
  562. wait_command_complete(info, channel);
  563. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  564. }
  565. static void tx_pause(struct tty_struct *tty)
  566. {
  567. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  568. unsigned long flags;
  569. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  570. return;
  571. if (debug_level >= DEBUG_LEVEL_INFO)
  572. printk("tx_pause(%s)\n",info->device_name);
  573. spin_lock_irqsave(&info->lock,flags);
  574. if (info->tx_enabled)
  575. tx_stop(info);
  576. spin_unlock_irqrestore(&info->lock,flags);
  577. }
  578. static void tx_release(struct tty_struct *tty)
  579. {
  580. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  581. unsigned long flags;
  582. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  583. return;
  584. if (debug_level >= DEBUG_LEVEL_INFO)
  585. printk("tx_release(%s)\n",info->device_name);
  586. spin_lock_irqsave(&info->lock,flags);
  587. if (!info->tx_enabled)
  588. tx_start(info, tty);
  589. spin_unlock_irqrestore(&info->lock,flags);
  590. }
  591. /* Return next bottom half action to perform.
  592. * or 0 if nothing to do.
  593. */
  594. static int bh_action(MGSLPC_INFO *info)
  595. {
  596. unsigned long flags;
  597. int rc = 0;
  598. spin_lock_irqsave(&info->lock,flags);
  599. if (info->pending_bh & BH_RECEIVE) {
  600. info->pending_bh &= ~BH_RECEIVE;
  601. rc = BH_RECEIVE;
  602. } else if (info->pending_bh & BH_TRANSMIT) {
  603. info->pending_bh &= ~BH_TRANSMIT;
  604. rc = BH_TRANSMIT;
  605. } else if (info->pending_bh & BH_STATUS) {
  606. info->pending_bh &= ~BH_STATUS;
  607. rc = BH_STATUS;
  608. }
  609. if (!rc) {
  610. /* Mark BH routine as complete */
  611. info->bh_running = false;
  612. info->bh_requested = false;
  613. }
  614. spin_unlock_irqrestore(&info->lock,flags);
  615. return rc;
  616. }
  617. static void bh_handler(struct work_struct *work)
  618. {
  619. MGSLPC_INFO *info = container_of(work, MGSLPC_INFO, task);
  620. struct tty_struct *tty;
  621. int action;
  622. if (!info)
  623. return;
  624. if (debug_level >= DEBUG_LEVEL_BH)
  625. printk( "%s(%d):bh_handler(%s) entry\n",
  626. __FILE__,__LINE__,info->device_name);
  627. info->bh_running = true;
  628. tty = tty_port_tty_get(&info->port);
  629. while((action = bh_action(info)) != 0) {
  630. /* Process work item */
  631. if ( debug_level >= DEBUG_LEVEL_BH )
  632. printk( "%s(%d):bh_handler() work item action=%d\n",
  633. __FILE__,__LINE__,action);
  634. switch (action) {
  635. case BH_RECEIVE:
  636. while(rx_get_frame(info, tty));
  637. break;
  638. case BH_TRANSMIT:
  639. bh_transmit(info, tty);
  640. break;
  641. case BH_STATUS:
  642. bh_status(info);
  643. break;
  644. default:
  645. /* unknown work item ID */
  646. printk("Unknown work item ID=%08X!\n", action);
  647. break;
  648. }
  649. }
  650. tty_kref_put(tty);
  651. if (debug_level >= DEBUG_LEVEL_BH)
  652. printk( "%s(%d):bh_handler(%s) exit\n",
  653. __FILE__,__LINE__,info->device_name);
  654. }
  655. static void bh_transmit(MGSLPC_INFO *info, struct tty_struct *tty)
  656. {
  657. if (debug_level >= DEBUG_LEVEL_BH)
  658. printk("bh_transmit() entry on %s\n", info->device_name);
  659. if (tty)
  660. tty_wakeup(tty);
  661. }
  662. static void bh_status(MGSLPC_INFO *info)
  663. {
  664. info->ri_chkcount = 0;
  665. info->dsr_chkcount = 0;
  666. info->dcd_chkcount = 0;
  667. info->cts_chkcount = 0;
  668. }
  669. /* eom: non-zero = end of frame */
  670. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  671. {
  672. unsigned char data[2];
  673. unsigned char fifo_count, read_count, i;
  674. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  675. if (debug_level >= DEBUG_LEVEL_ISR)
  676. printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
  677. if (!info->rx_enabled)
  678. return;
  679. if (info->rx_frame_count >= info->rx_buf_count) {
  680. /* no more free buffers */
  681. issue_command(info, CHA, CMD_RXRESET);
  682. info->pending_bh |= BH_RECEIVE;
  683. info->rx_overflow = true;
  684. info->icount.buf_overrun++;
  685. return;
  686. }
  687. if (eom) {
  688. /* end of frame, get FIFO count from RBCL register */
  689. if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
  690. fifo_count = 32;
  691. } else
  692. fifo_count = 32;
  693. do {
  694. if (fifo_count == 1) {
  695. read_count = 1;
  696. data[0] = read_reg(info, CHA + RXFIFO);
  697. } else {
  698. read_count = 2;
  699. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  700. }
  701. fifo_count -= read_count;
  702. if (!fifo_count && eom)
  703. buf->status = data[--read_count];
  704. for (i = 0; i < read_count; i++) {
  705. if (buf->count >= info->max_frame_size) {
  706. /* frame too large, reset receiver and reset current buffer */
  707. issue_command(info, CHA, CMD_RXRESET);
  708. buf->count = 0;
  709. return;
  710. }
  711. *(buf->data + buf->count) = data[i];
  712. buf->count++;
  713. }
  714. } while (fifo_count);
  715. if (eom) {
  716. info->pending_bh |= BH_RECEIVE;
  717. info->rx_frame_count++;
  718. info->rx_put++;
  719. if (info->rx_put >= info->rx_buf_count)
  720. info->rx_put = 0;
  721. }
  722. issue_command(info, CHA, CMD_RXFIFO);
  723. }
  724. static void rx_ready_async(MGSLPC_INFO *info, int tcd, struct tty_struct *tty)
  725. {
  726. unsigned char data, status, flag;
  727. int fifo_count;
  728. int work = 0;
  729. struct mgsl_icount *icount = &info->icount;
  730. if (tcd) {
  731. /* early termination, get FIFO count from RBCL register */
  732. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  733. /* Zero fifo count could mean 0 or 32 bytes available.
  734. * If BIT5 of STAR is set then at least 1 byte is available.
  735. */
  736. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  737. fifo_count = 32;
  738. } else
  739. fifo_count = 32;
  740. tty_buffer_request_room(tty, fifo_count);
  741. /* Flush received async data to receive data buffer. */
  742. while (fifo_count) {
  743. data = read_reg(info, CHA + RXFIFO);
  744. status = read_reg(info, CHA + RXFIFO);
  745. fifo_count -= 2;
  746. icount->rx++;
  747. flag = TTY_NORMAL;
  748. // if no frameing/crc error then save data
  749. // BIT7:parity error
  750. // BIT6:framing error
  751. if (status & (BIT7 + BIT6)) {
  752. if (status & BIT7)
  753. icount->parity++;
  754. else
  755. icount->frame++;
  756. /* discard char if tty control flags say so */
  757. if (status & info->ignore_status_mask)
  758. continue;
  759. status &= info->read_status_mask;
  760. if (status & BIT7)
  761. flag = TTY_PARITY;
  762. else if (status & BIT6)
  763. flag = TTY_FRAME;
  764. }
  765. work += tty_insert_flip_char(tty, data, flag);
  766. }
  767. issue_command(info, CHA, CMD_RXFIFO);
  768. if (debug_level >= DEBUG_LEVEL_ISR) {
  769. printk("%s(%d):rx_ready_async",
  770. __FILE__,__LINE__);
  771. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  772. __FILE__,__LINE__,icount->rx,icount->brk,
  773. icount->parity,icount->frame,icount->overrun);
  774. }
  775. if (work)
  776. tty_flip_buffer_push(tty);
  777. }
  778. static void tx_done(MGSLPC_INFO *info, struct tty_struct *tty)
  779. {
  780. if (!info->tx_active)
  781. return;
  782. info->tx_active = false;
  783. info->tx_aborting = false;
  784. if (info->params.mode == MGSL_MODE_ASYNC)
  785. return;
  786. info->tx_count = info->tx_put = info->tx_get = 0;
  787. del_timer(&info->tx_timer);
  788. if (info->drop_rts_on_tx_done) {
  789. get_signals(info);
  790. if (info->serial_signals & SerialSignal_RTS) {
  791. info->serial_signals &= ~SerialSignal_RTS;
  792. set_signals(info);
  793. }
  794. info->drop_rts_on_tx_done = false;
  795. }
  796. #if SYNCLINK_GENERIC_HDLC
  797. if (info->netcount)
  798. hdlcdev_tx_done(info);
  799. else
  800. #endif
  801. {
  802. if (tty->stopped || tty->hw_stopped) {
  803. tx_stop(info);
  804. return;
  805. }
  806. info->pending_bh |= BH_TRANSMIT;
  807. }
  808. }
  809. static void tx_ready(MGSLPC_INFO *info, struct tty_struct *tty)
  810. {
  811. unsigned char fifo_count = 32;
  812. int c;
  813. if (debug_level >= DEBUG_LEVEL_ISR)
  814. printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
  815. if (info->params.mode == MGSL_MODE_HDLC) {
  816. if (!info->tx_active)
  817. return;
  818. } else {
  819. if (tty->stopped || tty->hw_stopped) {
  820. tx_stop(info);
  821. return;
  822. }
  823. if (!info->tx_count)
  824. info->tx_active = false;
  825. }
  826. if (!info->tx_count)
  827. return;
  828. while (info->tx_count && fifo_count) {
  829. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  830. if (c == 1) {
  831. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  832. } else {
  833. write_reg16(info, CHA + TXFIFO,
  834. *((unsigned short*)(info->tx_buf + info->tx_get)));
  835. }
  836. info->tx_count -= c;
  837. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  838. fifo_count -= c;
  839. }
  840. if (info->params.mode == MGSL_MODE_ASYNC) {
  841. if (info->tx_count < WAKEUP_CHARS)
  842. info->pending_bh |= BH_TRANSMIT;
  843. issue_command(info, CHA, CMD_TXFIFO);
  844. } else {
  845. if (info->tx_count)
  846. issue_command(info, CHA, CMD_TXFIFO);
  847. else
  848. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  849. }
  850. }
  851. static void cts_change(MGSLPC_INFO *info, struct tty_struct *tty)
  852. {
  853. get_signals(info);
  854. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  855. irq_disable(info, CHB, IRQ_CTS);
  856. info->icount.cts++;
  857. if (info->serial_signals & SerialSignal_CTS)
  858. info->input_signal_events.cts_up++;
  859. else
  860. info->input_signal_events.cts_down++;
  861. wake_up_interruptible(&info->status_event_wait_q);
  862. wake_up_interruptible(&info->event_wait_q);
  863. if (info->port.flags & ASYNC_CTS_FLOW) {
  864. if (tty->hw_stopped) {
  865. if (info->serial_signals & SerialSignal_CTS) {
  866. if (debug_level >= DEBUG_LEVEL_ISR)
  867. printk("CTS tx start...");
  868. if (tty)
  869. tty->hw_stopped = 0;
  870. tx_start(info, tty);
  871. info->pending_bh |= BH_TRANSMIT;
  872. return;
  873. }
  874. } else {
  875. if (!(info->serial_signals & SerialSignal_CTS)) {
  876. if (debug_level >= DEBUG_LEVEL_ISR)
  877. printk("CTS tx stop...");
  878. if (tty)
  879. tty->hw_stopped = 1;
  880. tx_stop(info);
  881. }
  882. }
  883. }
  884. info->pending_bh |= BH_STATUS;
  885. }
  886. static void dcd_change(MGSLPC_INFO *info, struct tty_struct *tty)
  887. {
  888. get_signals(info);
  889. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  890. irq_disable(info, CHB, IRQ_DCD);
  891. info->icount.dcd++;
  892. if (info->serial_signals & SerialSignal_DCD) {
  893. info->input_signal_events.dcd_up++;
  894. }
  895. else
  896. info->input_signal_events.dcd_down++;
  897. #if SYNCLINK_GENERIC_HDLC
  898. if (info->netcount) {
  899. if (info->serial_signals & SerialSignal_DCD)
  900. netif_carrier_on(info->netdev);
  901. else
  902. netif_carrier_off(info->netdev);
  903. }
  904. #endif
  905. wake_up_interruptible(&info->status_event_wait_q);
  906. wake_up_interruptible(&info->event_wait_q);
  907. if (info->port.flags & ASYNC_CHECK_CD) {
  908. if (debug_level >= DEBUG_LEVEL_ISR)
  909. printk("%s CD now %s...", info->device_name,
  910. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  911. if (info->serial_signals & SerialSignal_DCD)
  912. wake_up_interruptible(&info->port.open_wait);
  913. else {
  914. if (debug_level >= DEBUG_LEVEL_ISR)
  915. printk("doing serial hangup...");
  916. if (tty)
  917. tty_hangup(tty);
  918. }
  919. }
  920. info->pending_bh |= BH_STATUS;
  921. }
  922. static void dsr_change(MGSLPC_INFO *info)
  923. {
  924. get_signals(info);
  925. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  926. port_irq_disable(info, PVR_DSR);
  927. info->icount.dsr++;
  928. if (info->serial_signals & SerialSignal_DSR)
  929. info->input_signal_events.dsr_up++;
  930. else
  931. info->input_signal_events.dsr_down++;
  932. wake_up_interruptible(&info->status_event_wait_q);
  933. wake_up_interruptible(&info->event_wait_q);
  934. info->pending_bh |= BH_STATUS;
  935. }
  936. static void ri_change(MGSLPC_INFO *info)
  937. {
  938. get_signals(info);
  939. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  940. port_irq_disable(info, PVR_RI);
  941. info->icount.rng++;
  942. if (info->serial_signals & SerialSignal_RI)
  943. info->input_signal_events.ri_up++;
  944. else
  945. info->input_signal_events.ri_down++;
  946. wake_up_interruptible(&info->status_event_wait_q);
  947. wake_up_interruptible(&info->event_wait_q);
  948. info->pending_bh |= BH_STATUS;
  949. }
  950. /* Interrupt service routine entry point.
  951. *
  952. * Arguments:
  953. *
  954. * irq interrupt number that caused interrupt
  955. * dev_id device ID supplied during interrupt registration
  956. */
  957. static irqreturn_t mgslpc_isr(int dummy, void *dev_id)
  958. {
  959. MGSLPC_INFO *info = dev_id;
  960. struct tty_struct *tty;
  961. unsigned short isr;
  962. unsigned char gis, pis;
  963. int count=0;
  964. if (debug_level >= DEBUG_LEVEL_ISR)
  965. printk("mgslpc_isr(%d) entry.\n", info->irq_level);
  966. if (!(info->p_dev->_locked))
  967. return IRQ_HANDLED;
  968. tty = tty_port_tty_get(&info->port);
  969. spin_lock(&info->lock);
  970. while ((gis = read_reg(info, CHA + GIS))) {
  971. if (debug_level >= DEBUG_LEVEL_ISR)
  972. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  973. if ((gis & 0x70) || count > 1000) {
  974. printk("synclink_cs:hardware failed or ejected\n");
  975. break;
  976. }
  977. count++;
  978. if (gis & (BIT1 + BIT0)) {
  979. isr = read_reg16(info, CHB + ISR);
  980. if (isr & IRQ_DCD)
  981. dcd_change(info, tty);
  982. if (isr & IRQ_CTS)
  983. cts_change(info, tty);
  984. }
  985. if (gis & (BIT3 + BIT2))
  986. {
  987. isr = read_reg16(info, CHA + ISR);
  988. if (isr & IRQ_TIMER) {
  989. info->irq_occurred = true;
  990. irq_disable(info, CHA, IRQ_TIMER);
  991. }
  992. /* receive IRQs */
  993. if (isr & IRQ_EXITHUNT) {
  994. info->icount.exithunt++;
  995. wake_up_interruptible(&info->event_wait_q);
  996. }
  997. if (isr & IRQ_BREAK_ON) {
  998. info->icount.brk++;
  999. if (info->port.flags & ASYNC_SAK)
  1000. do_SAK(tty);
  1001. }
  1002. if (isr & IRQ_RXTIME) {
  1003. issue_command(info, CHA, CMD_RXFIFO_READ);
  1004. }
  1005. if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
  1006. if (info->params.mode == MGSL_MODE_HDLC)
  1007. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1008. else
  1009. rx_ready_async(info, isr & IRQ_RXEOM, tty);
  1010. }
  1011. /* transmit IRQs */
  1012. if (isr & IRQ_UNDERRUN) {
  1013. if (info->tx_aborting)
  1014. info->icount.txabort++;
  1015. else
  1016. info->icount.txunder++;
  1017. tx_done(info, tty);
  1018. }
  1019. else if (isr & IRQ_ALLSENT) {
  1020. info->icount.txok++;
  1021. tx_done(info, tty);
  1022. }
  1023. else if (isr & IRQ_TXFIFO)
  1024. tx_ready(info, tty);
  1025. }
  1026. if (gis & BIT7) {
  1027. pis = read_reg(info, CHA + PIS);
  1028. if (pis & BIT1)
  1029. dsr_change(info);
  1030. if (pis & BIT2)
  1031. ri_change(info);
  1032. }
  1033. }
  1034. /* Request bottom half processing if there's something
  1035. * for it to do and the bh is not already running
  1036. */
  1037. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1038. if ( debug_level >= DEBUG_LEVEL_ISR )
  1039. printk("%s(%d):%s queueing bh task.\n",
  1040. __FILE__,__LINE__,info->device_name);
  1041. schedule_work(&info->task);
  1042. info->bh_requested = true;
  1043. }
  1044. spin_unlock(&info->lock);
  1045. tty_kref_put(tty);
  1046. if (debug_level >= DEBUG_LEVEL_ISR)
  1047. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1048. __FILE__, __LINE__, info->irq_level);
  1049. return IRQ_HANDLED;
  1050. }
  1051. /* Initialize and start device.
  1052. */
  1053. static int startup(MGSLPC_INFO * info, struct tty_struct *tty)
  1054. {
  1055. int retval = 0;
  1056. if (debug_level >= DEBUG_LEVEL_INFO)
  1057. printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1058. if (info->port.flags & ASYNC_INITIALIZED)
  1059. return 0;
  1060. if (!info->tx_buf) {
  1061. /* allocate a page of memory for a transmit buffer */
  1062. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1063. if (!info->tx_buf) {
  1064. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1065. __FILE__,__LINE__,info->device_name);
  1066. return -ENOMEM;
  1067. }
  1068. }
  1069. info->pending_bh = 0;
  1070. memset(&info->icount, 0, sizeof(info->icount));
  1071. setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
  1072. /* Allocate and claim adapter resources */
  1073. retval = claim_resources(info);
  1074. /* perform existence check and diagnostics */
  1075. if ( !retval )
  1076. retval = adapter_test(info);
  1077. if ( retval ) {
  1078. if (capable(CAP_SYS_ADMIN) && tty)
  1079. set_bit(TTY_IO_ERROR, &tty->flags);
  1080. release_resources(info);
  1081. return retval;
  1082. }
  1083. /* program hardware for current parameters */
  1084. mgslpc_change_params(info, tty);
  1085. if (tty)
  1086. clear_bit(TTY_IO_ERROR, &tty->flags);
  1087. info->port.flags |= ASYNC_INITIALIZED;
  1088. return 0;
  1089. }
  1090. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1091. */
  1092. static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty)
  1093. {
  1094. unsigned long flags;
  1095. if (!(info->port.flags & ASYNC_INITIALIZED))
  1096. return;
  1097. if (debug_level >= DEBUG_LEVEL_INFO)
  1098. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1099. __FILE__,__LINE__, info->device_name );
  1100. /* clear status wait queue because status changes */
  1101. /* can't happen after shutting down the hardware */
  1102. wake_up_interruptible(&info->status_event_wait_q);
  1103. wake_up_interruptible(&info->event_wait_q);
  1104. del_timer_sync(&info->tx_timer);
  1105. if (info->tx_buf) {
  1106. free_page((unsigned long) info->tx_buf);
  1107. info->tx_buf = NULL;
  1108. }
  1109. spin_lock_irqsave(&info->lock,flags);
  1110. rx_stop(info);
  1111. tx_stop(info);
  1112. /* TODO:disable interrupts instead of reset to preserve signal states */
  1113. reset_device(info);
  1114. if (!tty || tty->termios->c_cflag & HUPCL) {
  1115. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1116. set_signals(info);
  1117. }
  1118. spin_unlock_irqrestore(&info->lock,flags);
  1119. release_resources(info);
  1120. if (tty)
  1121. set_bit(TTY_IO_ERROR, &tty->flags);
  1122. info->port.flags &= ~ASYNC_INITIALIZED;
  1123. }
  1124. static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty)
  1125. {
  1126. unsigned long flags;
  1127. spin_lock_irqsave(&info->lock,flags);
  1128. rx_stop(info);
  1129. tx_stop(info);
  1130. info->tx_count = info->tx_put = info->tx_get = 0;
  1131. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1132. hdlc_mode(info);
  1133. else
  1134. async_mode(info);
  1135. set_signals(info);
  1136. info->dcd_chkcount = 0;
  1137. info->cts_chkcount = 0;
  1138. info->ri_chkcount = 0;
  1139. info->dsr_chkcount = 0;
  1140. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1141. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1142. get_signals(info);
  1143. if (info->netcount || (tty && (tty->termios->c_cflag & CREAD)))
  1144. rx_start(info);
  1145. spin_unlock_irqrestore(&info->lock,flags);
  1146. }
  1147. /* Reconfigure adapter based on new parameters
  1148. */
  1149. static void mgslpc_change_params(MGSLPC_INFO *info, struct tty_struct *tty)
  1150. {
  1151. unsigned cflag;
  1152. int bits_per_char;
  1153. if (!tty || !tty->termios)
  1154. return;
  1155. if (debug_level >= DEBUG_LEVEL_INFO)
  1156. printk("%s(%d):mgslpc_change_params(%s)\n",
  1157. __FILE__,__LINE__, info->device_name );
  1158. cflag = tty->termios->c_cflag;
  1159. /* if B0 rate (hangup) specified then negate DTR and RTS */
  1160. /* otherwise assert DTR and RTS */
  1161. if (cflag & CBAUD)
  1162. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1163. else
  1164. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1165. /* byte size and parity */
  1166. switch (cflag & CSIZE) {
  1167. case CS5: info->params.data_bits = 5; break;
  1168. case CS6: info->params.data_bits = 6; break;
  1169. case CS7: info->params.data_bits = 7; break;
  1170. case CS8: info->params.data_bits = 8; break;
  1171. default: info->params.data_bits = 7; break;
  1172. }
  1173. if (cflag & CSTOPB)
  1174. info->params.stop_bits = 2;
  1175. else
  1176. info->params.stop_bits = 1;
  1177. info->params.parity = ASYNC_PARITY_NONE;
  1178. if (cflag & PARENB) {
  1179. if (cflag & PARODD)
  1180. info->params.parity = ASYNC_PARITY_ODD;
  1181. else
  1182. info->params.parity = ASYNC_PARITY_EVEN;
  1183. #ifdef CMSPAR
  1184. if (cflag & CMSPAR)
  1185. info->params.parity = ASYNC_PARITY_SPACE;
  1186. #endif
  1187. }
  1188. /* calculate number of jiffies to transmit a full
  1189. * FIFO (32 bytes) at specified data rate
  1190. */
  1191. bits_per_char = info->params.data_bits +
  1192. info->params.stop_bits + 1;
  1193. /* if port data rate is set to 460800 or less then
  1194. * allow tty settings to override, otherwise keep the
  1195. * current data rate.
  1196. */
  1197. if (info->params.data_rate <= 460800) {
  1198. info->params.data_rate = tty_get_baud_rate(tty);
  1199. }
  1200. if ( info->params.data_rate ) {
  1201. info->timeout = (32*HZ*bits_per_char) /
  1202. info->params.data_rate;
  1203. }
  1204. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1205. if (cflag & CRTSCTS)
  1206. info->port.flags |= ASYNC_CTS_FLOW;
  1207. else
  1208. info->port.flags &= ~ASYNC_CTS_FLOW;
  1209. if (cflag & CLOCAL)
  1210. info->port.flags &= ~ASYNC_CHECK_CD;
  1211. else
  1212. info->port.flags |= ASYNC_CHECK_CD;
  1213. /* process tty input control flags */
  1214. info->read_status_mask = 0;
  1215. if (I_INPCK(tty))
  1216. info->read_status_mask |= BIT7 | BIT6;
  1217. if (I_IGNPAR(tty))
  1218. info->ignore_status_mask |= BIT7 | BIT6;
  1219. mgslpc_program_hw(info, tty);
  1220. }
  1221. /* Add a character to the transmit buffer
  1222. */
  1223. static int mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1224. {
  1225. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1226. unsigned long flags;
  1227. if (debug_level >= DEBUG_LEVEL_INFO) {
  1228. printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
  1229. __FILE__,__LINE__,ch,info->device_name);
  1230. }
  1231. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1232. return 0;
  1233. if (!info->tx_buf)
  1234. return 0;
  1235. spin_lock_irqsave(&info->lock,flags);
  1236. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1237. if (info->tx_count < TXBUFSIZE - 1) {
  1238. info->tx_buf[info->tx_put++] = ch;
  1239. info->tx_put &= TXBUFSIZE-1;
  1240. info->tx_count++;
  1241. }
  1242. }
  1243. spin_unlock_irqrestore(&info->lock,flags);
  1244. return 1;
  1245. }
  1246. /* Enable transmitter so remaining characters in the
  1247. * transmit buffer are sent.
  1248. */
  1249. static void mgslpc_flush_chars(struct tty_struct *tty)
  1250. {
  1251. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1252. unsigned long flags;
  1253. if (debug_level >= DEBUG_LEVEL_INFO)
  1254. printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1255. __FILE__,__LINE__,info->device_name,info->tx_count);
  1256. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1257. return;
  1258. if (info->tx_count <= 0 || tty->stopped ||
  1259. tty->hw_stopped || !info->tx_buf)
  1260. return;
  1261. if (debug_level >= DEBUG_LEVEL_INFO)
  1262. printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1263. __FILE__,__LINE__,info->device_name);
  1264. spin_lock_irqsave(&info->lock,flags);
  1265. if (!info->tx_active)
  1266. tx_start(info, tty);
  1267. spin_unlock_irqrestore(&info->lock,flags);
  1268. }
  1269. /* Send a block of data
  1270. *
  1271. * Arguments:
  1272. *
  1273. * tty pointer to tty information structure
  1274. * buf pointer to buffer containing send data
  1275. * count size of send data in bytes
  1276. *
  1277. * Returns: number of characters written
  1278. */
  1279. static int mgslpc_write(struct tty_struct * tty,
  1280. const unsigned char *buf, int count)
  1281. {
  1282. int c, ret = 0;
  1283. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1284. unsigned long flags;
  1285. if (debug_level >= DEBUG_LEVEL_INFO)
  1286. printk( "%s(%d):mgslpc_write(%s) count=%d\n",
  1287. __FILE__,__LINE__,info->device_name,count);
  1288. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1289. !info->tx_buf)
  1290. goto cleanup;
  1291. if (info->params.mode == MGSL_MODE_HDLC) {
  1292. if (count > TXBUFSIZE) {
  1293. ret = -EIO;
  1294. goto cleanup;
  1295. }
  1296. if (info->tx_active)
  1297. goto cleanup;
  1298. else if (info->tx_count)
  1299. goto start;
  1300. }
  1301. for (;;) {
  1302. c = min(count,
  1303. min(TXBUFSIZE - info->tx_count - 1,
  1304. TXBUFSIZE - info->tx_put));
  1305. if (c <= 0)
  1306. break;
  1307. memcpy(info->tx_buf + info->tx_put, buf, c);
  1308. spin_lock_irqsave(&info->lock,flags);
  1309. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1310. info->tx_count += c;
  1311. spin_unlock_irqrestore(&info->lock,flags);
  1312. buf += c;
  1313. count -= c;
  1314. ret += c;
  1315. }
  1316. start:
  1317. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1318. spin_lock_irqsave(&info->lock,flags);
  1319. if (!info->tx_active)
  1320. tx_start(info, tty);
  1321. spin_unlock_irqrestore(&info->lock,flags);
  1322. }
  1323. cleanup:
  1324. if (debug_level >= DEBUG_LEVEL_INFO)
  1325. printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
  1326. __FILE__,__LINE__,info->device_name,ret);
  1327. return ret;
  1328. }
  1329. /* Return the count of free bytes in transmit buffer
  1330. */
  1331. static int mgslpc_write_room(struct tty_struct *tty)
  1332. {
  1333. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1334. int ret;
  1335. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1336. return 0;
  1337. if (info->params.mode == MGSL_MODE_HDLC) {
  1338. /* HDLC (frame oriented) mode */
  1339. if (info->tx_active)
  1340. return 0;
  1341. else
  1342. return HDLC_MAX_FRAME_SIZE;
  1343. } else {
  1344. ret = TXBUFSIZE - info->tx_count - 1;
  1345. if (ret < 0)
  1346. ret = 0;
  1347. }
  1348. if (debug_level >= DEBUG_LEVEL_INFO)
  1349. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1350. __FILE__,__LINE__, info->device_name, ret);
  1351. return ret;
  1352. }
  1353. /* Return the count of bytes in transmit buffer
  1354. */
  1355. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1356. {
  1357. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1358. int rc;
  1359. if (debug_level >= DEBUG_LEVEL_INFO)
  1360. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1361. __FILE__,__LINE__, info->device_name );
  1362. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1363. return 0;
  1364. if (info->params.mode == MGSL_MODE_HDLC)
  1365. rc = info->tx_active ? info->max_frame_size : 0;
  1366. else
  1367. rc = info->tx_count;
  1368. if (debug_level >= DEBUG_LEVEL_INFO)
  1369. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1370. __FILE__,__LINE__, info->device_name, rc);
  1371. return rc;
  1372. }
  1373. /* Discard all data in the send buffer
  1374. */
  1375. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1376. {
  1377. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1378. unsigned long flags;
  1379. if (debug_level >= DEBUG_LEVEL_INFO)
  1380. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1381. __FILE__,__LINE__, info->device_name );
  1382. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1383. return;
  1384. spin_lock_irqsave(&info->lock,flags);
  1385. info->tx_count = info->tx_put = info->tx_get = 0;
  1386. del_timer(&info->tx_timer);
  1387. spin_unlock_irqrestore(&info->lock,flags);
  1388. wake_up_interruptible(&tty->write_wait);
  1389. tty_wakeup(tty);
  1390. }
  1391. /* Send a high-priority XON/XOFF character
  1392. */
  1393. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1394. {
  1395. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1396. unsigned long flags;
  1397. if (debug_level >= DEBUG_LEVEL_INFO)
  1398. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1399. __FILE__,__LINE__, info->device_name, ch );
  1400. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1401. return;
  1402. info->x_char = ch;
  1403. if (ch) {
  1404. spin_lock_irqsave(&info->lock,flags);
  1405. if (!info->tx_enabled)
  1406. tx_start(info, tty);
  1407. spin_unlock_irqrestore(&info->lock,flags);
  1408. }
  1409. }
  1410. /* Signal remote device to throttle send data (our receive data)
  1411. */
  1412. static void mgslpc_throttle(struct tty_struct * tty)
  1413. {
  1414. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1415. unsigned long flags;
  1416. if (debug_level >= DEBUG_LEVEL_INFO)
  1417. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1418. __FILE__,__LINE__, info->device_name );
  1419. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1420. return;
  1421. if (I_IXOFF(tty))
  1422. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1423. if (tty->termios->c_cflag & CRTSCTS) {
  1424. spin_lock_irqsave(&info->lock,flags);
  1425. info->serial_signals &= ~SerialSignal_RTS;
  1426. set_signals(info);
  1427. spin_unlock_irqrestore(&info->lock,flags);
  1428. }
  1429. }
  1430. /* Signal remote device to stop throttling send data (our receive data)
  1431. */
  1432. static void mgslpc_unthrottle(struct tty_struct * tty)
  1433. {
  1434. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1435. unsigned long flags;
  1436. if (debug_level >= DEBUG_LEVEL_INFO)
  1437. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1438. __FILE__,__LINE__, info->device_name );
  1439. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1440. return;
  1441. if (I_IXOFF(tty)) {
  1442. if (info->x_char)
  1443. info->x_char = 0;
  1444. else
  1445. mgslpc_send_xchar(tty, START_CHAR(tty));
  1446. }
  1447. if (tty->termios->c_cflag & CRTSCTS) {
  1448. spin_lock_irqsave(&info->lock,flags);
  1449. info->serial_signals |= SerialSignal_RTS;
  1450. set_signals(info);
  1451. spin_unlock_irqrestore(&info->lock,flags);
  1452. }
  1453. }
  1454. /* get the current serial statistics
  1455. */
  1456. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1457. {
  1458. int err;
  1459. if (debug_level >= DEBUG_LEVEL_INFO)
  1460. printk("get_params(%s)\n", info->device_name);
  1461. if (!user_icount) {
  1462. memset(&info->icount, 0, sizeof(info->icount));
  1463. } else {
  1464. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1465. if (err)
  1466. return -EFAULT;
  1467. }
  1468. return 0;
  1469. }
  1470. /* get the current serial parameters
  1471. */
  1472. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1473. {
  1474. int err;
  1475. if (debug_level >= DEBUG_LEVEL_INFO)
  1476. printk("get_params(%s)\n", info->device_name);
  1477. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1478. if (err)
  1479. return -EFAULT;
  1480. return 0;
  1481. }
  1482. /* set the serial parameters
  1483. *
  1484. * Arguments:
  1485. *
  1486. * info pointer to device instance data
  1487. * new_params user buffer containing new serial params
  1488. *
  1489. * Returns: 0 if success, otherwise error code
  1490. */
  1491. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params, struct tty_struct *tty)
  1492. {
  1493. unsigned long flags;
  1494. MGSL_PARAMS tmp_params;
  1495. int err;
  1496. if (debug_level >= DEBUG_LEVEL_INFO)
  1497. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1498. info->device_name );
  1499. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1500. if (err) {
  1501. if ( debug_level >= DEBUG_LEVEL_INFO )
  1502. printk( "%s(%d):set_params(%s) user buffer copy failed\n",
  1503. __FILE__,__LINE__,info->device_name);
  1504. return -EFAULT;
  1505. }
  1506. spin_lock_irqsave(&info->lock,flags);
  1507. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1508. spin_unlock_irqrestore(&info->lock,flags);
  1509. mgslpc_change_params(info, tty);
  1510. return 0;
  1511. }
  1512. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1513. {
  1514. int err;
  1515. if (debug_level >= DEBUG_LEVEL_INFO)
  1516. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1517. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1518. if (err)
  1519. return -EFAULT;
  1520. return 0;
  1521. }
  1522. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1523. {
  1524. unsigned long flags;
  1525. if (debug_level >= DEBUG_LEVEL_INFO)
  1526. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1527. spin_lock_irqsave(&info->lock,flags);
  1528. info->idle_mode = idle_mode;
  1529. tx_set_idle(info);
  1530. spin_unlock_irqrestore(&info->lock,flags);
  1531. return 0;
  1532. }
  1533. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1534. {
  1535. int err;
  1536. if (debug_level >= DEBUG_LEVEL_INFO)
  1537. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1538. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1539. if (err)
  1540. return -EFAULT;
  1541. return 0;
  1542. }
  1543. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1544. {
  1545. unsigned long flags;
  1546. unsigned char val;
  1547. if (debug_level >= DEBUG_LEVEL_INFO)
  1548. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1549. spin_lock_irqsave(&info->lock,flags);
  1550. info->if_mode = if_mode;
  1551. val = read_reg(info, PVR) & 0x0f;
  1552. switch (info->if_mode)
  1553. {
  1554. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1555. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1556. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1557. }
  1558. write_reg(info, PVR, val);
  1559. spin_unlock_irqrestore(&info->lock,flags);
  1560. return 0;
  1561. }
  1562. static int set_txenable(MGSLPC_INFO * info, int enable, struct tty_struct *tty)
  1563. {
  1564. unsigned long flags;
  1565. if (debug_level >= DEBUG_LEVEL_INFO)
  1566. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1567. spin_lock_irqsave(&info->lock,flags);
  1568. if (enable) {
  1569. if (!info->tx_enabled)
  1570. tx_start(info, tty);
  1571. } else {
  1572. if (info->tx_enabled)
  1573. tx_stop(info);
  1574. }
  1575. spin_unlock_irqrestore(&info->lock,flags);
  1576. return 0;
  1577. }
  1578. static int tx_abort(MGSLPC_INFO * info)
  1579. {
  1580. unsigned long flags;
  1581. if (debug_level >= DEBUG_LEVEL_INFO)
  1582. printk("tx_abort(%s)\n", info->device_name);
  1583. spin_lock_irqsave(&info->lock,flags);
  1584. if (info->tx_active && info->tx_count &&
  1585. info->params.mode == MGSL_MODE_HDLC) {
  1586. /* clear data count so FIFO is not filled on next IRQ.
  1587. * This results in underrun and abort transmission.
  1588. */
  1589. info->tx_count = info->tx_put = info->tx_get = 0;
  1590. info->tx_aborting = true;
  1591. }
  1592. spin_unlock_irqrestore(&info->lock,flags);
  1593. return 0;
  1594. }
  1595. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1596. {
  1597. unsigned long flags;
  1598. if (debug_level >= DEBUG_LEVEL_INFO)
  1599. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1600. spin_lock_irqsave(&info->lock,flags);
  1601. if (enable) {
  1602. if (!info->rx_enabled)
  1603. rx_start(info);
  1604. } else {
  1605. if (info->rx_enabled)
  1606. rx_stop(info);
  1607. }
  1608. spin_unlock_irqrestore(&info->lock,flags);
  1609. return 0;
  1610. }
  1611. /* wait for specified event to occur
  1612. *
  1613. * Arguments: info pointer to device instance data
  1614. * mask pointer to bitmask of events to wait for
  1615. * Return Value: 0 if successful and bit mask updated with
  1616. * of events triggerred,
  1617. * otherwise error code
  1618. */
  1619. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1620. {
  1621. unsigned long flags;
  1622. int s;
  1623. int rc=0;
  1624. struct mgsl_icount cprev, cnow;
  1625. int events;
  1626. int mask;
  1627. struct _input_signal_events oldsigs, newsigs;
  1628. DECLARE_WAITQUEUE(wait, current);
  1629. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1630. if (rc)
  1631. return -EFAULT;
  1632. if (debug_level >= DEBUG_LEVEL_INFO)
  1633. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1634. spin_lock_irqsave(&info->lock,flags);
  1635. /* return immediately if state matches requested events */
  1636. get_signals(info);
  1637. s = info->serial_signals;
  1638. events = mask &
  1639. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1640. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1641. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1642. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1643. if (events) {
  1644. spin_unlock_irqrestore(&info->lock,flags);
  1645. goto exit;
  1646. }
  1647. /* save current irq counts */
  1648. cprev = info->icount;
  1649. oldsigs = info->input_signal_events;
  1650. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1651. (mask & MgslEvent_ExitHuntMode))
  1652. irq_enable(info, CHA, IRQ_EXITHUNT);
  1653. set_current_state(TASK_INTERRUPTIBLE);
  1654. add_wait_queue(&info->event_wait_q, &wait);
  1655. spin_unlock_irqrestore(&info->lock,flags);
  1656. for(;;) {
  1657. schedule();
  1658. if (signal_pending(current)) {
  1659. rc = -ERESTARTSYS;
  1660. break;
  1661. }
  1662. /* get current irq counts */
  1663. spin_lock_irqsave(&info->lock,flags);
  1664. cnow = info->icount;
  1665. newsigs = info->input_signal_events;
  1666. set_current_state(TASK_INTERRUPTIBLE);
  1667. spin_unlock_irqrestore(&info->lock,flags);
  1668. /* if no change, wait aborted for some reason */
  1669. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1670. newsigs.dsr_down == oldsigs.dsr_down &&
  1671. newsigs.dcd_up == oldsigs.dcd_up &&
  1672. newsigs.dcd_down == oldsigs.dcd_down &&
  1673. newsigs.cts_up == oldsigs.cts_up &&
  1674. newsigs.cts_down == oldsigs.cts_down &&
  1675. newsigs.ri_up == oldsigs.ri_up &&
  1676. newsigs.ri_down == oldsigs.ri_down &&
  1677. cnow.exithunt == cprev.exithunt &&
  1678. cnow.rxidle == cprev.rxidle) {
  1679. rc = -EIO;
  1680. break;
  1681. }
  1682. events = mask &
  1683. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1684. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1685. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1686. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1687. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1688. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1689. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1690. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1691. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1692. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1693. if (events)
  1694. break;
  1695. cprev = cnow;
  1696. oldsigs = newsigs;
  1697. }
  1698. remove_wait_queue(&info->event_wait_q, &wait);
  1699. set_current_state(TASK_RUNNING);
  1700. if (mask & MgslEvent_ExitHuntMode) {
  1701. spin_lock_irqsave(&info->lock,flags);
  1702. if (!waitqueue_active(&info->event_wait_q))
  1703. irq_disable(info, CHA, IRQ_EXITHUNT);
  1704. spin_unlock_irqrestore(&info->lock,flags);
  1705. }
  1706. exit:
  1707. if (rc == 0)
  1708. PUT_USER(rc, events, mask_ptr);
  1709. return rc;
  1710. }
  1711. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1712. {
  1713. unsigned long flags;
  1714. int rc;
  1715. struct mgsl_icount cprev, cnow;
  1716. DECLARE_WAITQUEUE(wait, current);
  1717. /* save current irq counts */
  1718. spin_lock_irqsave(&info->lock,flags);
  1719. cprev = info->icount;
  1720. add_wait_queue(&info->status_event_wait_q, &wait);
  1721. set_current_state(TASK_INTERRUPTIBLE);
  1722. spin_unlock_irqrestore(&info->lock,flags);
  1723. for(;;) {
  1724. schedule();
  1725. if (signal_pending(current)) {
  1726. rc = -ERESTARTSYS;
  1727. break;
  1728. }
  1729. /* get new irq counts */
  1730. spin_lock_irqsave(&info->lock,flags);
  1731. cnow = info->icount;
  1732. set_current_state(TASK_INTERRUPTIBLE);
  1733. spin_unlock_irqrestore(&info->lock,flags);
  1734. /* if no change, wait aborted for some reason */
  1735. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1736. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1737. rc = -EIO;
  1738. break;
  1739. }
  1740. /* check for change in caller specified modem input */
  1741. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1742. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1743. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1744. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1745. rc = 0;
  1746. break;
  1747. }
  1748. cprev = cnow;
  1749. }
  1750. remove_wait_queue(&info->status_event_wait_q, &wait);
  1751. set_current_state(TASK_RUNNING);
  1752. return rc;
  1753. }
  1754. /* return the state of the serial control and status signals
  1755. */
  1756. static int tiocmget(struct tty_struct *tty)
  1757. {
  1758. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1759. unsigned int result;
  1760. unsigned long flags;
  1761. spin_lock_irqsave(&info->lock,flags);
  1762. get_signals(info);
  1763. spin_unlock_irqrestore(&info->lock,flags);
  1764. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1765. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1766. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1767. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1768. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1769. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1770. if (debug_level >= DEBUG_LEVEL_INFO)
  1771. printk("%s(%d):%s tiocmget() value=%08X\n",
  1772. __FILE__,__LINE__, info->device_name, result );
  1773. return result;
  1774. }
  1775. /* set modem control signals (DTR/RTS)
  1776. */
  1777. static int tiocmset(struct tty_struct *tty,
  1778. unsigned int set, unsigned int clear)
  1779. {
  1780. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1781. unsigned long flags;
  1782. if (debug_level >= DEBUG_LEVEL_INFO)
  1783. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1784. __FILE__,__LINE__,info->device_name, set, clear);
  1785. if (set & TIOCM_RTS)
  1786. info->serial_signals |= SerialSignal_RTS;
  1787. if (set & TIOCM_DTR)
  1788. info->serial_signals |= SerialSignal_DTR;
  1789. if (clear & TIOCM_RTS)
  1790. info->serial_signals &= ~SerialSignal_RTS;
  1791. if (clear & TIOCM_DTR)
  1792. info->serial_signals &= ~SerialSignal_DTR;
  1793. spin_lock_irqsave(&info->lock,flags);
  1794. set_signals(info);
  1795. spin_unlock_irqrestore(&info->lock,flags);
  1796. return 0;
  1797. }
  1798. /* Set or clear transmit break condition
  1799. *
  1800. * Arguments: tty pointer to tty instance data
  1801. * break_state -1=set break condition, 0=clear
  1802. */
  1803. static int mgslpc_break(struct tty_struct *tty, int break_state)
  1804. {
  1805. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1806. unsigned long flags;
  1807. if (debug_level >= DEBUG_LEVEL_INFO)
  1808. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1809. __FILE__,__LINE__, info->device_name, break_state);
  1810. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1811. return -EINVAL;
  1812. spin_lock_irqsave(&info->lock,flags);
  1813. if (break_state == -1)
  1814. set_reg_bits(info, CHA+DAFO, BIT6);
  1815. else
  1816. clear_reg_bits(info, CHA+DAFO, BIT6);
  1817. spin_unlock_irqrestore(&info->lock,flags);
  1818. return 0;
  1819. }
  1820. static int mgslpc_get_icount(struct tty_struct *tty,
  1821. struct serial_icounter_struct *icount)
  1822. {
  1823. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1824. struct mgsl_icount cnow; /* kernel counter temps */
  1825. unsigned long flags;
  1826. spin_lock_irqsave(&info->lock,flags);
  1827. cnow = info->icount;
  1828. spin_unlock_irqrestore(&info->lock,flags);
  1829. icount->cts = cnow.cts;
  1830. icount->dsr = cnow.dsr;
  1831. icount->rng = cnow.rng;
  1832. icount->dcd = cnow.dcd;
  1833. icount->rx = cnow.rx;
  1834. icount->tx = cnow.tx;
  1835. icount->frame = cnow.frame;
  1836. icount->overrun = cnow.overrun;
  1837. icount->parity = cnow.parity;
  1838. icount->brk = cnow.brk;
  1839. icount->buf_overrun = cnow.buf_overrun;
  1840. return 0;
  1841. }
  1842. /* Service an IOCTL request
  1843. *
  1844. * Arguments:
  1845. *
  1846. * tty pointer to tty instance data
  1847. * cmd IOCTL command code
  1848. * arg command argument/context
  1849. *
  1850. * Return Value: 0 if success, otherwise error code
  1851. */
  1852. static int mgslpc_ioctl(struct tty_struct *tty,
  1853. unsigned int cmd, unsigned long arg)
  1854. {
  1855. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1856. void __user *argp = (void __user *)arg;
  1857. if (debug_level >= DEBUG_LEVEL_INFO)
  1858. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  1859. info->device_name, cmd );
  1860. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1861. return -ENODEV;
  1862. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1863. (cmd != TIOCMIWAIT)) {
  1864. if (tty->flags & (1 << TTY_IO_ERROR))
  1865. return -EIO;
  1866. }
  1867. switch (cmd) {
  1868. case MGSL_IOCGPARAMS:
  1869. return get_params(info, argp);
  1870. case MGSL_IOCSPARAMS:
  1871. return set_params(info, argp, tty);
  1872. case MGSL_IOCGTXIDLE:
  1873. return get_txidle(info, argp);
  1874. case MGSL_IOCSTXIDLE:
  1875. return set_txidle(info, (int)arg);
  1876. case MGSL_IOCGIF:
  1877. return get_interface(info, argp);
  1878. case MGSL_IOCSIF:
  1879. return set_interface(info,(int)arg);
  1880. case MGSL_IOCTXENABLE:
  1881. return set_txenable(info,(int)arg, tty);
  1882. case MGSL_IOCRXENABLE:
  1883. return set_rxenable(info,(int)arg);
  1884. case MGSL_IOCTXABORT:
  1885. return tx_abort(info);
  1886. case MGSL_IOCGSTATS:
  1887. return get_stats(info, argp);
  1888. case MGSL_IOCWAITEVENT:
  1889. return wait_events(info, argp);
  1890. case TIOCMIWAIT:
  1891. return modem_input_wait(info,(int)arg);
  1892. default:
  1893. return -ENOIOCTLCMD;
  1894. }
  1895. return 0;
  1896. }
  1897. /* Set new termios settings
  1898. *
  1899. * Arguments:
  1900. *
  1901. * tty pointer to tty structure
  1902. * termios pointer to buffer to hold returned old termios
  1903. */
  1904. static void mgslpc_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  1905. {
  1906. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1907. unsigned long flags;
  1908. if (debug_level >= DEBUG_LEVEL_INFO)
  1909. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
  1910. tty->driver->name );
  1911. /* just return if nothing has changed */
  1912. if ((tty->termios->c_cflag == old_termios->c_cflag)
  1913. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  1914. == RELEVANT_IFLAG(old_termios->c_iflag)))
  1915. return;
  1916. mgslpc_change_params(info, tty);
  1917. /* Handle transition to B0 status */
  1918. if (old_termios->c_cflag & CBAUD &&
  1919. !(tty->termios->c_cflag & CBAUD)) {
  1920. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1921. spin_lock_irqsave(&info->lock,flags);
  1922. set_signals(info);
  1923. spin_unlock_irqrestore(&info->lock,flags);
  1924. }
  1925. /* Handle transition away from B0 status */
  1926. if (!(old_termios->c_cflag & CBAUD) &&
  1927. tty->termios->c_cflag & CBAUD) {
  1928. info->serial_signals |= SerialSignal_DTR;
  1929. if (!(tty->termios->c_cflag & CRTSCTS) ||
  1930. !test_bit(TTY_THROTTLED, &tty->flags)) {
  1931. info->serial_signals |= SerialSignal_RTS;
  1932. }
  1933. spin_lock_irqsave(&info->lock,flags);
  1934. set_signals(info);
  1935. spin_unlock_irqrestore(&info->lock,flags);
  1936. }
  1937. /* Handle turning off CRTSCTS */
  1938. if (old_termios->c_cflag & CRTSCTS &&
  1939. !(tty->termios->c_cflag & CRTSCTS)) {
  1940. tty->hw_stopped = 0;
  1941. tx_release(tty);
  1942. }
  1943. }
  1944. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  1945. {
  1946. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1947. struct tty_port *port = &info->port;
  1948. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  1949. return;
  1950. if (debug_level >= DEBUG_LEVEL_INFO)
  1951. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  1952. __FILE__,__LINE__, info->device_name, port->count);
  1953. WARN_ON(!port->count);
  1954. if (tty_port_close_start(port, tty, filp) == 0)
  1955. goto cleanup;
  1956. if (port->flags & ASYNC_INITIALIZED)
  1957. mgslpc_wait_until_sent(tty, info->timeout);
  1958. mgslpc_flush_buffer(tty);
  1959. tty_ldisc_flush(tty);
  1960. shutdown(info, tty);
  1961. tty_port_close_end(port, tty);
  1962. tty_port_tty_set(port, NULL);
  1963. cleanup:
  1964. if (debug_level >= DEBUG_LEVEL_INFO)
  1965. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  1966. tty->driver->name, port->count);
  1967. }
  1968. /* Wait until the transmitter is empty.
  1969. */
  1970. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  1971. {
  1972. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1973. unsigned long orig_jiffies, char_time;
  1974. if (!info )
  1975. return;
  1976. if (debug_level >= DEBUG_LEVEL_INFO)
  1977. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  1978. __FILE__,__LINE__, info->device_name );
  1979. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  1980. return;
  1981. if (!(info->port.flags & ASYNC_INITIALIZED))
  1982. goto exit;
  1983. orig_jiffies = jiffies;
  1984. /* Set check interval to 1/5 of estimated time to
  1985. * send a character, and make it at least 1. The check
  1986. * interval should also be less than the timeout.
  1987. * Note: use tight timings here to satisfy the NIST-PCTS.
  1988. */
  1989. if ( info->params.data_rate ) {
  1990. char_time = info->timeout/(32 * 5);
  1991. if (!char_time)
  1992. char_time++;
  1993. } else
  1994. char_time = 1;
  1995. if (timeout)
  1996. char_time = min_t(unsigned long, char_time, timeout);
  1997. if (info->params.mode == MGSL_MODE_HDLC) {
  1998. while (info->tx_active) {
  1999. msleep_interruptible(jiffies_to_msecs(char_time));
  2000. if (signal_pending(current))
  2001. break;
  2002. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2003. break;
  2004. }
  2005. } else {
  2006. while ((info->tx_count || info->tx_active) &&
  2007. info->tx_enabled) {
  2008. msleep_interruptible(jiffies_to_msecs(char_time));
  2009. if (signal_pending(current))
  2010. break;
  2011. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2012. break;
  2013. }
  2014. }
  2015. exit:
  2016. if (debug_level >= DEBUG_LEVEL_INFO)
  2017. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2018. __FILE__,__LINE__, info->device_name );
  2019. }
  2020. /* Called by tty_hangup() when a hangup is signaled.
  2021. * This is the same as closing all open files for the port.
  2022. */
  2023. static void mgslpc_hangup(struct tty_struct *tty)
  2024. {
  2025. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2026. if (debug_level >= DEBUG_LEVEL_INFO)
  2027. printk("%s(%d):mgslpc_hangup(%s)\n",
  2028. __FILE__,__LINE__, info->device_name );
  2029. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2030. return;
  2031. mgslpc_flush_buffer(tty);
  2032. shutdown(info, tty);
  2033. tty_port_hangup(&info->port);
  2034. }
  2035. static int carrier_raised(struct tty_port *port)
  2036. {
  2037. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2038. unsigned long flags;
  2039. spin_lock_irqsave(&info->lock,flags);
  2040. get_signals(info);
  2041. spin_unlock_irqrestore(&info->lock,flags);
  2042. if (info->serial_signals & SerialSignal_DCD)
  2043. return 1;
  2044. return 0;
  2045. }
  2046. static void dtr_rts(struct tty_port *port, int onoff)
  2047. {
  2048. MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port);
  2049. unsigned long flags;
  2050. spin_lock_irqsave(&info->lock,flags);
  2051. if (onoff)
  2052. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2053. else
  2054. info->serial_signals &= ~SerialSignal_RTS + SerialSignal_DTR;
  2055. set_signals(info);
  2056. spin_unlock_irqrestore(&info->lock,flags);
  2057. }
  2058. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2059. {
  2060. MGSLPC_INFO *info;
  2061. struct tty_port *port;
  2062. int retval, line;
  2063. unsigned long flags;
  2064. /* verify range of specified line number */
  2065. line = tty->index;
  2066. if (line >= mgslpc_device_count) {
  2067. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2068. __FILE__,__LINE__,line);
  2069. return -ENODEV;
  2070. }
  2071. /* find the info structure for the specified line */
  2072. info = mgslpc_device_list;
  2073. while(info && info->line != line)
  2074. info = info->next_device;
  2075. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2076. return -ENODEV;
  2077. port = &info->port;
  2078. tty->driver_data = info;
  2079. tty_port_tty_set(port, tty);
  2080. if (debug_level >= DEBUG_LEVEL_INFO)
  2081. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2082. __FILE__,__LINE__,tty->driver->name, port->count);
  2083. /* If port is closing, signal caller to try again */
  2084. if (tty_hung_up_p(filp) || port->flags & ASYNC_CLOSING){
  2085. if (port->flags & ASYNC_CLOSING)
  2086. interruptible_sleep_on(&port->close_wait);
  2087. retval = ((port->flags & ASYNC_HUP_NOTIFY) ?
  2088. -EAGAIN : -ERESTARTSYS);
  2089. goto cleanup;
  2090. }
  2091. tty->low_latency = (port->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2092. spin_lock_irqsave(&info->netlock, flags);
  2093. if (info->netcount) {
  2094. retval = -EBUSY;
  2095. spin_unlock_irqrestore(&info->netlock, flags);
  2096. goto cleanup;
  2097. }
  2098. spin_lock(&port->lock);
  2099. port->count++;
  2100. spin_unlock(&port->lock);
  2101. spin_unlock_irqrestore(&info->netlock, flags);
  2102. if (port->count == 1) {
  2103. /* 1st open on this device, init hardware */
  2104. retval = startup(info, tty);
  2105. if (retval < 0)
  2106. goto cleanup;
  2107. }
  2108. retval = tty_port_block_til_ready(&info->port, tty, filp);
  2109. if (retval) {
  2110. if (debug_level >= DEBUG_LEVEL_INFO)
  2111. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2112. __FILE__,__LINE__, info->device_name, retval);
  2113. goto cleanup;
  2114. }
  2115. if (debug_level >= DEBUG_LEVEL_INFO)
  2116. printk("%s(%d):mgslpc_open(%s) success\n",
  2117. __FILE__,__LINE__, info->device_name);
  2118. retval = 0;
  2119. cleanup:
  2120. return retval;
  2121. }
  2122. /*
  2123. * /proc fs routines....
  2124. */
  2125. static inline void line_info(struct seq_file *m, MGSLPC_INFO *info)
  2126. {
  2127. char stat_buf[30];
  2128. unsigned long flags;
  2129. seq_printf(m, "%s:io:%04X irq:%d",
  2130. info->device_name, info->io_base, info->irq_level);
  2131. /* output current serial signal states */
  2132. spin_lock_irqsave(&info->lock,flags);
  2133. get_signals(info);
  2134. spin_unlock_irqrestore(&info->lock,flags);
  2135. stat_buf[0] = 0;
  2136. stat_buf[1] = 0;
  2137. if (info->serial_signals & SerialSignal_RTS)
  2138. strcat(stat_buf, "|RTS");
  2139. if (info->serial_signals & SerialSignal_CTS)
  2140. strcat(stat_buf, "|CTS");
  2141. if (info->serial_signals & SerialSignal_DTR)
  2142. strcat(stat_buf, "|DTR");
  2143. if (info->serial_signals & SerialSignal_DSR)
  2144. strcat(stat_buf, "|DSR");
  2145. if (info->serial_signals & SerialSignal_DCD)
  2146. strcat(stat_buf, "|CD");
  2147. if (info->serial_signals & SerialSignal_RI)
  2148. strcat(stat_buf, "|RI");
  2149. if (info->params.mode == MGSL_MODE_HDLC) {
  2150. seq_printf(m, " HDLC txok:%d rxok:%d",
  2151. info->icount.txok, info->icount.rxok);
  2152. if (info->icount.txunder)
  2153. seq_printf(m, " txunder:%d", info->icount.txunder);
  2154. if (info->icount.txabort)
  2155. seq_printf(m, " txabort:%d", info->icount.txabort);
  2156. if (info->icount.rxshort)
  2157. seq_printf(m, " rxshort:%d", info->icount.rxshort);
  2158. if (info->icount.rxlong)
  2159. seq_printf(m, " rxlong:%d", info->icount.rxlong);
  2160. if (info->icount.rxover)
  2161. seq_printf(m, " rxover:%d", info->icount.rxover);
  2162. if (info->icount.rxcrc)
  2163. seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
  2164. } else {
  2165. seq_printf(m, " ASYNC tx:%d rx:%d",
  2166. info->icount.tx, info->icount.rx);
  2167. if (info->icount.frame)
  2168. seq_printf(m, " fe:%d", info->icount.frame);
  2169. if (info->icount.parity)
  2170. seq_printf(m, " pe:%d", info->icount.parity);
  2171. if (info->icount.brk)
  2172. seq_printf(m, " brk:%d", info->icount.brk);
  2173. if (info->icount.overrun)
  2174. seq_printf(m, " oe:%d", info->icount.overrun);
  2175. }
  2176. /* Append serial signal status to end */
  2177. seq_printf(m, " %s\n", stat_buf+1);
  2178. seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2179. info->tx_active,info->bh_requested,info->bh_running,
  2180. info->pending_bh);
  2181. }
  2182. /* Called to print information about devices
  2183. */
  2184. static int mgslpc_proc_show(struct seq_file *m, void *v)
  2185. {
  2186. MGSLPC_INFO *info;
  2187. seq_printf(m, "synclink driver:%s\n", driver_version);
  2188. info = mgslpc_device_list;
  2189. while( info ) {
  2190. line_info(m, info);
  2191. info = info->next_device;
  2192. }
  2193. return 0;
  2194. }
  2195. static int mgslpc_proc_open(struct inode *inode, struct file *file)
  2196. {
  2197. return single_open(file, mgslpc_proc_show, NULL);
  2198. }
  2199. static const struct file_operations mgslpc_proc_fops = {
  2200. .owner = THIS_MODULE,
  2201. .open = mgslpc_proc_open,
  2202. .read = seq_read,
  2203. .llseek = seq_lseek,
  2204. .release = single_release,
  2205. };
  2206. static int rx_alloc_buffers(MGSLPC_INFO *info)
  2207. {
  2208. /* each buffer has header and data */
  2209. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2210. /* calculate total allocation size for 8 buffers */
  2211. info->rx_buf_total_size = info->rx_buf_size * 8;
  2212. /* limit total allocated memory */
  2213. if (info->rx_buf_total_size > 0x10000)
  2214. info->rx_buf_total_size = 0x10000;
  2215. /* calculate number of buffers */
  2216. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2217. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2218. if (info->rx_buf == NULL)
  2219. return -ENOMEM;
  2220. rx_reset_buffers(info);
  2221. return 0;
  2222. }
  2223. static void rx_free_buffers(MGSLPC_INFO *info)
  2224. {
  2225. kfree(info->rx_buf);
  2226. info->rx_buf = NULL;
  2227. }
  2228. static int claim_resources(MGSLPC_INFO *info)
  2229. {
  2230. if (rx_alloc_buffers(info) < 0 ) {
  2231. printk( "Can't allocate rx buffer %s\n", info->device_name);
  2232. release_resources(info);
  2233. return -ENODEV;
  2234. }
  2235. return 0;
  2236. }
  2237. static void release_resources(MGSLPC_INFO *info)
  2238. {
  2239. if (debug_level >= DEBUG_LEVEL_INFO)
  2240. printk("release_resources(%s)\n", info->device_name);
  2241. rx_free_buffers(info);
  2242. }
  2243. /* Add the specified device instance data structure to the
  2244. * global linked list of devices and increment the device count.
  2245. *
  2246. * Arguments: info pointer to device instance data
  2247. */
  2248. static void mgslpc_add_device(MGSLPC_INFO *info)
  2249. {
  2250. info->next_device = NULL;
  2251. info->line = mgslpc_device_count;
  2252. sprintf(info->device_name,"ttySLP%d",info->line);
  2253. if (info->line < MAX_DEVICE_COUNT) {
  2254. if (maxframe[info->line])
  2255. info->max_frame_size = maxframe[info->line];
  2256. }
  2257. mgslpc_device_count++;
  2258. if (!mgslpc_device_list)
  2259. mgslpc_device_list = info;
  2260. else {
  2261. MGSLPC_INFO *current_dev = mgslpc_device_list;
  2262. while( current_dev->next_device )
  2263. current_dev = current_dev->next_device;
  2264. current_dev->next_device = info;
  2265. }
  2266. if (info->max_frame_size < 4096)
  2267. info->max_frame_size = 4096;
  2268. else if (info->max_frame_size > 65535)
  2269. info->max_frame_size = 65535;
  2270. printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2271. info->device_name, info->io_base, info->irq_level);
  2272. #if SYNCLINK_GENERIC_HDLC
  2273. hdlcdev_init(info);
  2274. #endif
  2275. }
  2276. static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2277. {
  2278. MGSLPC_INFO *info = mgslpc_device_list;
  2279. MGSLPC_INFO *last = NULL;
  2280. while(info) {
  2281. if (info == remove_info) {
  2282. if (last)
  2283. last->next_device = info->next_device;
  2284. else
  2285. mgslpc_device_list = info->next_device;
  2286. #if SYNCLINK_GENERIC_HDLC
  2287. hdlcdev_exit(info);
  2288. #endif
  2289. release_resources(info);
  2290. kfree(info);
  2291. mgslpc_device_count--;
  2292. return;
  2293. }
  2294. last = info;
  2295. info = info->next_device;
  2296. }
  2297. }
  2298. static const struct pcmcia_device_id mgslpc_ids[] = {
  2299. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2300. PCMCIA_DEVICE_NULL
  2301. };
  2302. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2303. static struct pcmcia_driver mgslpc_driver = {
  2304. .owner = THIS_MODULE,
  2305. .name = "synclink_cs",
  2306. .probe = mgslpc_probe,
  2307. .remove = mgslpc_detach,
  2308. .id_table = mgslpc_ids,
  2309. .suspend = mgslpc_suspend,
  2310. .resume = mgslpc_resume,
  2311. };
  2312. static const struct tty_operations mgslpc_ops = {
  2313. .open = mgslpc_open,
  2314. .close = mgslpc_close,
  2315. .write = mgslpc_write,
  2316. .put_char = mgslpc_put_char,
  2317. .flush_chars = mgslpc_flush_chars,
  2318. .write_room = mgslpc_write_room,
  2319. .chars_in_buffer = mgslpc_chars_in_buffer,
  2320. .flush_buffer = mgslpc_flush_buffer,
  2321. .ioctl = mgslpc_ioctl,
  2322. .throttle = mgslpc_throttle,
  2323. .unthrottle = mgslpc_unthrottle,
  2324. .send_xchar = mgslpc_send_xchar,
  2325. .break_ctl = mgslpc_break,
  2326. .wait_until_sent = mgslpc_wait_until_sent,
  2327. .set_termios = mgslpc_set_termios,
  2328. .stop = tx_pause,
  2329. .start = tx_release,
  2330. .hangup = mgslpc_hangup,
  2331. .tiocmget = tiocmget,
  2332. .tiocmset = tiocmset,
  2333. .get_icount = mgslpc_get_icount,
  2334. .proc_fops = &mgslpc_proc_fops,
  2335. };
  2336. static void synclink_cs_cleanup(void)
  2337. {
  2338. int rc;
  2339. while(mgslpc_device_list)
  2340. mgslpc_remove_device(mgslpc_device_list);
  2341. if (serial_driver) {
  2342. if ((rc = tty_unregister_driver(serial_driver)))
  2343. printk("%s(%d) failed to unregister tty driver err=%d\n",
  2344. __FILE__,__LINE__,rc);
  2345. put_tty_driver(serial_driver);
  2346. }
  2347. pcmcia_unregister_driver(&mgslpc_driver);
  2348. }
  2349. static int __init synclink_cs_init(void)
  2350. {
  2351. int rc;
  2352. if (break_on_load) {
  2353. mgslpc_get_text_ptr();
  2354. BREAKPOINT();
  2355. }
  2356. if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
  2357. return rc;
  2358. serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
  2359. if (!serial_driver) {
  2360. rc = -ENOMEM;
  2361. goto error;
  2362. }
  2363. /* Initialize the tty_driver structure */
  2364. serial_driver->driver_name = "synclink_cs";
  2365. serial_driver->name = "ttySLP";
  2366. serial_driver->major = ttymajor;
  2367. serial_driver->minor_start = 64;
  2368. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2369. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2370. serial_driver->init_termios = tty_std_termios;
  2371. serial_driver->init_termios.c_cflag =
  2372. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2373. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  2374. tty_set_operations(serial_driver, &mgslpc_ops);
  2375. if ((rc = tty_register_driver(serial_driver)) < 0) {
  2376. printk("%s(%d):Couldn't register serial driver\n",
  2377. __FILE__,__LINE__);
  2378. put_tty_driver(serial_driver);
  2379. serial_driver = NULL;
  2380. goto error;
  2381. }
  2382. printk("%s %s, tty major#%d\n",
  2383. driver_name, driver_version,
  2384. serial_driver->major);
  2385. return 0;
  2386. error:
  2387. synclink_cs_cleanup();
  2388. return rc;
  2389. }
  2390. static void __exit synclink_cs_exit(void)
  2391. {
  2392. synclink_cs_cleanup();
  2393. }
  2394. module_init(synclink_cs_init);
  2395. module_exit(synclink_cs_exit);
  2396. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2397. {
  2398. unsigned int M, N;
  2399. unsigned char val;
  2400. /* note:standard BRG mode is broken in V3.2 chip
  2401. * so enhanced mode is always used
  2402. */
  2403. if (rate) {
  2404. N = 3686400 / rate;
  2405. if (!N)
  2406. N = 1;
  2407. N >>= 1;
  2408. for (M = 1; N > 64 && M < 16; M++)
  2409. N >>= 1;
  2410. N--;
  2411. /* BGR[5..0] = N
  2412. * BGR[9..6] = M
  2413. * BGR[7..0] contained in BGR register
  2414. * BGR[9..8] contained in CCR2[7..6]
  2415. * divisor = (N+1)*2^M
  2416. *
  2417. * Note: M *must* not be zero (causes asymetric duty cycle)
  2418. */
  2419. write_reg(info, (unsigned char) (channel + BGR),
  2420. (unsigned char) ((M << 6) + N));
  2421. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2422. val |= ((M << 4) & 0xc0);
  2423. write_reg(info, (unsigned char) (channel + CCR2), val);
  2424. }
  2425. }
  2426. /* Enabled the AUX clock output at the specified frequency.
  2427. */
  2428. static void enable_auxclk(MGSLPC_INFO *info)
  2429. {
  2430. unsigned char val;
  2431. /* MODE
  2432. *
  2433. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2434. * 05 ADM Address Mode, 0 = no addr recognition
  2435. * 04 TMD Timer Mode, 0 = external
  2436. * 03 RAC Receiver Active, 0 = inactive
  2437. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2438. * 01 TRS Timer Resolution, 1=512
  2439. * 00 TLP Test Loop, 0 = no loop
  2440. *
  2441. * 1000 0010
  2442. */
  2443. val = 0x82;
  2444. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2445. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2446. val |= BIT2;
  2447. write_reg(info, CHB + MODE, val);
  2448. /* CCR0
  2449. *
  2450. * 07 PU Power Up, 1=active, 0=power down
  2451. * 06 MCE Master Clock Enable, 1=enabled
  2452. * 05 Reserved, 0
  2453. * 04..02 SC[2..0] Encoding
  2454. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2455. *
  2456. * 11000000
  2457. */
  2458. write_reg(info, CHB + CCR0, 0xc0);
  2459. /* CCR1
  2460. *
  2461. * 07 SFLG Shared Flag, 0 = disable shared flags
  2462. * 06 GALP Go Active On Loop, 0 = not used
  2463. * 05 GLP Go On Loop, 0 = not used
  2464. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2465. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2466. * 02..00 CM[2..0] Clock Mode
  2467. *
  2468. * 0001 0111
  2469. */
  2470. write_reg(info, CHB + CCR1, 0x17);
  2471. /* CCR2 (Channel B)
  2472. *
  2473. * 07..06 BGR[9..8] Baud rate bits 9..8
  2474. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2475. * 04 SSEL Clock source select, 1=submode b
  2476. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2477. * 02 RWX Read/Write Exchange 0=disabled
  2478. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2479. * 00 DIV, data inversion 0=disabled, 1=enabled
  2480. *
  2481. * 0011 1000
  2482. */
  2483. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2484. write_reg(info, CHB + CCR2, 0x38);
  2485. else
  2486. write_reg(info, CHB + CCR2, 0x30);
  2487. /* CCR4
  2488. *
  2489. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2490. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2491. * 05 TST1 Test Pin, 0=normal operation
  2492. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2493. * 03..02 Reserved, must be 0
  2494. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2495. *
  2496. * 0101 0000
  2497. */
  2498. write_reg(info, CHB + CCR4, 0x50);
  2499. /* if auxclk not enabled, set internal BRG so
  2500. * CTS transitions can be detected (requires TxC)
  2501. */
  2502. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2503. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2504. else
  2505. mgslpc_set_rate(info, CHB, 921600);
  2506. }
  2507. static void loopback_enable(MGSLPC_INFO *info)
  2508. {
  2509. unsigned char val;
  2510. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2511. val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
  2512. write_reg(info, CHA + CCR1, val);
  2513. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2514. val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
  2515. write_reg(info, CHA + CCR2, val);
  2516. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2517. if (info->params.clock_speed)
  2518. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2519. else
  2520. mgslpc_set_rate(info, CHA, 1843200);
  2521. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2522. val = read_reg(info, CHA + MODE) | BIT0;
  2523. write_reg(info, CHA + MODE, val);
  2524. }
  2525. static void hdlc_mode(MGSLPC_INFO *info)
  2526. {
  2527. unsigned char val;
  2528. unsigned char clkmode, clksubmode;
  2529. /* disable all interrupts */
  2530. irq_disable(info, CHA, 0xffff);
  2531. irq_disable(info, CHB, 0xffff);
  2532. port_irq_disable(info, 0xff);
  2533. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2534. clkmode = clksubmode = 0;
  2535. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2536. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2537. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2538. clkmode = 7;
  2539. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2540. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2541. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2542. clkmode = 7;
  2543. clksubmode = 1;
  2544. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2545. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2546. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2547. clkmode = 6;
  2548. clksubmode = 1;
  2549. } else {
  2550. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2551. clkmode = 6;
  2552. }
  2553. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2554. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2555. clksubmode = 1;
  2556. }
  2557. /* MODE
  2558. *
  2559. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2560. * 05 ADM Address Mode, 0 = no addr recognition
  2561. * 04 TMD Timer Mode, 0 = external
  2562. * 03 RAC Receiver Active, 0 = inactive
  2563. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2564. * 01 TRS Timer Resolution, 1=512
  2565. * 00 TLP Test Loop, 0 = no loop
  2566. *
  2567. * 1000 0010
  2568. */
  2569. val = 0x82;
  2570. if (info->params.loopback)
  2571. val |= BIT0;
  2572. /* preserve RTS state */
  2573. if (info->serial_signals & SerialSignal_RTS)
  2574. val |= BIT2;
  2575. write_reg(info, CHA + MODE, val);
  2576. /* CCR0
  2577. *
  2578. * 07 PU Power Up, 1=active, 0=power down
  2579. * 06 MCE Master Clock Enable, 1=enabled
  2580. * 05 Reserved, 0
  2581. * 04..02 SC[2..0] Encoding
  2582. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2583. *
  2584. * 11000000
  2585. */
  2586. val = 0xc0;
  2587. switch (info->params.encoding)
  2588. {
  2589. case HDLC_ENCODING_NRZI:
  2590. val |= BIT3;
  2591. break;
  2592. case HDLC_ENCODING_BIPHASE_SPACE:
  2593. val |= BIT4;
  2594. break; // FM0
  2595. case HDLC_ENCODING_BIPHASE_MARK:
  2596. val |= BIT4 + BIT2;
  2597. break; // FM1
  2598. case HDLC_ENCODING_BIPHASE_LEVEL:
  2599. val |= BIT4 + BIT3;
  2600. break; // Manchester
  2601. }
  2602. write_reg(info, CHA + CCR0, val);
  2603. /* CCR1
  2604. *
  2605. * 07 SFLG Shared Flag, 0 = disable shared flags
  2606. * 06 GALP Go Active On Loop, 0 = not used
  2607. * 05 GLP Go On Loop, 0 = not used
  2608. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2609. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2610. * 02..00 CM[2..0] Clock Mode
  2611. *
  2612. * 0001 0000
  2613. */
  2614. val = 0x10 + clkmode;
  2615. write_reg(info, CHA + CCR1, val);
  2616. /* CCR2
  2617. *
  2618. * 07..06 BGR[9..8] Baud rate bits 9..8
  2619. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2620. * 04 SSEL Clock source select, 1=submode b
  2621. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2622. * 02 RWX Read/Write Exchange 0=disabled
  2623. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2624. * 00 DIV, data inversion 0=disabled, 1=enabled
  2625. *
  2626. * 0000 0000
  2627. */
  2628. val = 0x00;
  2629. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2630. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2631. val |= BIT5;
  2632. if (clksubmode)
  2633. val |= BIT4;
  2634. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2635. val |= BIT1;
  2636. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2637. val |= BIT0;
  2638. write_reg(info, CHA + CCR2, val);
  2639. /* CCR3
  2640. *
  2641. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2642. * 05 EPT Enable preamble transmission, 1=enabled
  2643. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2644. * 03 CRL CRC Reset Level, 0=FFFF
  2645. * 02 RCRC Rx CRC 0=On 1=Off
  2646. * 01 TCRC Tx CRC 0=On 1=Off
  2647. * 00 PSD DPLL Phase Shift Disable
  2648. *
  2649. * 0000 0000
  2650. */
  2651. val = 0x00;
  2652. if (info->params.crc_type == HDLC_CRC_NONE)
  2653. val |= BIT2 + BIT1;
  2654. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2655. val |= BIT5;
  2656. switch (info->params.preamble_length)
  2657. {
  2658. case HDLC_PREAMBLE_LENGTH_16BITS:
  2659. val |= BIT6;
  2660. break;
  2661. case HDLC_PREAMBLE_LENGTH_32BITS:
  2662. val |= BIT6;
  2663. break;
  2664. case HDLC_PREAMBLE_LENGTH_64BITS:
  2665. val |= BIT7 + BIT6;
  2666. break;
  2667. }
  2668. write_reg(info, CHA + CCR3, val);
  2669. /* PRE - Preamble pattern */
  2670. val = 0;
  2671. switch (info->params.preamble)
  2672. {
  2673. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2674. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2675. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2676. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2677. }
  2678. write_reg(info, CHA + PRE, val);
  2679. /* CCR4
  2680. *
  2681. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2682. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2683. * 05 TST1 Test Pin, 0=normal operation
  2684. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2685. * 03..02 Reserved, must be 0
  2686. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2687. *
  2688. * 0101 0000
  2689. */
  2690. val = 0x50;
  2691. write_reg(info, CHA + CCR4, val);
  2692. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2693. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2694. else
  2695. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2696. /* RLCR Receive length check register
  2697. *
  2698. * 7 1=enable receive length check
  2699. * 6..0 Max frame length = (RL + 1) * 32
  2700. */
  2701. write_reg(info, CHA + RLCR, 0);
  2702. /* XBCH Transmit Byte Count High
  2703. *
  2704. * 07 DMA mode, 0 = interrupt driven
  2705. * 06 NRM, 0=ABM (ignored)
  2706. * 05 CAS Carrier Auto Start
  2707. * 04 XC Transmit Continuously (ignored)
  2708. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2709. *
  2710. * 0000 0000
  2711. */
  2712. val = 0x00;
  2713. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2714. val |= BIT5;
  2715. write_reg(info, CHA + XBCH, val);
  2716. enable_auxclk(info);
  2717. if (info->params.loopback || info->testing_irq)
  2718. loopback_enable(info);
  2719. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2720. {
  2721. irq_enable(info, CHB, IRQ_CTS);
  2722. /* PVR[3] 1=AUTO CTS active */
  2723. set_reg_bits(info, CHA + PVR, BIT3);
  2724. } else
  2725. clear_reg_bits(info, CHA + PVR, BIT3);
  2726. irq_enable(info, CHA,
  2727. IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
  2728. IRQ_UNDERRUN + IRQ_TXFIFO);
  2729. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2730. wait_command_complete(info, CHA);
  2731. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2732. /* Master clock mode enabled above to allow reset commands
  2733. * to complete even if no data clocks are present.
  2734. *
  2735. * Disable master clock mode for normal communications because
  2736. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2737. * IRQ when in master clock mode.
  2738. *
  2739. * Leave master clock mode enabled for IRQ test because the
  2740. * timer IRQ used by the test can only happen in master clock mode.
  2741. */
  2742. if (!info->testing_irq)
  2743. clear_reg_bits(info, CHA + CCR0, BIT6);
  2744. tx_set_idle(info);
  2745. tx_stop(info);
  2746. rx_stop(info);
  2747. }
  2748. static void rx_stop(MGSLPC_INFO *info)
  2749. {
  2750. if (debug_level >= DEBUG_LEVEL_ISR)
  2751. printk("%s(%d):rx_stop(%s)\n",
  2752. __FILE__,__LINE__, info->device_name );
  2753. /* MODE:03 RAC Receiver Active, 0=inactive */
  2754. clear_reg_bits(info, CHA + MODE, BIT3);
  2755. info->rx_enabled = false;
  2756. info->rx_overflow = false;
  2757. }
  2758. static void rx_start(MGSLPC_INFO *info)
  2759. {
  2760. if (debug_level >= DEBUG_LEVEL_ISR)
  2761. printk("%s(%d):rx_start(%s)\n",
  2762. __FILE__,__LINE__, info->device_name );
  2763. rx_reset_buffers(info);
  2764. info->rx_enabled = false;
  2765. info->rx_overflow = false;
  2766. /* MODE:03 RAC Receiver Active, 1=active */
  2767. set_reg_bits(info, CHA + MODE, BIT3);
  2768. info->rx_enabled = true;
  2769. }
  2770. static void tx_start(MGSLPC_INFO *info, struct tty_struct *tty)
  2771. {
  2772. if (debug_level >= DEBUG_LEVEL_ISR)
  2773. printk("%s(%d):tx_start(%s)\n",
  2774. __FILE__,__LINE__, info->device_name );
  2775. if (info->tx_count) {
  2776. /* If auto RTS enabled and RTS is inactive, then assert */
  2777. /* RTS and set a flag indicating that the driver should */
  2778. /* negate RTS when the transmission completes. */
  2779. info->drop_rts_on_tx_done = false;
  2780. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  2781. get_signals(info);
  2782. if (!(info->serial_signals & SerialSignal_RTS)) {
  2783. info->serial_signals |= SerialSignal_RTS;
  2784. set_signals(info);
  2785. info->drop_rts_on_tx_done = true;
  2786. }
  2787. }
  2788. if (info->params.mode == MGSL_MODE_ASYNC) {
  2789. if (!info->tx_active) {
  2790. info->tx_active = true;
  2791. tx_ready(info, tty);
  2792. }
  2793. } else {
  2794. info->tx_active = true;
  2795. tx_ready(info, tty);
  2796. mod_timer(&info->tx_timer, jiffies +
  2797. msecs_to_jiffies(5000));
  2798. }
  2799. }
  2800. if (!info->tx_enabled)
  2801. info->tx_enabled = true;
  2802. }
  2803. static void tx_stop(MGSLPC_INFO *info)
  2804. {
  2805. if (debug_level >= DEBUG_LEVEL_ISR)
  2806. printk("%s(%d):tx_stop(%s)\n",
  2807. __FILE__,__LINE__, info->device_name );
  2808. del_timer(&info->tx_timer);
  2809. info->tx_enabled = false;
  2810. info->tx_active = false;
  2811. }
  2812. /* Reset the adapter to a known state and prepare it for further use.
  2813. */
  2814. static void reset_device(MGSLPC_INFO *info)
  2815. {
  2816. /* power up both channels (set BIT7) */
  2817. write_reg(info, CHA + CCR0, 0x80);
  2818. write_reg(info, CHB + CCR0, 0x80);
  2819. write_reg(info, CHA + MODE, 0);
  2820. write_reg(info, CHB + MODE, 0);
  2821. /* disable all interrupts */
  2822. irq_disable(info, CHA, 0xffff);
  2823. irq_disable(info, CHB, 0xffff);
  2824. port_irq_disable(info, 0xff);
  2825. /* PCR Port Configuration Register
  2826. *
  2827. * 07..04 DEC[3..0] Serial I/F select outputs
  2828. * 03 output, 1=AUTO CTS control enabled
  2829. * 02 RI Ring Indicator input 0=active
  2830. * 01 DSR input 0=active
  2831. * 00 DTR output 0=active
  2832. *
  2833. * 0000 0110
  2834. */
  2835. write_reg(info, PCR, 0x06);
  2836. /* PVR Port Value Register
  2837. *
  2838. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  2839. * 03 AUTO CTS output 1=enabled
  2840. * 02 RI Ring Indicator input
  2841. * 01 DSR input
  2842. * 00 DTR output (1=inactive)
  2843. *
  2844. * 0000 0001
  2845. */
  2846. // write_reg(info, PVR, PVR_DTR);
  2847. /* IPC Interrupt Port Configuration
  2848. *
  2849. * 07 VIS 1=Masked interrupts visible
  2850. * 06..05 Reserved, 0
  2851. * 04..03 SLA Slave address, 00 ignored
  2852. * 02 CASM Cascading Mode, 1=daisy chain
  2853. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  2854. *
  2855. * 0000 0101
  2856. */
  2857. write_reg(info, IPC, 0x05);
  2858. }
  2859. static void async_mode(MGSLPC_INFO *info)
  2860. {
  2861. unsigned char val;
  2862. /* disable all interrupts */
  2863. irq_disable(info, CHA, 0xffff);
  2864. irq_disable(info, CHB, 0xffff);
  2865. port_irq_disable(info, 0xff);
  2866. /* MODE
  2867. *
  2868. * 07 Reserved, 0
  2869. * 06 FRTS RTS State, 0=active
  2870. * 05 FCTS Flow Control on CTS
  2871. * 04 FLON Flow Control Enable
  2872. * 03 RAC Receiver Active, 0 = inactive
  2873. * 02 RTS 0=Auto RTS, 1=manual RTS
  2874. * 01 TRS Timer Resolution, 1=512
  2875. * 00 TLP Test Loop, 0 = no loop
  2876. *
  2877. * 0000 0110
  2878. */
  2879. val = 0x06;
  2880. if (info->params.loopback)
  2881. val |= BIT0;
  2882. /* preserve RTS state */
  2883. if (!(info->serial_signals & SerialSignal_RTS))
  2884. val |= BIT6;
  2885. write_reg(info, CHA + MODE, val);
  2886. /* CCR0
  2887. *
  2888. * 07 PU Power Up, 1=active, 0=power down
  2889. * 06 MCE Master Clock Enable, 1=enabled
  2890. * 05 Reserved, 0
  2891. * 04..02 SC[2..0] Encoding, 000=NRZ
  2892. * 01..00 SM[1..0] Serial Mode, 11=Async
  2893. *
  2894. * 1000 0011
  2895. */
  2896. write_reg(info, CHA + CCR0, 0x83);
  2897. /* CCR1
  2898. *
  2899. * 07..05 Reserved, 0
  2900. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2901. * 03 BCR Bit Clock Rate, 1=16x
  2902. * 02..00 CM[2..0] Clock Mode, 111=BRG
  2903. *
  2904. * 0001 1111
  2905. */
  2906. write_reg(info, CHA + CCR1, 0x1f);
  2907. /* CCR2 (channel A)
  2908. *
  2909. * 07..06 BGR[9..8] Baud rate bits 9..8
  2910. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2911. * 04 SSEL Clock source select, 1=submode b
  2912. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2913. * 02 RWX Read/Write Exchange 0=disabled
  2914. * 01 Reserved, 0
  2915. * 00 DIV, data inversion 0=disabled, 1=enabled
  2916. *
  2917. * 0001 0000
  2918. */
  2919. write_reg(info, CHA + CCR2, 0x10);
  2920. /* CCR3
  2921. *
  2922. * 07..01 Reserved, 0
  2923. * 00 PSD DPLL Phase Shift Disable
  2924. *
  2925. * 0000 0000
  2926. */
  2927. write_reg(info, CHA + CCR3, 0);
  2928. /* CCR4
  2929. *
  2930. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2931. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2932. * 05 TST1 Test Pin, 0=normal operation
  2933. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2934. * 03..00 Reserved, must be 0
  2935. *
  2936. * 0101 0000
  2937. */
  2938. write_reg(info, CHA + CCR4, 0x50);
  2939. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  2940. /* DAFO Data Format
  2941. *
  2942. * 07 Reserved, 0
  2943. * 06 XBRK transmit break, 0=normal operation
  2944. * 05 Stop bits (0=1, 1=2)
  2945. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  2946. * 02 PAREN Parity Enable
  2947. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  2948. *
  2949. */
  2950. val = 0x00;
  2951. if (info->params.data_bits != 8)
  2952. val |= BIT0; /* 7 bits */
  2953. if (info->params.stop_bits != 1)
  2954. val |= BIT5;
  2955. if (info->params.parity != ASYNC_PARITY_NONE)
  2956. {
  2957. val |= BIT2; /* Parity enable */
  2958. if (info->params.parity == ASYNC_PARITY_ODD)
  2959. val |= BIT3;
  2960. else
  2961. val |= BIT4;
  2962. }
  2963. write_reg(info, CHA + DAFO, val);
  2964. /* RFC Rx FIFO Control
  2965. *
  2966. * 07 Reserved, 0
  2967. * 06 DPS, 1=parity bit not stored in data byte
  2968. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  2969. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  2970. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  2971. * 01 Reserved, 0
  2972. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  2973. *
  2974. * 0101 1100
  2975. */
  2976. write_reg(info, CHA + RFC, 0x5c);
  2977. /* RLCR Receive length check register
  2978. *
  2979. * Max frame length = (RL + 1) * 32
  2980. */
  2981. write_reg(info, CHA + RLCR, 0);
  2982. /* XBCH Transmit Byte Count High
  2983. *
  2984. * 07 DMA mode, 0 = interrupt driven
  2985. * 06 NRM, 0=ABM (ignored)
  2986. * 05 CAS Carrier Auto Start
  2987. * 04 XC Transmit Continuously (ignored)
  2988. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2989. *
  2990. * 0000 0000
  2991. */
  2992. val = 0x00;
  2993. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2994. val |= BIT5;
  2995. write_reg(info, CHA + XBCH, val);
  2996. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2997. irq_enable(info, CHA, IRQ_CTS);
  2998. /* MODE:03 RAC Receiver Active, 1=active */
  2999. set_reg_bits(info, CHA + MODE, BIT3);
  3000. enable_auxclk(info);
  3001. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3002. irq_enable(info, CHB, IRQ_CTS);
  3003. /* PVR[3] 1=AUTO CTS active */
  3004. set_reg_bits(info, CHA + PVR, BIT3);
  3005. } else
  3006. clear_reg_bits(info, CHA + PVR, BIT3);
  3007. irq_enable(info, CHA,
  3008. IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
  3009. IRQ_ALLSENT + IRQ_TXFIFO);
  3010. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3011. wait_command_complete(info, CHA);
  3012. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3013. }
  3014. /* Set the HDLC idle mode for the transmitter.
  3015. */
  3016. static void tx_set_idle(MGSLPC_INFO *info)
  3017. {
  3018. /* Note: ESCC2 only supports flags and one idle modes */
  3019. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3020. set_reg_bits(info, CHA + CCR1, BIT3);
  3021. else
  3022. clear_reg_bits(info, CHA + CCR1, BIT3);
  3023. }
  3024. /* get state of the V24 status (input) signals.
  3025. */
  3026. static void get_signals(MGSLPC_INFO *info)
  3027. {
  3028. unsigned char status = 0;
  3029. /* preserve DTR and RTS */
  3030. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  3031. if (read_reg(info, CHB + VSTR) & BIT7)
  3032. info->serial_signals |= SerialSignal_DCD;
  3033. if (read_reg(info, CHB + STAR) & BIT1)
  3034. info->serial_signals |= SerialSignal_CTS;
  3035. status = read_reg(info, CHA + PVR);
  3036. if (!(status & PVR_RI))
  3037. info->serial_signals |= SerialSignal_RI;
  3038. if (!(status & PVR_DSR))
  3039. info->serial_signals |= SerialSignal_DSR;
  3040. }
  3041. /* Set the state of DTR and RTS based on contents of
  3042. * serial_signals member of device extension.
  3043. */
  3044. static void set_signals(MGSLPC_INFO *info)
  3045. {
  3046. unsigned char val;
  3047. val = read_reg(info, CHA + MODE);
  3048. if (info->params.mode == MGSL_MODE_ASYNC) {
  3049. if (info->serial_signals & SerialSignal_RTS)
  3050. val &= ~BIT6;
  3051. else
  3052. val |= BIT6;
  3053. } else {
  3054. if (info->serial_signals & SerialSignal_RTS)
  3055. val |= BIT2;
  3056. else
  3057. val &= ~BIT2;
  3058. }
  3059. write_reg(info, CHA + MODE, val);
  3060. if (info->serial_signals & SerialSignal_DTR)
  3061. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3062. else
  3063. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3064. }
  3065. static void rx_reset_buffers(MGSLPC_INFO *info)
  3066. {
  3067. RXBUF *buf;
  3068. int i;
  3069. info->rx_put = 0;
  3070. info->rx_get = 0;
  3071. info->rx_frame_count = 0;
  3072. for (i=0 ; i < info->rx_buf_count ; i++) {
  3073. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3074. buf->status = buf->count = 0;
  3075. }
  3076. }
  3077. /* Attempt to return a received HDLC frame
  3078. * Only frames received without errors are returned.
  3079. *
  3080. * Returns true if frame returned, otherwise false
  3081. */
  3082. static bool rx_get_frame(MGSLPC_INFO *info, struct tty_struct *tty)
  3083. {
  3084. unsigned short status;
  3085. RXBUF *buf;
  3086. unsigned int framesize = 0;
  3087. unsigned long flags;
  3088. bool return_frame = false;
  3089. if (info->rx_frame_count == 0)
  3090. return false;
  3091. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3092. status = buf->status;
  3093. /* 07 VFR 1=valid frame
  3094. * 06 RDO 1=data overrun
  3095. * 05 CRC 1=OK, 0=error
  3096. * 04 RAB 1=frame aborted
  3097. */
  3098. if ((status & 0xf0) != 0xA0) {
  3099. if (!(status & BIT7) || (status & BIT4))
  3100. info->icount.rxabort++;
  3101. else if (status & BIT6)
  3102. info->icount.rxover++;
  3103. else if (!(status & BIT5)) {
  3104. info->icount.rxcrc++;
  3105. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3106. return_frame = true;
  3107. }
  3108. framesize = 0;
  3109. #if SYNCLINK_GENERIC_HDLC
  3110. {
  3111. info->netdev->stats.rx_errors++;
  3112. info->netdev->stats.rx_frame_errors++;
  3113. }
  3114. #endif
  3115. } else
  3116. return_frame = true;
  3117. if (return_frame)
  3118. framesize = buf->count;
  3119. if (debug_level >= DEBUG_LEVEL_BH)
  3120. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3121. __FILE__,__LINE__,info->device_name,status,framesize);
  3122. if (debug_level >= DEBUG_LEVEL_DATA)
  3123. trace_block(info, buf->data, framesize, 0);
  3124. if (framesize) {
  3125. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3126. framesize+1 > info->max_frame_size) ||
  3127. framesize > info->max_frame_size)
  3128. info->icount.rxlong++;
  3129. else {
  3130. if (status & BIT5)
  3131. info->icount.rxok++;
  3132. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3133. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3134. ++framesize;
  3135. }
  3136. #if SYNCLINK_GENERIC_HDLC
  3137. if (info->netcount)
  3138. hdlcdev_rx(info, buf->data, framesize);
  3139. else
  3140. #endif
  3141. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3142. }
  3143. }
  3144. spin_lock_irqsave(&info->lock,flags);
  3145. buf->status = buf->count = 0;
  3146. info->rx_frame_count--;
  3147. info->rx_get++;
  3148. if (info->rx_get >= info->rx_buf_count)
  3149. info->rx_get = 0;
  3150. spin_unlock_irqrestore(&info->lock,flags);
  3151. return true;
  3152. }
  3153. static bool register_test(MGSLPC_INFO *info)
  3154. {
  3155. static unsigned char patterns[] =
  3156. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3157. static unsigned int count = ARRAY_SIZE(patterns);
  3158. unsigned int i;
  3159. bool rc = true;
  3160. unsigned long flags;
  3161. spin_lock_irqsave(&info->lock,flags);
  3162. reset_device(info);
  3163. for (i = 0; i < count; i++) {
  3164. write_reg(info, XAD1, patterns[i]);
  3165. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3166. if ((read_reg(info, XAD1) != patterns[i]) ||
  3167. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3168. rc = false;
  3169. break;
  3170. }
  3171. }
  3172. spin_unlock_irqrestore(&info->lock,flags);
  3173. return rc;
  3174. }
  3175. static bool irq_test(MGSLPC_INFO *info)
  3176. {
  3177. unsigned long end_time;
  3178. unsigned long flags;
  3179. spin_lock_irqsave(&info->lock,flags);
  3180. reset_device(info);
  3181. info->testing_irq = true;
  3182. hdlc_mode(info);
  3183. info->irq_occurred = false;
  3184. /* init hdlc mode */
  3185. irq_enable(info, CHA, IRQ_TIMER);
  3186. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3187. issue_command(info, CHA, CMD_START_TIMER);
  3188. spin_unlock_irqrestore(&info->lock,flags);
  3189. end_time=100;
  3190. while(end_time-- && !info->irq_occurred) {
  3191. msleep_interruptible(10);
  3192. }
  3193. info->testing_irq = false;
  3194. spin_lock_irqsave(&info->lock,flags);
  3195. reset_device(info);
  3196. spin_unlock_irqrestore(&info->lock,flags);
  3197. return info->irq_occurred;
  3198. }
  3199. static int adapter_test(MGSLPC_INFO *info)
  3200. {
  3201. if (!register_test(info)) {
  3202. info->init_error = DiagStatus_AddressFailure;
  3203. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  3204. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  3205. return -ENODEV;
  3206. }
  3207. if (!irq_test(info)) {
  3208. info->init_error = DiagStatus_IrqFailure;
  3209. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3210. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  3211. return -ENODEV;
  3212. }
  3213. if (debug_level >= DEBUG_LEVEL_INFO)
  3214. printk("%s(%d):device %s passed diagnostics\n",
  3215. __FILE__,__LINE__,info->device_name);
  3216. return 0;
  3217. }
  3218. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3219. {
  3220. int i;
  3221. int linecount;
  3222. if (xmit)
  3223. printk("%s tx data:\n",info->device_name);
  3224. else
  3225. printk("%s rx data:\n",info->device_name);
  3226. while(count) {
  3227. if (count > 16)
  3228. linecount = 16;
  3229. else
  3230. linecount = count;
  3231. for(i=0;i<linecount;i++)
  3232. printk("%02X ",(unsigned char)data[i]);
  3233. for(;i<17;i++)
  3234. printk(" ");
  3235. for(i=0;i<linecount;i++) {
  3236. if (data[i]>=040 && data[i]<=0176)
  3237. printk("%c",data[i]);
  3238. else
  3239. printk(".");
  3240. }
  3241. printk("\n");
  3242. data += linecount;
  3243. count -= linecount;
  3244. }
  3245. }
  3246. /* HDLC frame time out
  3247. * update stats and do tx completion processing
  3248. */
  3249. static void tx_timeout(unsigned long context)
  3250. {
  3251. MGSLPC_INFO *info = (MGSLPC_INFO*)context;
  3252. unsigned long flags;
  3253. if ( debug_level >= DEBUG_LEVEL_INFO )
  3254. printk( "%s(%d):tx_timeout(%s)\n",
  3255. __FILE__,__LINE__,info->device_name);
  3256. if(info->tx_active &&
  3257. info->params.mode == MGSL_MODE_HDLC) {
  3258. info->icount.txtimeout++;
  3259. }
  3260. spin_lock_irqsave(&info->lock,flags);
  3261. info->tx_active = false;
  3262. info->tx_count = info->tx_put = info->tx_get = 0;
  3263. spin_unlock_irqrestore(&info->lock,flags);
  3264. #if SYNCLINK_GENERIC_HDLC
  3265. if (info->netcount)
  3266. hdlcdev_tx_done(info);
  3267. else
  3268. #endif
  3269. {
  3270. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3271. bh_transmit(info, tty);
  3272. tty_kref_put(tty);
  3273. }
  3274. }
  3275. #if SYNCLINK_GENERIC_HDLC
  3276. /**
  3277. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3278. * set encoding and frame check sequence (FCS) options
  3279. *
  3280. * dev pointer to network device structure
  3281. * encoding serial encoding setting
  3282. * parity FCS setting
  3283. *
  3284. * returns 0 if success, otherwise error code
  3285. */
  3286. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3287. unsigned short parity)
  3288. {
  3289. MGSLPC_INFO *info = dev_to_port(dev);
  3290. struct tty_struct *tty;
  3291. unsigned char new_encoding;
  3292. unsigned short new_crctype;
  3293. /* return error if TTY interface open */
  3294. if (info->port.count)
  3295. return -EBUSY;
  3296. switch (encoding)
  3297. {
  3298. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3299. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3300. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3301. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3302. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3303. default: return -EINVAL;
  3304. }
  3305. switch (parity)
  3306. {
  3307. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3308. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3309. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3310. default: return -EINVAL;
  3311. }
  3312. info->params.encoding = new_encoding;
  3313. info->params.crc_type = new_crctype;
  3314. /* if network interface up, reprogram hardware */
  3315. if (info->netcount) {
  3316. tty = tty_port_tty_get(&info->port);
  3317. mgslpc_program_hw(info, tty);
  3318. tty_kref_put(tty);
  3319. }
  3320. return 0;
  3321. }
  3322. /**
  3323. * called by generic HDLC layer to send frame
  3324. *
  3325. * skb socket buffer containing HDLC frame
  3326. * dev pointer to network device structure
  3327. */
  3328. static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
  3329. struct net_device *dev)
  3330. {
  3331. MGSLPC_INFO *info = dev_to_port(dev);
  3332. unsigned long flags;
  3333. if (debug_level >= DEBUG_LEVEL_INFO)
  3334. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  3335. /* stop sending until this frame completes */
  3336. netif_stop_queue(dev);
  3337. /* copy data to device buffers */
  3338. skb_copy_from_linear_data(skb, info->tx_buf, skb->len);
  3339. info->tx_get = 0;
  3340. info->tx_put = info->tx_count = skb->len;
  3341. /* update network statistics */
  3342. dev->stats.tx_packets++;
  3343. dev->stats.tx_bytes += skb->len;
  3344. /* done with socket buffer, so free it */
  3345. dev_kfree_skb(skb);
  3346. /* save start time for transmit timeout detection */
  3347. dev->trans_start = jiffies;
  3348. /* start hardware transmitter if necessary */
  3349. spin_lock_irqsave(&info->lock,flags);
  3350. if (!info->tx_active) {
  3351. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3352. tx_start(info, tty);
  3353. tty_kref_put(tty);
  3354. }
  3355. spin_unlock_irqrestore(&info->lock,flags);
  3356. return NETDEV_TX_OK;
  3357. }
  3358. /**
  3359. * called by network layer when interface enabled
  3360. * claim resources and initialize hardware
  3361. *
  3362. * dev pointer to network device structure
  3363. *
  3364. * returns 0 if success, otherwise error code
  3365. */
  3366. static int hdlcdev_open(struct net_device *dev)
  3367. {
  3368. MGSLPC_INFO *info = dev_to_port(dev);
  3369. struct tty_struct *tty;
  3370. int rc;
  3371. unsigned long flags;
  3372. if (debug_level >= DEBUG_LEVEL_INFO)
  3373. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  3374. /* generic HDLC layer open processing */
  3375. if ((rc = hdlc_open(dev)))
  3376. return rc;
  3377. /* arbitrate between network and tty opens */
  3378. spin_lock_irqsave(&info->netlock, flags);
  3379. if (info->port.count != 0 || info->netcount != 0) {
  3380. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3381. spin_unlock_irqrestore(&info->netlock, flags);
  3382. return -EBUSY;
  3383. }
  3384. info->netcount=1;
  3385. spin_unlock_irqrestore(&info->netlock, flags);
  3386. tty = tty_port_tty_get(&info->port);
  3387. /* claim resources and init adapter */
  3388. if ((rc = startup(info, tty)) != 0) {
  3389. tty_kref_put(tty);
  3390. spin_lock_irqsave(&info->netlock, flags);
  3391. info->netcount=0;
  3392. spin_unlock_irqrestore(&info->netlock, flags);
  3393. return rc;
  3394. }
  3395. /* assert DTR and RTS, apply hardware settings */
  3396. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  3397. mgslpc_program_hw(info, tty);
  3398. tty_kref_put(tty);
  3399. /* enable network layer transmit */
  3400. dev->trans_start = jiffies;
  3401. netif_start_queue(dev);
  3402. /* inform generic HDLC layer of current DCD status */
  3403. spin_lock_irqsave(&info->lock, flags);
  3404. get_signals(info);
  3405. spin_unlock_irqrestore(&info->lock, flags);
  3406. if (info->serial_signals & SerialSignal_DCD)
  3407. netif_carrier_on(dev);
  3408. else
  3409. netif_carrier_off(dev);
  3410. return 0;
  3411. }
  3412. /**
  3413. * called by network layer when interface is disabled
  3414. * shutdown hardware and release resources
  3415. *
  3416. * dev pointer to network device structure
  3417. *
  3418. * returns 0 if success, otherwise error code
  3419. */
  3420. static int hdlcdev_close(struct net_device *dev)
  3421. {
  3422. MGSLPC_INFO *info = dev_to_port(dev);
  3423. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3424. unsigned long flags;
  3425. if (debug_level >= DEBUG_LEVEL_INFO)
  3426. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  3427. netif_stop_queue(dev);
  3428. /* shutdown adapter and release resources */
  3429. shutdown(info, tty);
  3430. tty_kref_put(tty);
  3431. hdlc_close(dev);
  3432. spin_lock_irqsave(&info->netlock, flags);
  3433. info->netcount=0;
  3434. spin_unlock_irqrestore(&info->netlock, flags);
  3435. return 0;
  3436. }
  3437. /**
  3438. * called by network layer to process IOCTL call to network device
  3439. *
  3440. * dev pointer to network device structure
  3441. * ifr pointer to network interface request structure
  3442. * cmd IOCTL command code
  3443. *
  3444. * returns 0 if success, otherwise error code
  3445. */
  3446. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3447. {
  3448. const size_t size = sizeof(sync_serial_settings);
  3449. sync_serial_settings new_line;
  3450. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3451. MGSLPC_INFO *info = dev_to_port(dev);
  3452. unsigned int flags;
  3453. if (debug_level >= DEBUG_LEVEL_INFO)
  3454. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  3455. /* return error if TTY interface open */
  3456. if (info->port.count)
  3457. return -EBUSY;
  3458. if (cmd != SIOCWANDEV)
  3459. return hdlc_ioctl(dev, ifr, cmd);
  3460. memset(&new_line, 0, size);
  3461. switch(ifr->ifr_settings.type) {
  3462. case IF_GET_IFACE: /* return current sync_serial_settings */
  3463. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3464. if (ifr->ifr_settings.size < size) {
  3465. ifr->ifr_settings.size = size; /* data size wanted */
  3466. return -ENOBUFS;
  3467. }
  3468. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3469. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3470. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3471. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3472. switch (flags){
  3473. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3474. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3475. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3476. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3477. default: new_line.clock_type = CLOCK_DEFAULT;
  3478. }
  3479. new_line.clock_rate = info->params.clock_speed;
  3480. new_line.loopback = info->params.loopback ? 1:0;
  3481. if (copy_to_user(line, &new_line, size))
  3482. return -EFAULT;
  3483. return 0;
  3484. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3485. if(!capable(CAP_NET_ADMIN))
  3486. return -EPERM;
  3487. if (copy_from_user(&new_line, line, size))
  3488. return -EFAULT;
  3489. switch (new_line.clock_type)
  3490. {
  3491. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3492. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3493. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3494. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3495. case CLOCK_DEFAULT: flags = info->params.flags &
  3496. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3497. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3498. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3499. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3500. default: return -EINVAL;
  3501. }
  3502. if (new_line.loopback != 0 && new_line.loopback != 1)
  3503. return -EINVAL;
  3504. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3505. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3506. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3507. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3508. info->params.flags |= flags;
  3509. info->params.loopback = new_line.loopback;
  3510. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3511. info->params.clock_speed = new_line.clock_rate;
  3512. else
  3513. info->params.clock_speed = 0;
  3514. /* if network interface up, reprogram hardware */
  3515. if (info->netcount) {
  3516. struct tty_struct *tty = tty_port_tty_get(&info->port);
  3517. mgslpc_program_hw(info, tty);
  3518. tty_kref_put(tty);
  3519. }
  3520. return 0;
  3521. default:
  3522. return hdlc_ioctl(dev, ifr, cmd);
  3523. }
  3524. }
  3525. /**
  3526. * called by network layer when transmit timeout is detected
  3527. *
  3528. * dev pointer to network device structure
  3529. */
  3530. static void hdlcdev_tx_timeout(struct net_device *dev)
  3531. {
  3532. MGSLPC_INFO *info = dev_to_port(dev);
  3533. unsigned long flags;
  3534. if (debug_level >= DEBUG_LEVEL_INFO)
  3535. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  3536. dev->stats.tx_errors++;
  3537. dev->stats.tx_aborted_errors++;
  3538. spin_lock_irqsave(&info->lock,flags);
  3539. tx_stop(info);
  3540. spin_unlock_irqrestore(&info->lock,flags);
  3541. netif_wake_queue(dev);
  3542. }
  3543. /**
  3544. * called by device driver when transmit completes
  3545. * reenable network layer transmit if stopped
  3546. *
  3547. * info pointer to device instance information
  3548. */
  3549. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3550. {
  3551. if (netif_queue_stopped(info->netdev))
  3552. netif_wake_queue(info->netdev);
  3553. }
  3554. /**
  3555. * called by device driver when frame received
  3556. * pass frame to network layer
  3557. *
  3558. * info pointer to device instance information
  3559. * buf pointer to buffer contianing frame data
  3560. * size count of data bytes in buf
  3561. */
  3562. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3563. {
  3564. struct sk_buff *skb = dev_alloc_skb(size);
  3565. struct net_device *dev = info->netdev;
  3566. if (debug_level >= DEBUG_LEVEL_INFO)
  3567. printk("hdlcdev_rx(%s)\n",dev->name);
  3568. if (skb == NULL) {
  3569. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3570. dev->stats.rx_dropped++;
  3571. return;
  3572. }
  3573. memcpy(skb_put(skb, size), buf, size);
  3574. skb->protocol = hdlc_type_trans(skb, dev);
  3575. dev->stats.rx_packets++;
  3576. dev->stats.rx_bytes += size;
  3577. netif_rx(skb);
  3578. }
  3579. static const struct net_device_ops hdlcdev_ops = {
  3580. .ndo_open = hdlcdev_open,
  3581. .ndo_stop = hdlcdev_close,
  3582. .ndo_change_mtu = hdlc_change_mtu,
  3583. .ndo_start_xmit = hdlc_start_xmit,
  3584. .ndo_do_ioctl = hdlcdev_ioctl,
  3585. .ndo_tx_timeout = hdlcdev_tx_timeout,
  3586. };
  3587. /**
  3588. * called by device driver when adding device instance
  3589. * do generic HDLC initialization
  3590. *
  3591. * info pointer to device instance information
  3592. *
  3593. * returns 0 if success, otherwise error code
  3594. */
  3595. static int hdlcdev_init(MGSLPC_INFO *info)
  3596. {
  3597. int rc;
  3598. struct net_device *dev;
  3599. hdlc_device *hdlc;
  3600. /* allocate and initialize network and HDLC layer objects */
  3601. if (!(dev = alloc_hdlcdev(info))) {
  3602. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  3603. return -ENOMEM;
  3604. }
  3605. /* for network layer reporting purposes only */
  3606. dev->base_addr = info->io_base;
  3607. dev->irq = info->irq_level;
  3608. /* network layer callbacks and settings */
  3609. dev->netdev_ops = &hdlcdev_ops;
  3610. dev->watchdog_timeo = 10 * HZ;
  3611. dev->tx_queue_len = 50;
  3612. /* generic HDLC layer callbacks and settings */
  3613. hdlc = dev_to_hdlc(dev);
  3614. hdlc->attach = hdlcdev_attach;
  3615. hdlc->xmit = hdlcdev_xmit;
  3616. /* register objects with HDLC layer */
  3617. if ((rc = register_hdlc_device(dev))) {
  3618. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  3619. free_netdev(dev);
  3620. return rc;
  3621. }
  3622. info->netdev = dev;
  3623. return 0;
  3624. }
  3625. /**
  3626. * called by device driver when removing device instance
  3627. * do generic HDLC cleanup
  3628. *
  3629. * info pointer to device instance information
  3630. */
  3631. static void hdlcdev_exit(MGSLPC_INFO *info)
  3632. {
  3633. unregister_hdlc_device(info->netdev);
  3634. free_netdev(info->netdev);
  3635. info->netdev = NULL;
  3636. }
  3637. #endif /* CONFIG_HDLC */