noon010pc30.c 21 KB

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  1. /*
  2. * Driver for SiliconFile NOON010PC30 CIF (1/11") Image Sensor with ISP
  3. *
  4. * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
  5. * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
  6. *
  7. * Initial register configuration based on a driver authored by
  8. * HeungJun Kim <riverful.kim@samsung.com>.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/gpio.h>
  17. #include <linux/i2c.h>
  18. #include <linux/slab.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <media/noon010pc30.h>
  21. #include <media/v4l2-chip-ident.h>
  22. #include <linux/videodev2.h>
  23. #include <linux/module.h>
  24. #include <media/v4l2-ctrls.h>
  25. #include <media/v4l2-device.h>
  26. #include <media/v4l2-mediabus.h>
  27. #include <media/v4l2-subdev.h>
  28. static int debug;
  29. module_param(debug, int, 0644);
  30. MODULE_PARM_DESC(debug, "Enable module debug trace. Set to 1 to enable.");
  31. #define MODULE_NAME "NOON010PC30"
  32. /*
  33. * Register offsets within a page
  34. * b15..b8 - page id, b7..b0 - register address
  35. */
  36. #define POWER_CTRL_REG 0x0001
  37. #define PAGEMODE_REG 0x03
  38. #define DEVICE_ID_REG 0x0004
  39. #define NOON010PC30_ID 0x86
  40. #define VDO_CTL_REG(n) (0x0010 + (n))
  41. #define SYNC_CTL_REG 0x0012
  42. /* Window size and position */
  43. #define WIN_ROWH_REG 0x0013
  44. #define WIN_ROWL_REG 0x0014
  45. #define WIN_COLH_REG 0x0015
  46. #define WIN_COLL_REG 0x0016
  47. #define WIN_HEIGHTH_REG 0x0017
  48. #define WIN_HEIGHTL_REG 0x0018
  49. #define WIN_WIDTHH_REG 0x0019
  50. #define WIN_WIDTHL_REG 0x001A
  51. #define HBLANKH_REG 0x001B
  52. #define HBLANKL_REG 0x001C
  53. #define VSYNCH_REG 0x001D
  54. #define VSYNCL_REG 0x001E
  55. /* VSYNC control */
  56. #define VS_CTL_REG(n) (0x00A1 + (n))
  57. /* page 1 */
  58. #define ISP_CTL_REG(n) (0x0110 + (n))
  59. #define YOFS_REG 0x0119
  60. #define DARK_YOFS_REG 0x011A
  61. #define SAT_CTL_REG 0x0120
  62. #define BSAT_REG 0x0121
  63. #define RSAT_REG 0x0122
  64. /* Color correction */
  65. #define CMC_CTL_REG 0x0130
  66. #define CMC_OFSGH_REG 0x0133
  67. #define CMC_OFSGL_REG 0x0135
  68. #define CMC_SIGN_REG 0x0136
  69. #define CMC_GOFS_REG 0x0137
  70. #define CMC_COEF_REG(n) (0x0138 + (n))
  71. #define CMC_OFS_REG(n) (0x0141 + (n))
  72. /* Gamma correction */
  73. #define GMA_CTL_REG 0x0160
  74. #define GMA_COEF_REG(n) (0x0161 + (n))
  75. /* Lens Shading */
  76. #define LENS_CTRL_REG 0x01D0
  77. #define LENS_XCEN_REG 0x01D1
  78. #define LENS_YCEN_REG 0x01D2
  79. #define LENS_RC_REG 0x01D3
  80. #define LENS_GC_REG 0x01D4
  81. #define LENS_BC_REG 0x01D5
  82. #define L_AGON_REG 0x01D6
  83. #define L_AGOFF_REG 0x01D7
  84. /* Page 3 - Auto Exposure */
  85. #define AE_CTL_REG(n) (0x0310 + (n))
  86. #define AE_CTL9_REG 0x032C
  87. #define AE_CTL10_REG 0x032D
  88. #define AE_YLVL_REG 0x031C
  89. #define AE_YTH_REG(n) (0x031D + (n))
  90. #define AE_WGT_REG 0x0326
  91. #define EXP_TIMEH_REG 0x0333
  92. #define EXP_TIMEM_REG 0x0334
  93. #define EXP_TIMEL_REG 0x0335
  94. #define EXP_MMINH_REG 0x0336
  95. #define EXP_MMINL_REG 0x0337
  96. #define EXP_MMAXH_REG 0x0338
  97. #define EXP_MMAXM_REG 0x0339
  98. #define EXP_MMAXL_REG 0x033A
  99. /* Page 4 - Auto White Balance */
  100. #define AWB_CTL_REG(n) (0x0410 + (n))
  101. #define AWB_ENABE 0x80
  102. #define AWB_WGHT_REG 0x0419
  103. #define BGAIN_PAR_REG(n) (0x044F + (n))
  104. /* Manual white balance, when AWB_CTL2[0]=1 */
  105. #define MWB_RGAIN_REG 0x0466
  106. #define MWB_BGAIN_REG 0x0467
  107. /* The token to mark an array end */
  108. #define REG_TERM 0xFFFF
  109. struct noon010_format {
  110. enum v4l2_mbus_pixelcode code;
  111. enum v4l2_colorspace colorspace;
  112. u16 ispctl1_reg;
  113. };
  114. struct noon010_frmsize {
  115. u16 width;
  116. u16 height;
  117. int vid_ctl1;
  118. };
  119. static const char * const noon010_supply_name[] = {
  120. "vdd_core", "vddio", "vdda"
  121. };
  122. #define NOON010_NUM_SUPPLIES ARRAY_SIZE(noon010_supply_name)
  123. struct noon010_info {
  124. struct v4l2_subdev sd;
  125. struct media_pad pad;
  126. struct v4l2_ctrl_handler hdl;
  127. struct regulator_bulk_data supply[NOON010_NUM_SUPPLIES];
  128. u32 gpio_nreset;
  129. u32 gpio_nstby;
  130. /* Protects the struct members below */
  131. struct mutex lock;
  132. const struct noon010_format *curr_fmt;
  133. const struct noon010_frmsize *curr_win;
  134. unsigned int apply_new_cfg:1;
  135. unsigned int streaming:1;
  136. unsigned int hflip:1;
  137. unsigned int vflip:1;
  138. unsigned int power:1;
  139. u8 i2c_reg_page;
  140. };
  141. struct i2c_regval {
  142. u16 addr;
  143. u16 val;
  144. };
  145. /* Supported resolutions. */
  146. static const struct noon010_frmsize noon010_sizes[] = {
  147. {
  148. .width = 352,
  149. .height = 288,
  150. .vid_ctl1 = 0,
  151. }, {
  152. .width = 176,
  153. .height = 144,
  154. .vid_ctl1 = 0x10,
  155. }, {
  156. .width = 88,
  157. .height = 72,
  158. .vid_ctl1 = 0x20,
  159. },
  160. };
  161. /* Supported pixel formats. */
  162. static const struct noon010_format noon010_formats[] = {
  163. {
  164. .code = V4L2_MBUS_FMT_YUYV8_2X8,
  165. .colorspace = V4L2_COLORSPACE_JPEG,
  166. .ispctl1_reg = 0x03,
  167. }, {
  168. .code = V4L2_MBUS_FMT_YVYU8_2X8,
  169. .colorspace = V4L2_COLORSPACE_JPEG,
  170. .ispctl1_reg = 0x02,
  171. }, {
  172. .code = V4L2_MBUS_FMT_VYUY8_2X8,
  173. .colorspace = V4L2_COLORSPACE_JPEG,
  174. .ispctl1_reg = 0,
  175. }, {
  176. .code = V4L2_MBUS_FMT_UYVY8_2X8,
  177. .colorspace = V4L2_COLORSPACE_JPEG,
  178. .ispctl1_reg = 0x01,
  179. }, {
  180. .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
  181. .colorspace = V4L2_COLORSPACE_JPEG,
  182. .ispctl1_reg = 0x40,
  183. },
  184. };
  185. static const struct i2c_regval noon010_base_regs[] = {
  186. { WIN_COLL_REG, 0x06 }, { HBLANKL_REG, 0x7C },
  187. /* Color corection and saturation */
  188. { ISP_CTL_REG(0), 0x30 }, { ISP_CTL_REG(2), 0x30 },
  189. { YOFS_REG, 0x80 }, { DARK_YOFS_REG, 0x04 },
  190. { SAT_CTL_REG, 0x1F }, { BSAT_REG, 0x90 },
  191. { CMC_CTL_REG, 0x0F }, { CMC_OFSGH_REG, 0x3C },
  192. { CMC_OFSGL_REG, 0x2C }, { CMC_SIGN_REG, 0x3F },
  193. { CMC_COEF_REG(0), 0x79 }, { CMC_OFS_REG(0), 0x00 },
  194. { CMC_COEF_REG(1), 0x39 }, { CMC_OFS_REG(1), 0x00 },
  195. { CMC_COEF_REG(2), 0x00 }, { CMC_OFS_REG(2), 0x00 },
  196. { CMC_COEF_REG(3), 0x11 }, { CMC_OFS_REG(3), 0x8B },
  197. { CMC_COEF_REG(4), 0x65 }, { CMC_OFS_REG(4), 0x07 },
  198. { CMC_COEF_REG(5), 0x14 }, { CMC_OFS_REG(5), 0x04 },
  199. { CMC_COEF_REG(6), 0x01 }, { CMC_OFS_REG(6), 0x9C },
  200. { CMC_COEF_REG(7), 0x33 }, { CMC_OFS_REG(7), 0x89 },
  201. { CMC_COEF_REG(8), 0x74 }, { CMC_OFS_REG(8), 0x25 },
  202. /* Automatic white balance */
  203. { AWB_CTL_REG(0), 0x78 }, { AWB_CTL_REG(1), 0x2E },
  204. { AWB_CTL_REG(2), 0x20 }, { AWB_CTL_REG(3), 0x85 },
  205. /* Auto exposure */
  206. { AE_CTL_REG(0), 0xDC }, { AE_CTL_REG(1), 0x81 },
  207. { AE_CTL_REG(2), 0x30 }, { AE_CTL_REG(3), 0xA5 },
  208. { AE_CTL_REG(4), 0x40 }, { AE_CTL_REG(5), 0x51 },
  209. { AE_CTL_REG(6), 0x33 }, { AE_CTL_REG(7), 0x7E },
  210. { AE_CTL9_REG, 0x00 }, { AE_CTL10_REG, 0x02 },
  211. { AE_YLVL_REG, 0x44 }, { AE_YTH_REG(0), 0x34 },
  212. { AE_YTH_REG(1), 0x30 }, { AE_WGT_REG, 0xD5 },
  213. /* Lens shading compensation */
  214. { LENS_CTRL_REG, 0x01 }, { LENS_XCEN_REG, 0x80 },
  215. { LENS_YCEN_REG, 0x70 }, { LENS_RC_REG, 0x53 },
  216. { LENS_GC_REG, 0x40 }, { LENS_BC_REG, 0x3E },
  217. { REG_TERM, 0 },
  218. };
  219. static inline struct noon010_info *to_noon010(struct v4l2_subdev *sd)
  220. {
  221. return container_of(sd, struct noon010_info, sd);
  222. }
  223. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  224. {
  225. return &container_of(ctrl->handler, struct noon010_info, hdl)->sd;
  226. }
  227. static inline int set_i2c_page(struct noon010_info *info,
  228. struct i2c_client *client, unsigned int reg)
  229. {
  230. u32 page = reg >> 8 & 0xFF;
  231. int ret = 0;
  232. if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
  233. ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
  234. if (!ret)
  235. info->i2c_reg_page = page;
  236. }
  237. return ret;
  238. }
  239. static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
  240. {
  241. struct i2c_client *client = v4l2_get_subdevdata(sd);
  242. struct noon010_info *info = to_noon010(sd);
  243. int ret = set_i2c_page(info, client, reg_addr);
  244. if (ret)
  245. return ret;
  246. return i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
  247. }
  248. static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
  249. {
  250. struct i2c_client *client = v4l2_get_subdevdata(sd);
  251. struct noon010_info *info = to_noon010(sd);
  252. int ret = set_i2c_page(info, client, reg_addr);
  253. if (ret)
  254. return ret;
  255. return i2c_smbus_write_byte_data(client, reg_addr & 0xFF, val);
  256. }
  257. static inline int noon010_bulk_write_reg(struct v4l2_subdev *sd,
  258. const struct i2c_regval *msg)
  259. {
  260. while (msg->addr != REG_TERM) {
  261. int ret = cam_i2c_write(sd, msg->addr, msg->val);
  262. if (ret)
  263. return ret;
  264. msg++;
  265. }
  266. return 0;
  267. }
  268. /* Device reset and sleep mode control */
  269. static int noon010_power_ctrl(struct v4l2_subdev *sd, bool reset, bool sleep)
  270. {
  271. struct noon010_info *info = to_noon010(sd);
  272. u8 reg = sleep ? 0xF1 : 0xF0;
  273. int ret = 0;
  274. if (reset) {
  275. ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
  276. udelay(20);
  277. }
  278. if (!ret) {
  279. ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
  280. if (reset && !ret)
  281. info->i2c_reg_page = -1;
  282. }
  283. return ret;
  284. }
  285. /* Automatic white balance control */
  286. static int noon010_enable_autowhitebalance(struct v4l2_subdev *sd, int on)
  287. {
  288. int ret;
  289. ret = cam_i2c_write(sd, AWB_CTL_REG(1), on ? 0x2E : 0x2F);
  290. if (!ret)
  291. ret = cam_i2c_write(sd, AWB_CTL_REG(0), on ? 0xFB : 0x7B);
  292. return ret;
  293. }
  294. /* Called with struct noon010_info.lock mutex held */
  295. static int noon010_set_flip(struct v4l2_subdev *sd, int hflip, int vflip)
  296. {
  297. struct noon010_info *info = to_noon010(sd);
  298. int reg, ret;
  299. reg = cam_i2c_read(sd, VDO_CTL_REG(1));
  300. if (reg < 0)
  301. return reg;
  302. reg &= 0x7C;
  303. if (hflip)
  304. reg |= 0x01;
  305. if (vflip)
  306. reg |= 0x02;
  307. ret = cam_i2c_write(sd, VDO_CTL_REG(1), reg | 0x80);
  308. if (!ret) {
  309. info->hflip = hflip;
  310. info->vflip = vflip;
  311. }
  312. return ret;
  313. }
  314. /* Configure resolution and color format */
  315. static int noon010_set_params(struct v4l2_subdev *sd)
  316. {
  317. struct noon010_info *info = to_noon010(sd);
  318. int ret = cam_i2c_write(sd, VDO_CTL_REG(0),
  319. info->curr_win->vid_ctl1);
  320. if (ret)
  321. return ret;
  322. return cam_i2c_write(sd, ISP_CTL_REG(0),
  323. info->curr_fmt->ispctl1_reg);
  324. }
  325. /* Find nearest matching image pixel size. */
  326. static int noon010_try_frame_size(struct v4l2_mbus_framefmt *mf,
  327. const struct noon010_frmsize **size)
  328. {
  329. unsigned int min_err = ~0;
  330. int i = ARRAY_SIZE(noon010_sizes);
  331. const struct noon010_frmsize *fsize = &noon010_sizes[0],
  332. *match = NULL;
  333. while (i--) {
  334. int err = abs(fsize->width - mf->width)
  335. + abs(fsize->height - mf->height);
  336. if (err < min_err) {
  337. min_err = err;
  338. match = fsize;
  339. }
  340. fsize++;
  341. }
  342. if (match) {
  343. mf->width = match->width;
  344. mf->height = match->height;
  345. if (size)
  346. *size = match;
  347. return 0;
  348. }
  349. return -EINVAL;
  350. }
  351. /* Called with info.lock mutex held */
  352. static int power_enable(struct noon010_info *info)
  353. {
  354. int ret;
  355. if (info->power) {
  356. v4l2_info(&info->sd, "%s: sensor is already on\n", __func__);
  357. return 0;
  358. }
  359. if (gpio_is_valid(info->gpio_nstby))
  360. gpio_set_value(info->gpio_nstby, 0);
  361. if (gpio_is_valid(info->gpio_nreset))
  362. gpio_set_value(info->gpio_nreset, 0);
  363. ret = regulator_bulk_enable(NOON010_NUM_SUPPLIES, info->supply);
  364. if (ret)
  365. return ret;
  366. if (gpio_is_valid(info->gpio_nreset)) {
  367. msleep(50);
  368. gpio_set_value(info->gpio_nreset, 1);
  369. }
  370. if (gpio_is_valid(info->gpio_nstby)) {
  371. udelay(1000);
  372. gpio_set_value(info->gpio_nstby, 1);
  373. }
  374. if (gpio_is_valid(info->gpio_nreset)) {
  375. udelay(1000);
  376. gpio_set_value(info->gpio_nreset, 0);
  377. msleep(100);
  378. gpio_set_value(info->gpio_nreset, 1);
  379. msleep(20);
  380. }
  381. info->power = 1;
  382. v4l2_dbg(1, debug, &info->sd, "%s: sensor is on\n", __func__);
  383. return 0;
  384. }
  385. /* Called with info.lock mutex held */
  386. static int power_disable(struct noon010_info *info)
  387. {
  388. int ret;
  389. if (!info->power) {
  390. v4l2_info(&info->sd, "%s: sensor is already off\n", __func__);
  391. return 0;
  392. }
  393. ret = regulator_bulk_disable(NOON010_NUM_SUPPLIES, info->supply);
  394. if (ret)
  395. return ret;
  396. if (gpio_is_valid(info->gpio_nstby))
  397. gpio_set_value(info->gpio_nstby, 0);
  398. if (gpio_is_valid(info->gpio_nreset))
  399. gpio_set_value(info->gpio_nreset, 0);
  400. info->power = 0;
  401. v4l2_dbg(1, debug, &info->sd, "%s: sensor is off\n", __func__);
  402. return 0;
  403. }
  404. static int noon010_s_ctrl(struct v4l2_ctrl *ctrl)
  405. {
  406. struct v4l2_subdev *sd = to_sd(ctrl);
  407. struct noon010_info *info = to_noon010(sd);
  408. int ret = 0;
  409. v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
  410. __func__, ctrl->id, ctrl->val);
  411. mutex_lock(&info->lock);
  412. /*
  413. * If the device is not powered up by the host driver do
  414. * not apply any controls to H/W at this time. Instead
  415. * the controls will be restored right after power-up.
  416. */
  417. if (!info->power)
  418. goto unlock;
  419. switch (ctrl->id) {
  420. case V4L2_CID_AUTO_WHITE_BALANCE:
  421. ret = noon010_enable_autowhitebalance(sd, ctrl->val);
  422. break;
  423. case V4L2_CID_BLUE_BALANCE:
  424. ret = cam_i2c_write(sd, MWB_BGAIN_REG, ctrl->val);
  425. break;
  426. case V4L2_CID_RED_BALANCE:
  427. ret = cam_i2c_write(sd, MWB_RGAIN_REG, ctrl->val);
  428. break;
  429. default:
  430. ret = -EINVAL;
  431. }
  432. unlock:
  433. mutex_unlock(&info->lock);
  434. return ret;
  435. }
  436. static int noon010_enum_mbus_code(struct v4l2_subdev *sd,
  437. struct v4l2_subdev_fh *fh,
  438. struct v4l2_subdev_mbus_code_enum *code)
  439. {
  440. if (code->index >= ARRAY_SIZE(noon010_formats))
  441. return -EINVAL;
  442. code->code = noon010_formats[code->index].code;
  443. return 0;
  444. }
  445. static int noon010_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
  446. struct v4l2_subdev_format *fmt)
  447. {
  448. struct noon010_info *info = to_noon010(sd);
  449. struct v4l2_mbus_framefmt *mf;
  450. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  451. if (fh) {
  452. mf = v4l2_subdev_get_try_format(fh, 0);
  453. fmt->format = *mf;
  454. }
  455. return 0;
  456. }
  457. mf = &fmt->format;
  458. mutex_lock(&info->lock);
  459. mf->width = info->curr_win->width;
  460. mf->height = info->curr_win->height;
  461. mf->code = info->curr_fmt->code;
  462. mf->colorspace = info->curr_fmt->colorspace;
  463. mf->field = V4L2_FIELD_NONE;
  464. mutex_unlock(&info->lock);
  465. return 0;
  466. }
  467. /* Return nearest media bus frame format. */
  468. static const struct noon010_format *noon010_try_fmt(struct v4l2_subdev *sd,
  469. struct v4l2_mbus_framefmt *mf)
  470. {
  471. int i = ARRAY_SIZE(noon010_formats);
  472. while (--i)
  473. if (mf->code == noon010_formats[i].code)
  474. break;
  475. mf->code = noon010_formats[i].code;
  476. return &noon010_formats[i];
  477. }
  478. static int noon010_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
  479. struct v4l2_subdev_format *fmt)
  480. {
  481. struct noon010_info *info = to_noon010(sd);
  482. const struct noon010_frmsize *size = NULL;
  483. const struct noon010_format *nf;
  484. struct v4l2_mbus_framefmt *mf;
  485. int ret = 0;
  486. nf = noon010_try_fmt(sd, &fmt->format);
  487. noon010_try_frame_size(&fmt->format, &size);
  488. fmt->format.colorspace = V4L2_COLORSPACE_JPEG;
  489. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  490. if (fh) {
  491. mf = v4l2_subdev_get_try_format(fh, 0);
  492. *mf = fmt->format;
  493. }
  494. return 0;
  495. }
  496. mutex_lock(&info->lock);
  497. if (!info->streaming) {
  498. info->apply_new_cfg = 1;
  499. info->curr_fmt = nf;
  500. info->curr_win = size;
  501. } else {
  502. ret = -EBUSY;
  503. }
  504. mutex_unlock(&info->lock);
  505. return ret;
  506. }
  507. /* Called with struct noon010_info.lock mutex held */
  508. static int noon010_base_config(struct v4l2_subdev *sd)
  509. {
  510. int ret = noon010_bulk_write_reg(sd, noon010_base_regs);
  511. if (!ret)
  512. ret = noon010_set_params(sd);
  513. if (!ret)
  514. ret = noon010_set_flip(sd, 1, 0);
  515. return ret;
  516. }
  517. static int noon010_s_power(struct v4l2_subdev *sd, int on)
  518. {
  519. struct noon010_info *info = to_noon010(sd);
  520. int ret;
  521. mutex_lock(&info->lock);
  522. if (on) {
  523. ret = power_enable(info);
  524. if (!ret)
  525. ret = noon010_base_config(sd);
  526. } else {
  527. noon010_power_ctrl(sd, false, true);
  528. ret = power_disable(info);
  529. }
  530. mutex_unlock(&info->lock);
  531. /* Restore the controls state */
  532. if (!ret && on)
  533. ret = v4l2_ctrl_handler_setup(&info->hdl);
  534. return ret;
  535. }
  536. static int noon010_s_stream(struct v4l2_subdev *sd, int on)
  537. {
  538. struct noon010_info *info = to_noon010(sd);
  539. int ret = 0;
  540. mutex_lock(&info->lock);
  541. if (!info->streaming != !on) {
  542. ret = noon010_power_ctrl(sd, false, !on);
  543. if (!ret)
  544. info->streaming = on;
  545. }
  546. if (!ret && on && info->apply_new_cfg) {
  547. ret = noon010_set_params(sd);
  548. if (!ret)
  549. info->apply_new_cfg = 0;
  550. }
  551. mutex_unlock(&info->lock);
  552. return ret;
  553. }
  554. static int noon010_log_status(struct v4l2_subdev *sd)
  555. {
  556. struct noon010_info *info = to_noon010(sd);
  557. v4l2_ctrl_handler_log_status(&info->hdl, sd->name);
  558. return 0;
  559. }
  560. static int noon010_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  561. {
  562. struct v4l2_mbus_framefmt *mf = v4l2_subdev_get_try_format(fh, 0);
  563. mf->width = noon010_sizes[0].width;
  564. mf->height = noon010_sizes[0].height;
  565. mf->code = noon010_formats[0].code;
  566. mf->colorspace = V4L2_COLORSPACE_JPEG;
  567. mf->field = V4L2_FIELD_NONE;
  568. return 0;
  569. }
  570. static const struct v4l2_subdev_internal_ops noon010_subdev_internal_ops = {
  571. .open = noon010_open,
  572. };
  573. static const struct v4l2_ctrl_ops noon010_ctrl_ops = {
  574. .s_ctrl = noon010_s_ctrl,
  575. };
  576. static const struct v4l2_subdev_core_ops noon010_core_ops = {
  577. .s_power = noon010_s_power,
  578. .g_ctrl = v4l2_subdev_g_ctrl,
  579. .s_ctrl = v4l2_subdev_s_ctrl,
  580. .queryctrl = v4l2_subdev_queryctrl,
  581. .querymenu = v4l2_subdev_querymenu,
  582. .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
  583. .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
  584. .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
  585. .log_status = noon010_log_status,
  586. };
  587. static struct v4l2_subdev_pad_ops noon010_pad_ops = {
  588. .enum_mbus_code = noon010_enum_mbus_code,
  589. .get_fmt = noon010_get_fmt,
  590. .set_fmt = noon010_set_fmt,
  591. };
  592. static struct v4l2_subdev_video_ops noon010_video_ops = {
  593. .s_stream = noon010_s_stream,
  594. };
  595. static const struct v4l2_subdev_ops noon010_ops = {
  596. .core = &noon010_core_ops,
  597. .pad = &noon010_pad_ops,
  598. .video = &noon010_video_ops,
  599. };
  600. /* Return 0 if NOON010PC30L sensor type was detected or -ENODEV otherwise. */
  601. static int noon010_detect(struct i2c_client *client, struct noon010_info *info)
  602. {
  603. int ret;
  604. ret = power_enable(info);
  605. if (ret)
  606. return ret;
  607. ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
  608. if (ret < 0)
  609. dev_err(&client->dev, "I2C read failed: 0x%X\n", ret);
  610. power_disable(info);
  611. return ret == NOON010PC30_ID ? 0 : -ENODEV;
  612. }
  613. static int noon010_probe(struct i2c_client *client,
  614. const struct i2c_device_id *id)
  615. {
  616. struct noon010_info *info;
  617. struct v4l2_subdev *sd;
  618. const struct noon010pc30_platform_data *pdata
  619. = client->dev.platform_data;
  620. int ret;
  621. int i;
  622. if (!pdata) {
  623. dev_err(&client->dev, "No platform data!\n");
  624. return -EIO;
  625. }
  626. info = kzalloc(sizeof(*info), GFP_KERNEL);
  627. if (!info)
  628. return -ENOMEM;
  629. mutex_init(&info->lock);
  630. sd = &info->sd;
  631. v4l2_i2c_subdev_init(sd, client, &noon010_ops);
  632. strlcpy(sd->name, MODULE_NAME, sizeof(sd->name));
  633. sd->internal_ops = &noon010_subdev_internal_ops;
  634. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  635. v4l2_ctrl_handler_init(&info->hdl, 3);
  636. v4l2_ctrl_new_std(&info->hdl, &noon010_ctrl_ops,
  637. V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
  638. v4l2_ctrl_new_std(&info->hdl, &noon010_ctrl_ops,
  639. V4L2_CID_RED_BALANCE, 0, 127, 1, 64);
  640. v4l2_ctrl_new_std(&info->hdl, &noon010_ctrl_ops,
  641. V4L2_CID_BLUE_BALANCE, 0, 127, 1, 64);
  642. sd->ctrl_handler = &info->hdl;
  643. ret = info->hdl.error;
  644. if (ret)
  645. goto np_err;
  646. info->i2c_reg_page = -1;
  647. info->gpio_nreset = -EINVAL;
  648. info->gpio_nstby = -EINVAL;
  649. info->curr_fmt = &noon010_formats[0];
  650. info->curr_win = &noon010_sizes[0];
  651. if (gpio_is_valid(pdata->gpio_nreset)) {
  652. ret = gpio_request(pdata->gpio_nreset, "NOON010PC30 NRST");
  653. if (ret) {
  654. dev_err(&client->dev, "GPIO request error: %d\n", ret);
  655. goto np_err;
  656. }
  657. info->gpio_nreset = pdata->gpio_nreset;
  658. gpio_direction_output(info->gpio_nreset, 0);
  659. gpio_export(info->gpio_nreset, 0);
  660. }
  661. if (gpio_is_valid(pdata->gpio_nstby)) {
  662. ret = gpio_request(pdata->gpio_nstby, "NOON010PC30 NSTBY");
  663. if (ret) {
  664. dev_err(&client->dev, "GPIO request error: %d\n", ret);
  665. goto np_gpio_err;
  666. }
  667. info->gpio_nstby = pdata->gpio_nstby;
  668. gpio_direction_output(info->gpio_nstby, 0);
  669. gpio_export(info->gpio_nstby, 0);
  670. }
  671. for (i = 0; i < NOON010_NUM_SUPPLIES; i++)
  672. info->supply[i].supply = noon010_supply_name[i];
  673. ret = regulator_bulk_get(&client->dev, NOON010_NUM_SUPPLIES,
  674. info->supply);
  675. if (ret)
  676. goto np_reg_err;
  677. info->pad.flags = MEDIA_PAD_FL_SOURCE;
  678. sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
  679. ret = media_entity_init(&sd->entity, 1, &info->pad, 0);
  680. if (ret < 0)
  681. goto np_me_err;
  682. ret = noon010_detect(client, info);
  683. if (!ret)
  684. return 0;
  685. np_me_err:
  686. regulator_bulk_free(NOON010_NUM_SUPPLIES, info->supply);
  687. np_reg_err:
  688. if (gpio_is_valid(info->gpio_nstby))
  689. gpio_free(info->gpio_nstby);
  690. np_gpio_err:
  691. if (gpio_is_valid(info->gpio_nreset))
  692. gpio_free(info->gpio_nreset);
  693. np_err:
  694. v4l2_ctrl_handler_free(&info->hdl);
  695. v4l2_device_unregister_subdev(sd);
  696. kfree(info);
  697. return ret;
  698. }
  699. static int noon010_remove(struct i2c_client *client)
  700. {
  701. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  702. struct noon010_info *info = to_noon010(sd);
  703. v4l2_device_unregister_subdev(sd);
  704. v4l2_ctrl_handler_free(&info->hdl);
  705. regulator_bulk_free(NOON010_NUM_SUPPLIES, info->supply);
  706. if (gpio_is_valid(info->gpio_nreset))
  707. gpio_free(info->gpio_nreset);
  708. if (gpio_is_valid(info->gpio_nstby))
  709. gpio_free(info->gpio_nstby);
  710. media_entity_cleanup(&sd->entity);
  711. kfree(info);
  712. return 0;
  713. }
  714. static const struct i2c_device_id noon010_id[] = {
  715. { MODULE_NAME, 0 },
  716. { },
  717. };
  718. MODULE_DEVICE_TABLE(i2c, noon010_id);
  719. static struct i2c_driver noon010_i2c_driver = {
  720. .driver = {
  721. .name = MODULE_NAME
  722. },
  723. .probe = noon010_probe,
  724. .remove = noon010_remove,
  725. .id_table = noon010_id,
  726. };
  727. module_i2c_driver(noon010_i2c_driver);
  728. MODULE_DESCRIPTION("Siliconfile NOON010PC30 camera driver");
  729. MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
  730. MODULE_LICENSE("GPL");