m5mols_controls.c 8.8 KB

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  1. /*
  2. * Controls for M-5MOLS 8M Pixel camera sensor with ISP
  3. *
  4. * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  5. * Author: HeungJun Kim <riverful.kim@samsung.com>
  6. *
  7. * Copyright (C) 2009 Samsung Electronics Co., Ltd.
  8. * Author: Dongsoo Nathaniel Kim <dongsoo45.kim@samsung.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. */
  15. #include <linux/i2c.h>
  16. #include <linux/delay.h>
  17. #include <linux/videodev2.h>
  18. #include <media/v4l2-ctrls.h>
  19. #include "m5mols.h"
  20. #include "m5mols_reg.h"
  21. static struct m5mols_scenemode m5mols_default_scenemode[] = {
  22. [REG_SCENE_NORMAL] = {
  23. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  24. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  25. REG_AF_NORMAL, REG_FD_OFF,
  26. REG_MCC_NORMAL, REG_LIGHT_OFF, REG_FLASH_OFF,
  27. 5, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  28. },
  29. [REG_SCENE_PORTRAIT] = {
  30. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  31. REG_CHROMA_ON, 3, REG_EDGE_ON, 4,
  32. REG_AF_NORMAL, BIT_FD_EN | BIT_FD_DRAW_FACE_FRAME,
  33. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  34. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  35. },
  36. [REG_SCENE_LANDSCAPE] = {
  37. REG_AE_ALL, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  38. REG_CHROMA_ON, 4, REG_EDGE_ON, 6,
  39. REG_AF_NORMAL, REG_FD_OFF,
  40. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  41. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  42. },
  43. [REG_SCENE_SPORTS] = {
  44. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  45. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  46. REG_AF_NORMAL, REG_FD_OFF,
  47. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  48. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  49. },
  50. [REG_SCENE_PARTY_INDOOR] = {
  51. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  52. REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
  53. REG_AF_NORMAL, REG_FD_OFF,
  54. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  55. 6, REG_ISO_200, REG_CAP_NONE, REG_WDR_OFF,
  56. },
  57. [REG_SCENE_BEACH_SNOW] = {
  58. REG_AE_CENTER, REG_AE_INDEX_10_POS, REG_AWB_AUTO, 0,
  59. REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
  60. REG_AF_NORMAL, REG_FD_OFF,
  61. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  62. 6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
  63. },
  64. [REG_SCENE_SUNSET] = {
  65. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
  66. REG_AWB_DAYLIGHT,
  67. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  68. REG_AF_NORMAL, REG_FD_OFF,
  69. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  70. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  71. },
  72. [REG_SCENE_DAWN_DUSK] = {
  73. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
  74. REG_AWB_FLUORESCENT_1,
  75. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  76. REG_AF_NORMAL, REG_FD_OFF,
  77. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  78. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  79. },
  80. [REG_SCENE_FALL] = {
  81. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  82. REG_CHROMA_ON, 5, REG_EDGE_ON, 5,
  83. REG_AF_NORMAL, REG_FD_OFF,
  84. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  85. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  86. },
  87. [REG_SCENE_NIGHT] = {
  88. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  89. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  90. REG_AF_NORMAL, REG_FD_OFF,
  91. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  92. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  93. },
  94. [REG_SCENE_AGAINST_LIGHT] = {
  95. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  96. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  97. REG_AF_NORMAL, REG_FD_OFF,
  98. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  99. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  100. },
  101. [REG_SCENE_FIRE] = {
  102. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  103. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  104. REG_AF_NORMAL, REG_FD_OFF,
  105. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  106. 6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
  107. },
  108. [REG_SCENE_TEXT] = {
  109. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  110. REG_CHROMA_ON, 3, REG_EDGE_ON, 7,
  111. REG_AF_MACRO, REG_FD_OFF,
  112. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  113. 6, REG_ISO_AUTO, REG_CAP_ANTI_SHAKE, REG_WDR_ON,
  114. },
  115. [REG_SCENE_CANDLE] = {
  116. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  117. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  118. REG_AF_NORMAL, REG_FD_OFF,
  119. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  120. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  121. },
  122. };
  123. /**
  124. * m5mols_do_scenemode() - Change current scenemode
  125. * @mode: Desired mode of the scenemode
  126. *
  127. * WARNING: The execution order is important. Do not change the order.
  128. */
  129. int m5mols_do_scenemode(struct m5mols_info *info, u8 mode)
  130. {
  131. struct v4l2_subdev *sd = &info->sd;
  132. struct m5mols_scenemode scenemode = m5mols_default_scenemode[mode];
  133. int ret;
  134. if (mode > REG_SCENE_CANDLE)
  135. return -EINVAL;
  136. ret = m5mols_lock_3a(info, false);
  137. if (!ret)
  138. ret = m5mols_write(sd, AE_EV_PRESET_MONITOR, mode);
  139. if (!ret)
  140. ret = m5mols_write(sd, AE_EV_PRESET_CAPTURE, mode);
  141. if (!ret)
  142. ret = m5mols_write(sd, AE_MODE, scenemode.metering);
  143. if (!ret)
  144. ret = m5mols_write(sd, AE_INDEX, scenemode.ev_bias);
  145. if (!ret)
  146. ret = m5mols_write(sd, AWB_MODE, scenemode.wb_mode);
  147. if (!ret)
  148. ret = m5mols_write(sd, AWB_MANUAL, scenemode.wb_preset);
  149. if (!ret)
  150. ret = m5mols_write(sd, MON_CHROMA_EN, scenemode.chroma_en);
  151. if (!ret)
  152. ret = m5mols_write(sd, MON_CHROMA_LVL, scenemode.chroma_lvl);
  153. if (!ret)
  154. ret = m5mols_write(sd, MON_EDGE_EN, scenemode.edge_en);
  155. if (!ret)
  156. ret = m5mols_write(sd, MON_EDGE_LVL, scenemode.edge_lvl);
  157. if (!ret && is_available_af(info))
  158. ret = m5mols_write(sd, AF_MODE, scenemode.af_range);
  159. if (!ret && is_available_af(info))
  160. ret = m5mols_write(sd, FD_CTL, scenemode.fd_mode);
  161. if (!ret)
  162. ret = m5mols_write(sd, MON_TONE_CTL, scenemode.tone);
  163. if (!ret)
  164. ret = m5mols_write(sd, AE_ISO, scenemode.iso);
  165. if (!ret)
  166. ret = m5mols_mode(info, REG_CAPTURE);
  167. if (!ret)
  168. ret = m5mols_write(sd, CAPP_WDR_EN, scenemode.wdr);
  169. if (!ret)
  170. ret = m5mols_write(sd, CAPP_MCC_MODE, scenemode.mcc);
  171. if (!ret)
  172. ret = m5mols_write(sd, CAPP_LIGHT_CTRL, scenemode.light);
  173. if (!ret)
  174. ret = m5mols_write(sd, CAPP_FLASH_CTRL, scenemode.flash);
  175. if (!ret)
  176. ret = m5mols_write(sd, CAPC_MODE, scenemode.capt_mode);
  177. if (!ret)
  178. ret = m5mols_mode(info, REG_MONITOR);
  179. return ret;
  180. }
  181. static int m5mols_lock_ae(struct m5mols_info *info, bool lock)
  182. {
  183. int ret = 0;
  184. if (info->lock_ae != lock)
  185. ret = m5mols_write(&info->sd, AE_LOCK,
  186. lock ? REG_AE_LOCK : REG_AE_UNLOCK);
  187. if (!ret)
  188. info->lock_ae = lock;
  189. return ret;
  190. }
  191. static int m5mols_lock_awb(struct m5mols_info *info, bool lock)
  192. {
  193. int ret = 0;
  194. if (info->lock_awb != lock)
  195. ret = m5mols_write(&info->sd, AWB_LOCK,
  196. lock ? REG_AWB_LOCK : REG_AWB_UNLOCK);
  197. if (!ret)
  198. info->lock_awb = lock;
  199. return ret;
  200. }
  201. /* m5mols_lock_3a() - Lock 3A(Auto Exposure, Auto Whitebalance, Auto Focus) */
  202. int m5mols_lock_3a(struct m5mols_info *info, bool lock)
  203. {
  204. int ret;
  205. ret = m5mols_lock_ae(info, lock);
  206. if (!ret)
  207. ret = m5mols_lock_awb(info, lock);
  208. /* Don't need to handle unlocking AF */
  209. if (!ret && is_available_af(info) && lock)
  210. ret = m5mols_write(&info->sd, AF_EXECUTE, REG_AF_STOP);
  211. return ret;
  212. }
  213. /* m5mols_set_ctrl() - The main s_ctrl function called by m5mols_set_ctrl() */
  214. int m5mols_set_ctrl(struct v4l2_ctrl *ctrl)
  215. {
  216. struct v4l2_subdev *sd = to_sd(ctrl);
  217. struct m5mols_info *info = to_m5mols(sd);
  218. int ret;
  219. switch (ctrl->id) {
  220. case V4L2_CID_ZOOM_ABSOLUTE:
  221. return m5mols_write(sd, MON_ZOOM, ctrl->val);
  222. case V4L2_CID_EXPOSURE_AUTO:
  223. ret = m5mols_lock_ae(info,
  224. ctrl->val == V4L2_EXPOSURE_AUTO ? false : true);
  225. if (!ret && ctrl->val == V4L2_EXPOSURE_AUTO)
  226. ret = m5mols_write(sd, AE_MODE, REG_AE_ALL);
  227. if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL) {
  228. int val = info->exposure->val;
  229. ret = m5mols_write(sd, AE_MODE, REG_AE_OFF);
  230. if (!ret)
  231. ret = m5mols_write(sd, AE_MAN_GAIN_MON, val);
  232. if (!ret)
  233. ret = m5mols_write(sd, AE_MAN_GAIN_CAP, val);
  234. }
  235. return ret;
  236. case V4L2_CID_AUTO_WHITE_BALANCE:
  237. ret = m5mols_lock_awb(info, ctrl->val ? false : true);
  238. if (!ret)
  239. ret = m5mols_write(sd, AWB_MODE, ctrl->val ?
  240. REG_AWB_AUTO : REG_AWB_PRESET);
  241. return ret;
  242. case V4L2_CID_SATURATION:
  243. ret = m5mols_write(sd, MON_CHROMA_LVL, ctrl->val);
  244. if (!ret)
  245. ret = m5mols_write(sd, MON_CHROMA_EN, REG_CHROMA_ON);
  246. return ret;
  247. case V4L2_CID_COLORFX:
  248. /*
  249. * This control uses two kinds of registers: normal & color.
  250. * The normal effect belongs to category 1, while the color
  251. * one belongs to category 2.
  252. *
  253. * The normal effect uses one register: CAT1_EFFECT.
  254. * The color effect uses three registers:
  255. * CAT2_COLOR_EFFECT, CAT2_CFIXR, CAT2_CFIXB.
  256. */
  257. ret = m5mols_write(sd, PARM_EFFECT,
  258. ctrl->val == V4L2_COLORFX_NEGATIVE ? REG_EFFECT_NEGA :
  259. ctrl->val == V4L2_COLORFX_EMBOSS ? REG_EFFECT_EMBOSS :
  260. REG_EFFECT_OFF);
  261. if (!ret)
  262. ret = m5mols_write(sd, MON_EFFECT,
  263. ctrl->val == V4L2_COLORFX_SEPIA ?
  264. REG_COLOR_EFFECT_ON : REG_COLOR_EFFECT_OFF);
  265. if (!ret)
  266. ret = m5mols_write(sd, MON_CFIXR,
  267. ctrl->val == V4L2_COLORFX_SEPIA ?
  268. REG_CFIXR_SEPIA : 0);
  269. if (!ret)
  270. ret = m5mols_write(sd, MON_CFIXB,
  271. ctrl->val == V4L2_COLORFX_SEPIA ?
  272. REG_CFIXB_SEPIA : 0);
  273. return ret;
  274. }
  275. return -EINVAL;
  276. }