cx23885-cards.c 45 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include <linux/firmware.h>
  27. #include <misc/altera.h>
  28. #include "cx23885.h"
  29. #include "tuner-xc2028.h"
  30. #include "netup-eeprom.h"
  31. #include "netup-init.h"
  32. #include "altera-ci.h"
  33. #include "xc4000.h"
  34. #include "xc5000.h"
  35. #include "cx23888-ir.h"
  36. static unsigned int netup_card_rev = 1;
  37. module_param(netup_card_rev, int, 0644);
  38. MODULE_PARM_DESC(netup_card_rev,
  39. "NetUP Dual DVB-T/C CI card revision");
  40. static unsigned int enable_885_ir;
  41. module_param(enable_885_ir, int, 0644);
  42. MODULE_PARM_DESC(enable_885_ir,
  43. "Enable integrated IR controller for supported\n"
  44. "\t\t CX2388[57] boards that are wired for it:\n"
  45. "\t\t\tHVR-1250 (reported safe)\n"
  46. "\t\t\tTeVii S470 (reported unsafe)\n"
  47. "\t\t This can cause an interrupt storm with some cards.\n"
  48. "\t\t Default: 0 [Disabled]");
  49. /* ------------------------------------------------------------------ */
  50. /* board config info */
  51. struct cx23885_board cx23885_boards[] = {
  52. [CX23885_BOARD_UNKNOWN] = {
  53. .name = "UNKNOWN/GENERIC",
  54. /* Ensure safe default for unknown boards */
  55. .clk_freq = 0,
  56. .input = {{
  57. .type = CX23885_VMUX_COMPOSITE1,
  58. .vmux = 0,
  59. }, {
  60. .type = CX23885_VMUX_COMPOSITE2,
  61. .vmux = 1,
  62. }, {
  63. .type = CX23885_VMUX_COMPOSITE3,
  64. .vmux = 2,
  65. }, {
  66. .type = CX23885_VMUX_COMPOSITE4,
  67. .vmux = 3,
  68. } },
  69. },
  70. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  71. .name = "Hauppauge WinTV-HVR1800lp",
  72. .portc = CX23885_MPEG_DVB,
  73. .input = {{
  74. .type = CX23885_VMUX_TELEVISION,
  75. .vmux = 0,
  76. .gpio0 = 0xff00,
  77. }, {
  78. .type = CX23885_VMUX_DEBUG,
  79. .vmux = 0,
  80. .gpio0 = 0xff01,
  81. }, {
  82. .type = CX23885_VMUX_COMPOSITE1,
  83. .vmux = 1,
  84. .gpio0 = 0xff02,
  85. }, {
  86. .type = CX23885_VMUX_SVIDEO,
  87. .vmux = 2,
  88. .gpio0 = 0xff02,
  89. } },
  90. },
  91. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  92. .name = "Hauppauge WinTV-HVR1800",
  93. .porta = CX23885_ANALOG_VIDEO,
  94. .portb = CX23885_MPEG_ENCODER,
  95. .portc = CX23885_MPEG_DVB,
  96. .tuner_type = TUNER_PHILIPS_TDA8290,
  97. .tuner_addr = 0x42, /* 0x84 >> 1 */
  98. .tuner_bus = 1,
  99. .input = {{
  100. .type = CX23885_VMUX_TELEVISION,
  101. .vmux = CX25840_VIN7_CH3 |
  102. CX25840_VIN5_CH2 |
  103. CX25840_VIN2_CH1,
  104. .amux = CX25840_AUDIO8,
  105. .gpio0 = 0,
  106. }, {
  107. .type = CX23885_VMUX_COMPOSITE1,
  108. .vmux = CX25840_VIN7_CH3 |
  109. CX25840_VIN4_CH2 |
  110. CX25840_VIN6_CH1,
  111. .amux = CX25840_AUDIO7,
  112. .gpio0 = 0,
  113. }, {
  114. .type = CX23885_VMUX_SVIDEO,
  115. .vmux = CX25840_VIN7_CH3 |
  116. CX25840_VIN4_CH2 |
  117. CX25840_VIN8_CH1 |
  118. CX25840_SVIDEO_ON,
  119. .amux = CX25840_AUDIO7,
  120. .gpio0 = 0,
  121. } },
  122. },
  123. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  124. .name = "Hauppauge WinTV-HVR1250",
  125. .portc = CX23885_MPEG_DVB,
  126. .input = {{
  127. .type = CX23885_VMUX_TELEVISION,
  128. .vmux = 0,
  129. .gpio0 = 0xff00,
  130. }, {
  131. .type = CX23885_VMUX_DEBUG,
  132. .vmux = 0,
  133. .gpio0 = 0xff01,
  134. }, {
  135. .type = CX23885_VMUX_COMPOSITE1,
  136. .vmux = 1,
  137. .gpio0 = 0xff02,
  138. }, {
  139. .type = CX23885_VMUX_SVIDEO,
  140. .vmux = 2,
  141. .gpio0 = 0xff02,
  142. } },
  143. },
  144. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  145. .name = "DViCO FusionHDTV5 Express",
  146. .portb = CX23885_MPEG_DVB,
  147. },
  148. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  149. .name = "Hauppauge WinTV-HVR1500Q",
  150. .portc = CX23885_MPEG_DVB,
  151. },
  152. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  153. .name = "Hauppauge WinTV-HVR1500",
  154. .porta = CX23885_ANALOG_VIDEO,
  155. .portc = CX23885_MPEG_DVB,
  156. .tuner_type = TUNER_XC2028,
  157. .tuner_addr = 0x61, /* 0xc2 >> 1 */
  158. .input = {{
  159. .type = CX23885_VMUX_TELEVISION,
  160. .vmux = CX25840_VIN7_CH3 |
  161. CX25840_VIN5_CH2 |
  162. CX25840_VIN2_CH1,
  163. .gpio0 = 0,
  164. }, {
  165. .type = CX23885_VMUX_COMPOSITE1,
  166. .vmux = CX25840_VIN7_CH3 |
  167. CX25840_VIN4_CH2 |
  168. CX25840_VIN6_CH1,
  169. .gpio0 = 0,
  170. }, {
  171. .type = CX23885_VMUX_SVIDEO,
  172. .vmux = CX25840_VIN7_CH3 |
  173. CX25840_VIN4_CH2 |
  174. CX25840_VIN8_CH1 |
  175. CX25840_SVIDEO_ON,
  176. .gpio0 = 0,
  177. } },
  178. },
  179. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  180. .name = "Hauppauge WinTV-HVR1200",
  181. .portc = CX23885_MPEG_DVB,
  182. },
  183. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  184. .name = "Hauppauge WinTV-HVR1700",
  185. .portc = CX23885_MPEG_DVB,
  186. },
  187. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  188. .name = "Hauppauge WinTV-HVR1400",
  189. .portc = CX23885_MPEG_DVB,
  190. },
  191. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  192. .name = "DViCO FusionHDTV7 Dual Express",
  193. .portb = CX23885_MPEG_DVB,
  194. .portc = CX23885_MPEG_DVB,
  195. },
  196. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  197. .name = "DViCO FusionHDTV DVB-T Dual Express",
  198. .portb = CX23885_MPEG_DVB,
  199. .portc = CX23885_MPEG_DVB,
  200. },
  201. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  202. .name = "Leadtek Winfast PxDVR3200 H",
  203. .portc = CX23885_MPEG_DVB,
  204. },
  205. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
  206. .name = "Leadtek Winfast PxDVR3200 H XC4000",
  207. .porta = CX23885_ANALOG_VIDEO,
  208. .portc = CX23885_MPEG_DVB,
  209. .tuner_type = TUNER_XC4000,
  210. .tuner_addr = 0x61,
  211. .radio_type = UNSET,
  212. .radio_addr = ADDR_UNSET,
  213. .input = {{
  214. .type = CX23885_VMUX_TELEVISION,
  215. .vmux = CX25840_VIN2_CH1 |
  216. CX25840_VIN5_CH2 |
  217. CX25840_NONE0_CH3,
  218. }, {
  219. .type = CX23885_VMUX_COMPOSITE1,
  220. .vmux = CX25840_COMPOSITE1,
  221. }, {
  222. .type = CX23885_VMUX_SVIDEO,
  223. .vmux = CX25840_SVIDEO_LUMA3 |
  224. CX25840_SVIDEO_CHROMA4,
  225. }, {
  226. .type = CX23885_VMUX_COMPONENT,
  227. .vmux = CX25840_VIN7_CH1 |
  228. CX25840_VIN6_CH2 |
  229. CX25840_VIN8_CH3 |
  230. CX25840_COMPONENT_ON,
  231. } },
  232. },
  233. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  234. .name = "Compro VideoMate E650F",
  235. .portc = CX23885_MPEG_DVB,
  236. },
  237. [CX23885_BOARD_TBS_6920] = {
  238. .name = "TurboSight TBS 6920",
  239. .portb = CX23885_MPEG_DVB,
  240. },
  241. [CX23885_BOARD_TEVII_S470] = {
  242. .name = "TeVii S470",
  243. .portb = CX23885_MPEG_DVB,
  244. },
  245. [CX23885_BOARD_DVBWORLD_2005] = {
  246. .name = "DVBWorld DVB-S2 2005",
  247. .portb = CX23885_MPEG_DVB,
  248. },
  249. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  250. .ci_type = 1,
  251. .name = "NetUP Dual DVB-S2 CI",
  252. .portb = CX23885_MPEG_DVB,
  253. .portc = CX23885_MPEG_DVB,
  254. },
  255. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  256. .name = "Hauppauge WinTV-HVR1270",
  257. .portc = CX23885_MPEG_DVB,
  258. },
  259. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  260. .name = "Hauppauge WinTV-HVR1275",
  261. .portc = CX23885_MPEG_DVB,
  262. },
  263. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  264. .name = "Hauppauge WinTV-HVR1255",
  265. .portc = CX23885_MPEG_DVB,
  266. },
  267. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  268. .name = "Hauppauge WinTV-HVR1210",
  269. .portc = CX23885_MPEG_DVB,
  270. },
  271. [CX23885_BOARD_MYGICA_X8506] = {
  272. .name = "Mygica X8506 DMB-TH",
  273. .tuner_type = TUNER_XC5000,
  274. .tuner_addr = 0x61,
  275. .tuner_bus = 1,
  276. .porta = CX23885_ANALOG_VIDEO,
  277. .portb = CX23885_MPEG_DVB,
  278. .input = {
  279. {
  280. .type = CX23885_VMUX_TELEVISION,
  281. .vmux = CX25840_COMPOSITE2,
  282. },
  283. {
  284. .type = CX23885_VMUX_COMPOSITE1,
  285. .vmux = CX25840_COMPOSITE8,
  286. },
  287. {
  288. .type = CX23885_VMUX_SVIDEO,
  289. .vmux = CX25840_SVIDEO_LUMA3 |
  290. CX25840_SVIDEO_CHROMA4,
  291. },
  292. {
  293. .type = CX23885_VMUX_COMPONENT,
  294. .vmux = CX25840_COMPONENT_ON |
  295. CX25840_VIN1_CH1 |
  296. CX25840_VIN6_CH2 |
  297. CX25840_VIN7_CH3,
  298. },
  299. },
  300. },
  301. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  302. .name = "Magic-Pro ProHDTV Extreme 2",
  303. .tuner_type = TUNER_XC5000,
  304. .tuner_addr = 0x61,
  305. .tuner_bus = 1,
  306. .porta = CX23885_ANALOG_VIDEO,
  307. .portb = CX23885_MPEG_DVB,
  308. .input = {
  309. {
  310. .type = CX23885_VMUX_TELEVISION,
  311. .vmux = CX25840_COMPOSITE2,
  312. },
  313. {
  314. .type = CX23885_VMUX_COMPOSITE1,
  315. .vmux = CX25840_COMPOSITE8,
  316. },
  317. {
  318. .type = CX23885_VMUX_SVIDEO,
  319. .vmux = CX25840_SVIDEO_LUMA3 |
  320. CX25840_SVIDEO_CHROMA4,
  321. },
  322. {
  323. .type = CX23885_VMUX_COMPONENT,
  324. .vmux = CX25840_COMPONENT_ON |
  325. CX25840_VIN1_CH1 |
  326. CX25840_VIN6_CH2 |
  327. CX25840_VIN7_CH3,
  328. },
  329. },
  330. },
  331. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  332. .name = "Hauppauge WinTV-HVR1850",
  333. .porta = CX23885_ANALOG_VIDEO,
  334. .portb = CX23885_MPEG_ENCODER,
  335. .portc = CX23885_MPEG_DVB,
  336. .tuner_type = TUNER_ABSENT,
  337. .tuner_addr = 0x42, /* 0x84 >> 1 */
  338. .force_bff = 1,
  339. .input = {{
  340. .type = CX23885_VMUX_TELEVISION,
  341. .vmux = CX25840_VIN7_CH3 |
  342. CX25840_VIN5_CH2 |
  343. CX25840_VIN2_CH1 |
  344. CX25840_DIF_ON,
  345. .amux = CX25840_AUDIO8,
  346. }, {
  347. .type = CX23885_VMUX_COMPOSITE1,
  348. .vmux = CX25840_VIN7_CH3 |
  349. CX25840_VIN4_CH2 |
  350. CX25840_VIN6_CH1,
  351. .amux = CX25840_AUDIO7,
  352. }, {
  353. .type = CX23885_VMUX_SVIDEO,
  354. .vmux = CX25840_VIN7_CH3 |
  355. CX25840_VIN4_CH2 |
  356. CX25840_VIN8_CH1 |
  357. CX25840_SVIDEO_ON,
  358. .amux = CX25840_AUDIO7,
  359. } },
  360. },
  361. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  362. .name = "Compro VideoMate E800",
  363. .portc = CX23885_MPEG_DVB,
  364. },
  365. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  366. .name = "Hauppauge WinTV-HVR1290",
  367. .portc = CX23885_MPEG_DVB,
  368. },
  369. [CX23885_BOARD_MYGICA_X8558PRO] = {
  370. .name = "Mygica X8558 PRO DMB-TH",
  371. .portb = CX23885_MPEG_DVB,
  372. .portc = CX23885_MPEG_DVB,
  373. },
  374. [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
  375. .name = "LEADTEK WinFast PxTV1200",
  376. .porta = CX23885_ANALOG_VIDEO,
  377. .tuner_type = TUNER_XC2028,
  378. .tuner_addr = 0x61,
  379. .tuner_bus = 1,
  380. .input = {{
  381. .type = CX23885_VMUX_TELEVISION,
  382. .vmux = CX25840_VIN2_CH1 |
  383. CX25840_VIN5_CH2 |
  384. CX25840_NONE0_CH3,
  385. }, {
  386. .type = CX23885_VMUX_COMPOSITE1,
  387. .vmux = CX25840_COMPOSITE1,
  388. }, {
  389. .type = CX23885_VMUX_SVIDEO,
  390. .vmux = CX25840_SVIDEO_LUMA3 |
  391. CX25840_SVIDEO_CHROMA4,
  392. }, {
  393. .type = CX23885_VMUX_COMPONENT,
  394. .vmux = CX25840_VIN7_CH1 |
  395. CX25840_VIN6_CH2 |
  396. CX25840_VIN8_CH3 |
  397. CX25840_COMPONENT_ON,
  398. } },
  399. },
  400. [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
  401. .name = "GoTView X5 3D Hybrid",
  402. .tuner_type = TUNER_XC5000,
  403. .tuner_addr = 0x64,
  404. .tuner_bus = 1,
  405. .porta = CX23885_ANALOG_VIDEO,
  406. .portb = CX23885_MPEG_DVB,
  407. .input = {{
  408. .type = CX23885_VMUX_TELEVISION,
  409. .vmux = CX25840_VIN2_CH1 |
  410. CX25840_VIN5_CH2,
  411. .gpio0 = 0x02,
  412. }, {
  413. .type = CX23885_VMUX_COMPOSITE1,
  414. .vmux = CX23885_VMUX_COMPOSITE1,
  415. }, {
  416. .type = CX23885_VMUX_SVIDEO,
  417. .vmux = CX25840_SVIDEO_LUMA3 |
  418. CX25840_SVIDEO_CHROMA4,
  419. } },
  420. },
  421. [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
  422. .ci_type = 2,
  423. .name = "NetUP Dual DVB-T/C-CI RF",
  424. .porta = CX23885_ANALOG_VIDEO,
  425. .portb = CX23885_MPEG_DVB,
  426. .portc = CX23885_MPEG_DVB,
  427. .num_fds_portb = 2,
  428. .num_fds_portc = 2,
  429. .tuner_type = TUNER_XC5000,
  430. .tuner_addr = 0x64,
  431. .input = { {
  432. .type = CX23885_VMUX_TELEVISION,
  433. .vmux = CX25840_COMPOSITE1,
  434. } },
  435. },
  436. [CX23885_BOARD_MPX885] = {
  437. .name = "MPX-885",
  438. .porta = CX23885_ANALOG_VIDEO,
  439. .input = {{
  440. .type = CX23885_VMUX_COMPOSITE1,
  441. .vmux = CX25840_COMPOSITE1,
  442. .amux = CX25840_AUDIO6,
  443. .gpio0 = 0,
  444. }, {
  445. .type = CX23885_VMUX_COMPOSITE2,
  446. .vmux = CX25840_COMPOSITE2,
  447. .amux = CX25840_AUDIO6,
  448. .gpio0 = 0,
  449. }, {
  450. .type = CX23885_VMUX_COMPOSITE3,
  451. .vmux = CX25840_COMPOSITE3,
  452. .amux = CX25840_AUDIO7,
  453. .gpio0 = 0,
  454. }, {
  455. .type = CX23885_VMUX_COMPOSITE4,
  456. .vmux = CX25840_COMPOSITE4,
  457. .amux = CX25840_AUDIO7,
  458. .gpio0 = 0,
  459. } },
  460. },
  461. [CX23885_BOARD_MYGICA_X8507] = {
  462. .name = "Mygica X8507",
  463. .tuner_type = TUNER_XC5000,
  464. .tuner_addr = 0x61,
  465. .tuner_bus = 1,
  466. .porta = CX23885_ANALOG_VIDEO,
  467. .input = {
  468. {
  469. .type = CX23885_VMUX_TELEVISION,
  470. .vmux = CX25840_COMPOSITE2,
  471. .amux = CX25840_AUDIO8,
  472. },
  473. {
  474. .type = CX23885_VMUX_COMPOSITE1,
  475. .vmux = CX25840_COMPOSITE8,
  476. },
  477. {
  478. .type = CX23885_VMUX_SVIDEO,
  479. .vmux = CX25840_SVIDEO_LUMA3 |
  480. CX25840_SVIDEO_CHROMA4,
  481. },
  482. {
  483. .type = CX23885_VMUX_COMPONENT,
  484. .vmux = CX25840_COMPONENT_ON |
  485. CX25840_VIN1_CH1 |
  486. CX25840_VIN6_CH2 |
  487. CX25840_VIN7_CH3,
  488. },
  489. },
  490. },
  491. [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
  492. .name = "TerraTec Cinergy T PCIe Dual",
  493. .portb = CX23885_MPEG_DVB,
  494. .portc = CX23885_MPEG_DVB,
  495. }
  496. };
  497. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  498. /* ------------------------------------------------------------------ */
  499. /* PCI subsystem IDs */
  500. struct cx23885_subid cx23885_subids[] = {
  501. {
  502. .subvendor = 0x0070,
  503. .subdevice = 0x3400,
  504. .card = CX23885_BOARD_UNKNOWN,
  505. }, {
  506. .subvendor = 0x0070,
  507. .subdevice = 0x7600,
  508. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  509. }, {
  510. .subvendor = 0x0070,
  511. .subdevice = 0x7800,
  512. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  513. }, {
  514. .subvendor = 0x0070,
  515. .subdevice = 0x7801,
  516. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  517. }, {
  518. .subvendor = 0x0070,
  519. .subdevice = 0x7809,
  520. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  521. }, {
  522. .subvendor = 0x0070,
  523. .subdevice = 0x7911,
  524. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  525. }, {
  526. .subvendor = 0x18ac,
  527. .subdevice = 0xd500,
  528. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  529. }, {
  530. .subvendor = 0x0070,
  531. .subdevice = 0x7790,
  532. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  533. }, {
  534. .subvendor = 0x0070,
  535. .subdevice = 0x7797,
  536. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  537. }, {
  538. .subvendor = 0x0070,
  539. .subdevice = 0x7710,
  540. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  541. }, {
  542. .subvendor = 0x0070,
  543. .subdevice = 0x7717,
  544. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  545. }, {
  546. .subvendor = 0x0070,
  547. .subdevice = 0x71d1,
  548. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  549. }, {
  550. .subvendor = 0x0070,
  551. .subdevice = 0x71d3,
  552. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  553. }, {
  554. .subvendor = 0x0070,
  555. .subdevice = 0x8101,
  556. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  557. }, {
  558. .subvendor = 0x0070,
  559. .subdevice = 0x8010,
  560. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  561. }, {
  562. .subvendor = 0x18ac,
  563. .subdevice = 0xd618,
  564. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  565. }, {
  566. .subvendor = 0x18ac,
  567. .subdevice = 0xdb78,
  568. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  569. }, {
  570. .subvendor = 0x107d,
  571. .subdevice = 0x6681,
  572. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  573. }, {
  574. .subvendor = 0x107d,
  575. .subdevice = 0x6f39,
  576. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
  577. }, {
  578. .subvendor = 0x185b,
  579. .subdevice = 0xe800,
  580. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  581. }, {
  582. .subvendor = 0x6920,
  583. .subdevice = 0x8888,
  584. .card = CX23885_BOARD_TBS_6920,
  585. }, {
  586. .subvendor = 0xd470,
  587. .subdevice = 0x9022,
  588. .card = CX23885_BOARD_TEVII_S470,
  589. }, {
  590. .subvendor = 0x0001,
  591. .subdevice = 0x2005,
  592. .card = CX23885_BOARD_DVBWORLD_2005,
  593. }, {
  594. .subvendor = 0x1b55,
  595. .subdevice = 0x2a2c,
  596. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  597. }, {
  598. .subvendor = 0x0070,
  599. .subdevice = 0x2211,
  600. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  601. }, {
  602. .subvendor = 0x0070,
  603. .subdevice = 0x2215,
  604. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  605. }, {
  606. .subvendor = 0x0070,
  607. .subdevice = 0x221d,
  608. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  609. }, {
  610. .subvendor = 0x0070,
  611. .subdevice = 0x2251,
  612. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  613. }, {
  614. .subvendor = 0x0070,
  615. .subdevice = 0x2259,
  616. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  617. }, {
  618. .subvendor = 0x0070,
  619. .subdevice = 0x2291,
  620. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  621. }, {
  622. .subvendor = 0x0070,
  623. .subdevice = 0x2295,
  624. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  625. }, {
  626. .subvendor = 0x0070,
  627. .subdevice = 0x2299,
  628. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  629. }, {
  630. .subvendor = 0x0070,
  631. .subdevice = 0x229d,
  632. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  633. }, {
  634. .subvendor = 0x0070,
  635. .subdevice = 0x22f0,
  636. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  637. }, {
  638. .subvendor = 0x0070,
  639. .subdevice = 0x22f1,
  640. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  641. }, {
  642. .subvendor = 0x0070,
  643. .subdevice = 0x22f2,
  644. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  645. }, {
  646. .subvendor = 0x0070,
  647. .subdevice = 0x22f3,
  648. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  649. }, {
  650. .subvendor = 0x0070,
  651. .subdevice = 0x22f4,
  652. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  653. }, {
  654. .subvendor = 0x0070,
  655. .subdevice = 0x22f5,
  656. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  657. }, {
  658. .subvendor = 0x14f1,
  659. .subdevice = 0x8651,
  660. .card = CX23885_BOARD_MYGICA_X8506,
  661. }, {
  662. .subvendor = 0x14f1,
  663. .subdevice = 0x8657,
  664. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  665. }, {
  666. .subvendor = 0x0070,
  667. .subdevice = 0x8541,
  668. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  669. }, {
  670. .subvendor = 0x1858,
  671. .subdevice = 0xe800,
  672. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  673. }, {
  674. .subvendor = 0x0070,
  675. .subdevice = 0x8551,
  676. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  677. }, {
  678. .subvendor = 0x14f1,
  679. .subdevice = 0x8578,
  680. .card = CX23885_BOARD_MYGICA_X8558PRO,
  681. }, {
  682. .subvendor = 0x107d,
  683. .subdevice = 0x6f22,
  684. .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
  685. }, {
  686. .subvendor = 0x5654,
  687. .subdevice = 0x2390,
  688. .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
  689. }, {
  690. .subvendor = 0x1b55,
  691. .subdevice = 0xe2e4,
  692. .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
  693. }, {
  694. .subvendor = 0x14f1,
  695. .subdevice = 0x8502,
  696. .card = CX23885_BOARD_MYGICA_X8507,
  697. }, {
  698. .subvendor = 0x153b,
  699. .subdevice = 0x117e,
  700. .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
  701. },
  702. };
  703. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  704. void cx23885_card_list(struct cx23885_dev *dev)
  705. {
  706. int i;
  707. if (0 == dev->pci->subsystem_vendor &&
  708. 0 == dev->pci->subsystem_device) {
  709. printk(KERN_INFO
  710. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  711. "%s: be autodetected. Pass card=<n> insmod option\n"
  712. "%s: to workaround that. Redirect complaints to the\n"
  713. "%s: vendor of the TV card. Best regards,\n"
  714. "%s: -- tux\n",
  715. dev->name, dev->name, dev->name, dev->name, dev->name);
  716. } else {
  717. printk(KERN_INFO
  718. "%s: Your board isn't known (yet) to the driver.\n"
  719. "%s: Try to pick one of the existing card configs via\n"
  720. "%s: card=<n> insmod option. Updating to the latest\n"
  721. "%s: version might help as well.\n",
  722. dev->name, dev->name, dev->name, dev->name);
  723. }
  724. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  725. dev->name);
  726. for (i = 0; i < cx23885_bcount; i++)
  727. printk(KERN_INFO "%s: card=%d -> %s\n",
  728. dev->name, i, cx23885_boards[i].name);
  729. }
  730. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  731. {
  732. struct tveeprom tv;
  733. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  734. eeprom_data);
  735. /* Make sure we support the board model */
  736. switch (tv.model) {
  737. case 22001:
  738. /* WinTV-HVR1270 (PCIe, Retail, half height)
  739. * ATSC/QAM and basic analog, IR Blast */
  740. case 22009:
  741. /* WinTV-HVR1210 (PCIe, Retail, half height)
  742. * DVB-T and basic analog, IR Blast */
  743. case 22011:
  744. /* WinTV-HVR1270 (PCIe, Retail, half height)
  745. * ATSC/QAM and basic analog, IR Recv */
  746. case 22019:
  747. /* WinTV-HVR1210 (PCIe, Retail, half height)
  748. * DVB-T and basic analog, IR Recv */
  749. case 22021:
  750. /* WinTV-HVR1275 (PCIe, Retail, half height)
  751. * ATSC/QAM and basic analog, IR Recv */
  752. case 22029:
  753. /* WinTV-HVR1210 (PCIe, Retail, half height)
  754. * DVB-T and basic analog, IR Recv */
  755. case 22101:
  756. /* WinTV-HVR1270 (PCIe, Retail, full height)
  757. * ATSC/QAM and basic analog, IR Blast */
  758. case 22109:
  759. /* WinTV-HVR1210 (PCIe, Retail, full height)
  760. * DVB-T and basic analog, IR Blast */
  761. case 22111:
  762. /* WinTV-HVR1270 (PCIe, Retail, full height)
  763. * ATSC/QAM and basic analog, IR Recv */
  764. case 22119:
  765. /* WinTV-HVR1210 (PCIe, Retail, full height)
  766. * DVB-T and basic analog, IR Recv */
  767. case 22121:
  768. /* WinTV-HVR1275 (PCIe, Retail, full height)
  769. * ATSC/QAM and basic analog, IR Recv */
  770. case 22129:
  771. /* WinTV-HVR1210 (PCIe, Retail, full height)
  772. * DVB-T and basic analog, IR Recv */
  773. case 71009:
  774. /* WinTV-HVR1200 (PCIe, Retail, full height)
  775. * DVB-T and basic analog */
  776. case 71359:
  777. /* WinTV-HVR1200 (PCIe, OEM, half height)
  778. * DVB-T and basic analog */
  779. case 71439:
  780. /* WinTV-HVR1200 (PCIe, OEM, half height)
  781. * DVB-T and basic analog */
  782. case 71449:
  783. /* WinTV-HVR1200 (PCIe, OEM, full height)
  784. * DVB-T and basic analog */
  785. case 71939:
  786. /* WinTV-HVR1200 (PCIe, OEM, half height)
  787. * DVB-T and basic analog */
  788. case 71949:
  789. /* WinTV-HVR1200 (PCIe, OEM, full height)
  790. * DVB-T and basic analog */
  791. case 71959:
  792. /* WinTV-HVR1200 (PCIe, OEM, full height)
  793. * DVB-T and basic analog */
  794. case 71979:
  795. /* WinTV-HVR1200 (PCIe, OEM, half height)
  796. * DVB-T and basic analog */
  797. case 71999:
  798. /* WinTV-HVR1200 (PCIe, OEM, full height)
  799. * DVB-T and basic analog */
  800. case 76601:
  801. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  802. channel ATSC and MPEG2 HW Encoder */
  803. case 77001:
  804. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  805. and Basic analog */
  806. case 77011:
  807. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  808. and Basic analog */
  809. case 77041:
  810. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  811. and Basic analog */
  812. case 77051:
  813. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  814. and Basic analog */
  815. case 78011:
  816. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  817. Dual channel ATSC and MPEG2 HW Encoder */
  818. case 78501:
  819. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  820. Dual channel ATSC and MPEG2 HW Encoder */
  821. case 78521:
  822. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  823. Dual channel ATSC and MPEG2 HW Encoder */
  824. case 78531:
  825. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  826. Dual channel ATSC and MPEG2 HW Encoder */
  827. case 78631:
  828. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  829. Dual channel ATSC and MPEG2 HW Encoder */
  830. case 79001:
  831. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  832. ATSC and Basic analog */
  833. case 79101:
  834. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  835. ATSC and Basic analog */
  836. case 79501:
  837. /* WinTV-HVR1250 (PCIe, No IR, half height,
  838. ATSC [at least] and Basic analog) */
  839. case 79561:
  840. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  841. ATSC and Basic analog */
  842. case 79571:
  843. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  844. ATSC and Basic analog */
  845. case 79671:
  846. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  847. ATSC and Basic analog */
  848. case 80019:
  849. /* WinTV-HVR1400 (Express Card, Retail, IR,
  850. * DVB-T and Basic analog */
  851. case 81509:
  852. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  853. * DVB-T and MPEG2 HW Encoder */
  854. case 81519:
  855. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  856. * DVB-T and MPEG2 HW Encoder */
  857. break;
  858. case 85021:
  859. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  860. Dual channel ATSC and MPEG2 HW Encoder */
  861. break;
  862. case 85721:
  863. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  864. Dual channel ATSC and Basic analog */
  865. break;
  866. default:
  867. printk(KERN_WARNING "%s: warning: "
  868. "unknown hauppauge model #%d\n",
  869. dev->name, tv.model);
  870. break;
  871. }
  872. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  873. dev->name, tv.model);
  874. }
  875. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  876. {
  877. struct cx23885_tsport *port = priv;
  878. struct cx23885_dev *dev = port->dev;
  879. u32 bitmask = 0;
  880. if (command == XC2028_RESET_CLK)
  881. return 0;
  882. if (command != 0) {
  883. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  884. __func__, command);
  885. return -EINVAL;
  886. }
  887. switch (dev->board) {
  888. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  889. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  890. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  891. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  892. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  893. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  894. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  895. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  896. /* Tuner Reset Command */
  897. bitmask = 0x04;
  898. break;
  899. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  900. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  901. /* Two identical tuners on two different i2c buses,
  902. * we need to reset the correct gpio. */
  903. if (port->nr == 1)
  904. bitmask = 0x01;
  905. else if (port->nr == 2)
  906. bitmask = 0x04;
  907. break;
  908. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  909. /* Tuner Reset Command */
  910. bitmask = 0x02;
  911. break;
  912. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  913. altera_ci_tuner_reset(dev, port->nr);
  914. break;
  915. }
  916. if (bitmask) {
  917. /* Drive the tuner into reset and back out */
  918. cx_clear(GP0_IO, bitmask);
  919. mdelay(200);
  920. cx_set(GP0_IO, bitmask);
  921. }
  922. return 0;
  923. }
  924. void cx23885_gpio_setup(struct cx23885_dev *dev)
  925. {
  926. switch (dev->board) {
  927. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  928. /* GPIO-0 cx24227 demodulator reset */
  929. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  930. break;
  931. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  932. /* GPIO-0 cx24227 demodulator */
  933. /* GPIO-2 xc3028 tuner */
  934. /* Put the parts into reset */
  935. cx_set(GP0_IO, 0x00050000);
  936. cx_clear(GP0_IO, 0x00000005);
  937. msleep(5);
  938. /* Bring the parts out of reset */
  939. cx_set(GP0_IO, 0x00050005);
  940. break;
  941. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  942. /* GPIO-0 cx24227 demodulator reset */
  943. /* GPIO-2 xc5000 tuner reset */
  944. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  945. break;
  946. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  947. /* GPIO-0 656_CLK */
  948. /* GPIO-1 656_D0 */
  949. /* GPIO-2 8295A Reset */
  950. /* GPIO-3-10 cx23417 data0-7 */
  951. /* GPIO-11-14 cx23417 addr0-3 */
  952. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  953. /* GPIO-19 IR_RX */
  954. /* CX23417 GPIO's */
  955. /* EIO15 Zilog Reset */
  956. /* EIO14 S5H1409/CX24227 Reset */
  957. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  958. /* Put the demod into reset and protect the eeprom */
  959. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  960. mdelay(100);
  961. /* Bring the demod and blaster out of reset */
  962. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  963. mdelay(100);
  964. /* Force the TDA8295A into reset and back */
  965. cx23885_gpio_enable(dev, GPIO_2, 1);
  966. cx23885_gpio_set(dev, GPIO_2);
  967. mdelay(20);
  968. cx23885_gpio_clear(dev, GPIO_2);
  969. mdelay(20);
  970. cx23885_gpio_set(dev, GPIO_2);
  971. mdelay(20);
  972. break;
  973. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  974. /* GPIO-0 tda10048 demodulator reset */
  975. /* GPIO-2 tda18271 tuner reset */
  976. /* Put the parts into reset and back */
  977. cx_set(GP0_IO, 0x00050000);
  978. mdelay(20);
  979. cx_clear(GP0_IO, 0x00000005);
  980. mdelay(20);
  981. cx_set(GP0_IO, 0x00050005);
  982. break;
  983. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  984. /* GPIO-0 TDA10048 demodulator reset */
  985. /* GPIO-2 TDA8295A Reset */
  986. /* GPIO-3-10 cx23417 data0-7 */
  987. /* GPIO-11-14 cx23417 addr0-3 */
  988. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  989. /* The following GPIO's are on the interna AVCore (cx25840) */
  990. /* GPIO-19 IR_RX */
  991. /* GPIO-20 IR_TX 416/DVBT Select */
  992. /* GPIO-21 IIS DAT */
  993. /* GPIO-22 IIS WCLK */
  994. /* GPIO-23 IIS BCLK */
  995. /* Put the parts into reset and back */
  996. cx_set(GP0_IO, 0x00050000);
  997. mdelay(20);
  998. cx_clear(GP0_IO, 0x00000005);
  999. mdelay(20);
  1000. cx_set(GP0_IO, 0x00050005);
  1001. break;
  1002. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1003. /* GPIO-0 Dibcom7000p demodulator reset */
  1004. /* GPIO-2 xc3028L tuner reset */
  1005. /* GPIO-13 LED */
  1006. /* Put the parts into reset and back */
  1007. cx_set(GP0_IO, 0x00050000);
  1008. mdelay(20);
  1009. cx_clear(GP0_IO, 0x00000005);
  1010. mdelay(20);
  1011. cx_set(GP0_IO, 0x00050005);
  1012. break;
  1013. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1014. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  1015. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  1016. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  1017. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  1018. /* Put the parts into reset and back */
  1019. cx_set(GP0_IO, 0x000f0000);
  1020. mdelay(20);
  1021. cx_clear(GP0_IO, 0x0000000f);
  1022. mdelay(20);
  1023. cx_set(GP0_IO, 0x000f000f);
  1024. break;
  1025. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1026. /* GPIO-0 portb xc3028 reset */
  1027. /* GPIO-1 portb zl10353 reset */
  1028. /* GPIO-2 portc xc3028 reset */
  1029. /* GPIO-3 portc zl10353 reset */
  1030. /* Put the parts into reset and back */
  1031. cx_set(GP0_IO, 0x000f0000);
  1032. mdelay(20);
  1033. cx_clear(GP0_IO, 0x0000000f);
  1034. mdelay(20);
  1035. cx_set(GP0_IO, 0x000f000f);
  1036. break;
  1037. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1038. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1039. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1040. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1041. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1042. /* GPIO-2 xc3028 tuner reset */
  1043. /* The following GPIO's are on the internal AVCore (cx25840) */
  1044. /* GPIO-? zl10353 demod reset */
  1045. /* Put the parts into reset and back */
  1046. cx_set(GP0_IO, 0x00040000);
  1047. mdelay(20);
  1048. cx_clear(GP0_IO, 0x00000004);
  1049. mdelay(20);
  1050. cx_set(GP0_IO, 0x00040004);
  1051. break;
  1052. case CX23885_BOARD_TBS_6920:
  1053. cx_write(MC417_CTL, 0x00000036);
  1054. cx_write(MC417_OEN, 0x00001000);
  1055. cx_set(MC417_RWD, 0x00000002);
  1056. mdelay(200);
  1057. cx_clear(MC417_RWD, 0x00000800);
  1058. mdelay(200);
  1059. cx_set(MC417_RWD, 0x00000800);
  1060. mdelay(200);
  1061. break;
  1062. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1063. /* GPIO-0 INTA from CiMax1
  1064. GPIO-1 INTB from CiMax2
  1065. GPIO-2 reset chips
  1066. GPIO-3 to GPIO-10 data/addr for CA
  1067. GPIO-11 ~CS0 to CiMax1
  1068. GPIO-12 ~CS1 to CiMax2
  1069. GPIO-13 ADL0 load LSB addr
  1070. GPIO-14 ADL1 load MSB addr
  1071. GPIO-15 ~RDY from CiMax
  1072. GPIO-17 ~RD to CiMax
  1073. GPIO-18 ~WR to CiMax
  1074. */
  1075. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  1076. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  1077. cx_clear(GP0_IO, 0x00030004);
  1078. mdelay(100);/* reset delay */
  1079. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  1080. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  1081. /* GPIO-15 IN as ~ACK, rest as OUT */
  1082. cx_write(MC417_OEN, 0x00001000);
  1083. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  1084. cx_write(MC417_RWD, 0x0000c300);
  1085. /* enable irq */
  1086. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1087. break;
  1088. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1089. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1090. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1091. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1092. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  1093. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  1094. /* GPIO-9 Demod reset */
  1095. /* Put the parts into reset and back */
  1096. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  1097. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  1098. cx23885_gpio_clear(dev, GPIO_9);
  1099. mdelay(20);
  1100. cx23885_gpio_set(dev, GPIO_9);
  1101. break;
  1102. case CX23885_BOARD_MYGICA_X8506:
  1103. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1104. case CX23885_BOARD_MYGICA_X8507:
  1105. /* GPIO-0 (0)Analog / (1)Digital TV */
  1106. /* GPIO-1 reset XC5000 */
  1107. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  1108. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  1109. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  1110. mdelay(100);
  1111. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  1112. mdelay(100);
  1113. break;
  1114. case CX23885_BOARD_MYGICA_X8558PRO:
  1115. /* GPIO-0 reset first ATBM8830 */
  1116. /* GPIO-1 reset second ATBM8830 */
  1117. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  1118. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  1119. mdelay(100);
  1120. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  1121. mdelay(100);
  1122. break;
  1123. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1124. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1125. /* GPIO-0 656_CLK */
  1126. /* GPIO-1 656_D0 */
  1127. /* GPIO-2 Wake# */
  1128. /* GPIO-3-10 cx23417 data0-7 */
  1129. /* GPIO-11-14 cx23417 addr0-3 */
  1130. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  1131. /* GPIO-19 IR_RX */
  1132. /* GPIO-20 C_IR_TX */
  1133. /* GPIO-21 I2S DAT */
  1134. /* GPIO-22 I2S WCLK */
  1135. /* GPIO-23 I2S BCLK */
  1136. /* ALT GPIO: EXP GPIO LATCH */
  1137. /* CX23417 GPIO's */
  1138. /* GPIO-14 S5H1411/CX24228 Reset */
  1139. /* GPIO-13 EEPROM write protect */
  1140. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  1141. /* Put the demod into reset and protect the eeprom */
  1142. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  1143. mdelay(100);
  1144. /* Bring the demod out of reset */
  1145. mc417_gpio_set(dev, GPIO_14);
  1146. mdelay(100);
  1147. /* CX24228 GPIO */
  1148. /* Connected to IF / Mux */
  1149. break;
  1150. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1151. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  1152. break;
  1153. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1154. /* GPIO-0 ~INT in
  1155. GPIO-1 TMS out
  1156. GPIO-2 ~reset chips out
  1157. GPIO-3 to GPIO-10 data/addr for CA in/out
  1158. GPIO-11 ~CS out
  1159. GPIO-12 ADDR out
  1160. GPIO-13 ~WR out
  1161. GPIO-14 ~RD out
  1162. GPIO-15 ~RDY in
  1163. GPIO-16 TCK out
  1164. GPIO-17 TDO in
  1165. GPIO-18 TDI out
  1166. */
  1167. cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
  1168. /* GPIO-0 as INT, reset & TMS low */
  1169. cx_clear(GP0_IO, 0x00010006);
  1170. mdelay(100);/* reset delay */
  1171. cx_set(GP0_IO, 0x00000004); /* reset high */
  1172. cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
  1173. /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
  1174. cx_write(MC417_OEN, 0x00005000);
  1175. /* ~RD, ~WR high; ADDR low; ~CS high */
  1176. cx_write(MC417_RWD, 0x00000d00);
  1177. /* enable irq */
  1178. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1179. break;
  1180. }
  1181. }
  1182. int cx23885_ir_init(struct cx23885_dev *dev)
  1183. {
  1184. static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
  1185. {
  1186. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1187. .pin = CX23885_PIN_IR_RX_GPIO19,
  1188. .function = CX23885_PAD_IR_RX,
  1189. .value = 0,
  1190. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1191. }, {
  1192. .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
  1193. .pin = CX23885_PIN_IR_TX_GPIO20,
  1194. .function = CX23885_PAD_IR_TX,
  1195. .value = 0,
  1196. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1197. }
  1198. };
  1199. const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
  1200. static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
  1201. {
  1202. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1203. .pin = CX23885_PIN_IR_RX_GPIO19,
  1204. .function = CX23885_PAD_IR_RX,
  1205. .value = 0,
  1206. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1207. }
  1208. };
  1209. const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
  1210. struct v4l2_subdev_ir_parameters params;
  1211. int ret = 0;
  1212. switch (dev->board) {
  1213. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1214. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1215. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1216. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1217. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1218. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1219. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1220. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1221. /* FIXME: Implement me */
  1222. break;
  1223. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1224. ret = cx23888_ir_probe(dev);
  1225. if (ret)
  1226. break;
  1227. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1228. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1229. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1230. break;
  1231. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1232. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1233. ret = cx23888_ir_probe(dev);
  1234. if (ret)
  1235. break;
  1236. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1237. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1238. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1239. /*
  1240. * For these boards we need to invert the Tx output via the
  1241. * IR controller to have the LED off while idle
  1242. */
  1243. v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
  1244. params.enable = false;
  1245. params.shutdown = false;
  1246. params.invert_level = true;
  1247. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1248. params.shutdown = true;
  1249. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1250. break;
  1251. case CX23885_BOARD_TEVII_S470:
  1252. if (!enable_885_ir)
  1253. break;
  1254. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1255. if (dev->sd_ir == NULL) {
  1256. ret = -ENODEV;
  1257. break;
  1258. }
  1259. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1260. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1261. break;
  1262. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1263. if (!enable_885_ir)
  1264. break;
  1265. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1266. if (dev->sd_ir == NULL) {
  1267. ret = -ENODEV;
  1268. break;
  1269. }
  1270. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1271. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1272. break;
  1273. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1274. request_module("ir-kbd-i2c");
  1275. break;
  1276. }
  1277. return ret;
  1278. }
  1279. void cx23885_ir_fini(struct cx23885_dev *dev)
  1280. {
  1281. switch (dev->board) {
  1282. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1283. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1284. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1285. cx23885_irq_remove(dev, PCI_MSK_IR);
  1286. cx23888_ir_remove(dev);
  1287. dev->sd_ir = NULL;
  1288. break;
  1289. case CX23885_BOARD_TEVII_S470:
  1290. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1291. cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
  1292. /* sd_ir is a duplicate pointer to the AV Core, just clear it */
  1293. dev->sd_ir = NULL;
  1294. break;
  1295. }
  1296. }
  1297. int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
  1298. {
  1299. int data;
  1300. int tdo = 0;
  1301. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  1302. /*TMS*/
  1303. data = ((cx_read(GP0_IO)) & (~0x00000002));
  1304. data |= (tms ? 0x00020002 : 0x00020000);
  1305. cx_write(GP0_IO, data);
  1306. /*TDI*/
  1307. data = ((cx_read(MC417_RWD)) & (~0x0000a000));
  1308. data |= (tdi ? 0x00008000 : 0);
  1309. cx_write(MC417_RWD, data);
  1310. if (read_tdo)
  1311. tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
  1312. cx_write(MC417_RWD, data | 0x00002000);
  1313. udelay(1);
  1314. /*TCK*/
  1315. cx_write(MC417_RWD, data);
  1316. return tdo;
  1317. }
  1318. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  1319. {
  1320. switch (dev->board) {
  1321. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1322. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1323. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1324. if (dev->sd_ir)
  1325. cx23885_irq_add_enable(dev, PCI_MSK_IR);
  1326. break;
  1327. case CX23885_BOARD_TEVII_S470:
  1328. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1329. if (dev->sd_ir)
  1330. cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
  1331. break;
  1332. }
  1333. }
  1334. void cx23885_card_setup(struct cx23885_dev *dev)
  1335. {
  1336. struct cx23885_tsport *ts1 = &dev->ts1;
  1337. struct cx23885_tsport *ts2 = &dev->ts2;
  1338. static u8 eeprom[256];
  1339. if (dev->i2c_bus[0].i2c_rc == 0) {
  1340. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1341. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  1342. eeprom, sizeof(eeprom));
  1343. }
  1344. switch (dev->board) {
  1345. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1346. if (dev->i2c_bus[0].i2c_rc == 0) {
  1347. if (eeprom[0x80] != 0x84)
  1348. hauppauge_eeprom(dev, eeprom+0xc0);
  1349. else
  1350. hauppauge_eeprom(dev, eeprom+0x80);
  1351. }
  1352. break;
  1353. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1354. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1355. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1356. if (dev->i2c_bus[0].i2c_rc == 0)
  1357. hauppauge_eeprom(dev, eeprom+0x80);
  1358. break;
  1359. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1360. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1361. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1362. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1363. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1364. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1365. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1366. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1367. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1368. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1369. if (dev->i2c_bus[0].i2c_rc == 0)
  1370. hauppauge_eeprom(dev, eeprom+0xc0);
  1371. break;
  1372. }
  1373. switch (dev->board) {
  1374. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1375. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1376. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1377. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1378. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1379. /* break omitted intentionally */
  1380. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  1381. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1382. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1383. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1384. break;
  1385. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1386. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1387. /* Defaults for VID B - Analog encoder */
  1388. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  1389. ts1->gen_ctrl_val = 0x10e;
  1390. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1391. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1392. /* APB_TSVALERR_POL (active low)*/
  1393. ts1->vld_misc_val = 0x2000;
  1394. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  1395. cx_write(0x130184, 0xc);
  1396. /* Defaults for VID C */
  1397. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1398. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1399. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1400. break;
  1401. case CX23885_BOARD_TBS_6920:
  1402. ts1->gen_ctrl_val = 0x4; /* Parallel */
  1403. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1404. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1405. break;
  1406. case CX23885_BOARD_TEVII_S470:
  1407. case CX23885_BOARD_DVBWORLD_2005:
  1408. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1409. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1410. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1411. break;
  1412. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1413. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1414. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1415. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1416. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1417. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1418. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1419. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1420. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1421. break;
  1422. case CX23885_BOARD_MYGICA_X8506:
  1423. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1424. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1425. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1426. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1427. break;
  1428. case CX23885_BOARD_MYGICA_X8558PRO:
  1429. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1430. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1431. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1432. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1433. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1434. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1435. break;
  1436. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1437. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1438. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1439. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1440. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1441. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1442. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1443. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1444. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1445. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1446. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1447. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1448. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1449. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1450. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1451. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1452. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1453. default:
  1454. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1455. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1456. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1457. }
  1458. /* Certain boards support analog, or require the avcore to be
  1459. * loaded, ensure this happens.
  1460. */
  1461. switch (dev->board) {
  1462. case CX23885_BOARD_TEVII_S470:
  1463. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1464. /* Currently only enabled for the integrated IR controller */
  1465. if (!enable_885_ir)
  1466. break;
  1467. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1468. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1469. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1470. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1471. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1472. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1473. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1474. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1475. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1476. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1477. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1478. case CX23885_BOARD_MYGICA_X8506:
  1479. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1480. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1481. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1482. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1483. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1484. case CX23885_BOARD_MPX885:
  1485. case CX23885_BOARD_MYGICA_X8507:
  1486. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1487. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  1488. &dev->i2c_bus[2].i2c_adap,
  1489. "cx25840", 0x88 >> 1, NULL);
  1490. if (dev->sd_cx25840) {
  1491. dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
  1492. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  1493. }
  1494. break;
  1495. }
  1496. /* AUX-PLL 27MHz CLK */
  1497. switch (dev->board) {
  1498. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1499. netup_initialize(dev);
  1500. break;
  1501. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1502. int ret;
  1503. const struct firmware *fw;
  1504. const char *filename = "dvb-netup-altera-01.fw";
  1505. char *action = "configure";
  1506. static struct netup_card_info cinfo;
  1507. struct altera_config netup_config = {
  1508. .dev = dev,
  1509. .action = action,
  1510. .jtag_io = netup_jtag_io,
  1511. };
  1512. netup_initialize(dev);
  1513. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1514. if (netup_card_rev)
  1515. cinfo.rev = netup_card_rev;
  1516. switch (cinfo.rev) {
  1517. case 0x4:
  1518. filename = "dvb-netup-altera-04.fw";
  1519. break;
  1520. default:
  1521. filename = "dvb-netup-altera-01.fw";
  1522. break;
  1523. }
  1524. printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
  1525. cinfo.rev, filename);
  1526. ret = request_firmware(&fw, filename, &dev->pci->dev);
  1527. if (ret != 0)
  1528. printk(KERN_ERR "did not find the firmware file. (%s) "
  1529. "Please see linux/Documentation/dvb/ for more details "
  1530. "on firmware-problems.", filename);
  1531. else
  1532. altera_init(&netup_config, fw);
  1533. release_firmware(fw);
  1534. break;
  1535. }
  1536. }
  1537. }
  1538. /* ------------------------------------------------------------------ */