adv7343.c 12 KB

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  1. /*
  2. * adv7343 - ADV7343 Video Encoder Driver
  3. *
  4. * The encoder hardware does not support SECAM.
  5. *
  6. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/ctype.h>
  20. #include <linux/slab.h>
  21. #include <linux/i2c.h>
  22. #include <linux/device.h>
  23. #include <linux/delay.h>
  24. #include <linux/module.h>
  25. #include <linux/videodev2.h>
  26. #include <linux/uaccess.h>
  27. #include <media/adv7343.h>
  28. #include <media/v4l2-device.h>
  29. #include <media/v4l2-chip-ident.h>
  30. #include <media/v4l2-ctrls.h>
  31. #include "adv7343_regs.h"
  32. MODULE_DESCRIPTION("ADV7343 video encoder driver");
  33. MODULE_LICENSE("GPL");
  34. static int debug;
  35. module_param(debug, int, 0644);
  36. MODULE_PARM_DESC(debug, "Debug level 0-1");
  37. struct adv7343_state {
  38. struct v4l2_subdev sd;
  39. struct v4l2_ctrl_handler hdl;
  40. u8 reg00;
  41. u8 reg01;
  42. u8 reg02;
  43. u8 reg35;
  44. u8 reg80;
  45. u8 reg82;
  46. u32 output;
  47. v4l2_std_id std;
  48. };
  49. static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
  50. {
  51. return container_of(sd, struct adv7343_state, sd);
  52. }
  53. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  54. {
  55. return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
  56. }
  57. static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
  58. {
  59. struct i2c_client *client = v4l2_get_subdevdata(sd);
  60. return i2c_smbus_write_byte_data(client, reg, value);
  61. }
  62. static const u8 adv7343_init_reg_val[] = {
  63. ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
  64. ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
  65. ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
  66. ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
  67. ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
  68. ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
  69. ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
  70. ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
  71. ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
  72. ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
  73. ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
  74. ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
  75. ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
  76. ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
  77. ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
  78. ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
  79. ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
  80. ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
  81. ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
  82. ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
  83. };
  84. /*
  85. * 2^32
  86. * FSC(reg) = FSC (HZ) * --------
  87. * 27000000
  88. */
  89. static const struct adv7343_std_info stdinfo[] = {
  90. {
  91. /* FSC(Hz) = 3,579,545.45 Hz */
  92. SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
  93. }, {
  94. /* FSC(Hz) = 3,575,611.00 Hz */
  95. SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
  96. }, {
  97. /* FSC(Hz) = 3,582,056.00 */
  98. SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
  99. }, {
  100. /* FSC(Hz) = 4,433,618.75 Hz */
  101. SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
  102. }, {
  103. /* FSC(Hz) = 4,433,618.75 Hz */
  104. SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
  105. }, {
  106. /* FSC(Hz) = 4,433,618.75 Hz */
  107. SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
  108. }, {
  109. /* FSC(Hz) = 4,433,618.75 Hz */
  110. SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
  111. },
  112. };
  113. static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
  114. {
  115. struct adv7343_state *state = to_state(sd);
  116. struct adv7343_std_info *std_info;
  117. int output_idx, num_std;
  118. char *fsc_ptr;
  119. u8 reg, val;
  120. int err = 0;
  121. int i = 0;
  122. output_idx = state->output;
  123. std_info = (struct adv7343_std_info *)stdinfo;
  124. num_std = ARRAY_SIZE(stdinfo);
  125. for (i = 0; i < num_std; i++) {
  126. if (std_info[i].stdid & std)
  127. break;
  128. }
  129. if (i == num_std) {
  130. v4l2_dbg(1, debug, sd,
  131. "Invalid std or std is not supported: %llx\n",
  132. (unsigned long long)std);
  133. return -EINVAL;
  134. }
  135. /* Set the standard */
  136. val = state->reg80 & (~(SD_STD_MASK));
  137. val |= std_info[i].standard_val3;
  138. err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
  139. if (err < 0)
  140. goto setstd_exit;
  141. state->reg80 = val;
  142. /* Configure the input mode register */
  143. val = state->reg01 & (~((u8) INPUT_MODE_MASK));
  144. val |= SD_INPUT_MODE;
  145. err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
  146. if (err < 0)
  147. goto setstd_exit;
  148. state->reg01 = val;
  149. /* Program the sub carrier frequency registers */
  150. fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
  151. reg = ADV7343_FSC_REG0;
  152. for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
  153. err = adv7343_write(sd, reg, *fsc_ptr);
  154. if (err < 0)
  155. goto setstd_exit;
  156. }
  157. val = state->reg80;
  158. /* Filter settings */
  159. if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
  160. val &= 0x03;
  161. else if (std & ~V4L2_STD_SECAM)
  162. val |= 0x04;
  163. err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
  164. if (err < 0)
  165. goto setstd_exit;
  166. state->reg80 = val;
  167. setstd_exit:
  168. if (err != 0)
  169. v4l2_err(sd, "Error setting std, write failed\n");
  170. return err;
  171. }
  172. static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
  173. {
  174. struct adv7343_state *state = to_state(sd);
  175. unsigned char val;
  176. int err = 0;
  177. if (output_type > ADV7343_SVIDEO_ID) {
  178. v4l2_dbg(1, debug, sd,
  179. "Invalid output type or output type not supported:%d\n",
  180. output_type);
  181. return -EINVAL;
  182. }
  183. /* Enable Appropriate DAC */
  184. val = state->reg00 & 0x03;
  185. if (output_type == ADV7343_COMPOSITE_ID)
  186. val |= ADV7343_COMPOSITE_POWER_VALUE;
  187. else if (output_type == ADV7343_COMPONENT_ID)
  188. val |= ADV7343_COMPONENT_POWER_VALUE;
  189. else
  190. val |= ADV7343_SVIDEO_POWER_VALUE;
  191. err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
  192. if (err < 0)
  193. goto setoutput_exit;
  194. state->reg00 = val;
  195. /* Enable YUV output */
  196. val = state->reg02 | YUV_OUTPUT_SELECT;
  197. err = adv7343_write(sd, ADV7343_MODE_REG0, val);
  198. if (err < 0)
  199. goto setoutput_exit;
  200. state->reg02 = val;
  201. /* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
  202. val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
  203. err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
  204. if (err < 0)
  205. goto setoutput_exit;
  206. state->reg82 = val;
  207. /* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
  208. * zero */
  209. val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
  210. err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
  211. if (err < 0)
  212. goto setoutput_exit;
  213. state->reg35 = val;
  214. setoutput_exit:
  215. if (err != 0)
  216. v4l2_err(sd, "Error setting output, write failed\n");
  217. return err;
  218. }
  219. static int adv7343_log_status(struct v4l2_subdev *sd)
  220. {
  221. struct adv7343_state *state = to_state(sd);
  222. v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
  223. v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
  224. ((state->output == 1) ? "Component" : "S-Video"));
  225. return 0;
  226. }
  227. static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
  228. {
  229. struct v4l2_subdev *sd = to_sd(ctrl);
  230. switch (ctrl->id) {
  231. case V4L2_CID_BRIGHTNESS:
  232. return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
  233. ctrl->val);
  234. case V4L2_CID_HUE:
  235. return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
  236. case V4L2_CID_GAIN:
  237. return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
  238. }
  239. return -EINVAL;
  240. }
  241. static int adv7343_g_chip_ident(struct v4l2_subdev *sd,
  242. struct v4l2_dbg_chip_ident *chip)
  243. {
  244. struct i2c_client *client = v4l2_get_subdevdata(sd);
  245. return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7343, 0);
  246. }
  247. static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
  248. .s_ctrl = adv7343_s_ctrl,
  249. };
  250. static const struct v4l2_subdev_core_ops adv7343_core_ops = {
  251. .log_status = adv7343_log_status,
  252. .g_chip_ident = adv7343_g_chip_ident,
  253. .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
  254. .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
  255. .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
  256. .g_ctrl = v4l2_subdev_g_ctrl,
  257. .s_ctrl = v4l2_subdev_s_ctrl,
  258. .queryctrl = v4l2_subdev_queryctrl,
  259. .querymenu = v4l2_subdev_querymenu,
  260. };
  261. static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
  262. {
  263. struct adv7343_state *state = to_state(sd);
  264. int err = 0;
  265. if (state->std == std)
  266. return 0;
  267. err = adv7343_setstd(sd, std);
  268. if (!err)
  269. state->std = std;
  270. return err;
  271. }
  272. static int adv7343_s_routing(struct v4l2_subdev *sd,
  273. u32 input, u32 output, u32 config)
  274. {
  275. struct adv7343_state *state = to_state(sd);
  276. int err = 0;
  277. if (state->output == output)
  278. return 0;
  279. err = adv7343_setoutput(sd, output);
  280. if (!err)
  281. state->output = output;
  282. return err;
  283. }
  284. static const struct v4l2_subdev_video_ops adv7343_video_ops = {
  285. .s_std_output = adv7343_s_std_output,
  286. .s_routing = adv7343_s_routing,
  287. };
  288. static const struct v4l2_subdev_ops adv7343_ops = {
  289. .core = &adv7343_core_ops,
  290. .video = &adv7343_video_ops,
  291. };
  292. static int adv7343_initialize(struct v4l2_subdev *sd)
  293. {
  294. struct adv7343_state *state = to_state(sd);
  295. int err = 0;
  296. int i;
  297. for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
  298. err = adv7343_write(sd, adv7343_init_reg_val[i],
  299. adv7343_init_reg_val[i+1]);
  300. if (err) {
  301. v4l2_err(sd, "Error initializing\n");
  302. return err;
  303. }
  304. }
  305. /* Configure for default video standard */
  306. err = adv7343_setoutput(sd, state->output);
  307. if (err < 0) {
  308. v4l2_err(sd, "Error setting output during init\n");
  309. return -EINVAL;
  310. }
  311. err = adv7343_setstd(sd, state->std);
  312. if (err < 0) {
  313. v4l2_err(sd, "Error setting std during init\n");
  314. return -EINVAL;
  315. }
  316. return err;
  317. }
  318. static int adv7343_probe(struct i2c_client *client,
  319. const struct i2c_device_id *id)
  320. {
  321. struct adv7343_state *state;
  322. int err;
  323. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  324. return -ENODEV;
  325. v4l_info(client, "chip found @ 0x%x (%s)\n",
  326. client->addr << 1, client->adapter->name);
  327. state = kzalloc(sizeof(struct adv7343_state), GFP_KERNEL);
  328. if (state == NULL)
  329. return -ENOMEM;
  330. state->reg00 = 0x80;
  331. state->reg01 = 0x00;
  332. state->reg02 = 0x20;
  333. state->reg35 = 0x00;
  334. state->reg80 = ADV7343_SD_MODE_REG1_DEFAULT;
  335. state->reg82 = ADV7343_SD_MODE_REG2_DEFAULT;
  336. state->output = ADV7343_COMPOSITE_ID;
  337. state->std = V4L2_STD_NTSC;
  338. v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
  339. v4l2_ctrl_handler_init(&state->hdl, 2);
  340. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  341. V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
  342. ADV7343_BRIGHTNESS_MAX, 1,
  343. ADV7343_BRIGHTNESS_DEF);
  344. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  345. V4L2_CID_HUE, ADV7343_HUE_MIN,
  346. ADV7343_HUE_MAX, 1,
  347. ADV7343_HUE_DEF);
  348. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  349. V4L2_CID_GAIN, ADV7343_GAIN_MIN,
  350. ADV7343_GAIN_MAX, 1,
  351. ADV7343_GAIN_DEF);
  352. state->sd.ctrl_handler = &state->hdl;
  353. if (state->hdl.error) {
  354. int err = state->hdl.error;
  355. v4l2_ctrl_handler_free(&state->hdl);
  356. kfree(state);
  357. return err;
  358. }
  359. v4l2_ctrl_handler_setup(&state->hdl);
  360. err = adv7343_initialize(&state->sd);
  361. if (err) {
  362. v4l2_ctrl_handler_free(&state->hdl);
  363. kfree(state);
  364. }
  365. return err;
  366. }
  367. static int adv7343_remove(struct i2c_client *client)
  368. {
  369. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  370. struct adv7343_state *state = to_state(sd);
  371. v4l2_device_unregister_subdev(sd);
  372. v4l2_ctrl_handler_free(&state->hdl);
  373. kfree(state);
  374. return 0;
  375. }
  376. static const struct i2c_device_id adv7343_id[] = {
  377. {"adv7343", 0},
  378. {},
  379. };
  380. MODULE_DEVICE_TABLE(i2c, adv7343_id);
  381. static struct i2c_driver adv7343_driver = {
  382. .driver = {
  383. .owner = THIS_MODULE,
  384. .name = "adv7343",
  385. },
  386. .probe = adv7343_probe,
  387. .remove = adv7343_remove,
  388. .id_table = adv7343_id,
  389. };
  390. module_i2c_driver(adv7343_driver);